JP2684387B2 - Electronic device and manufacturing method thereof - Google Patents
Electronic device and manufacturing method thereofInfo
- Publication number
- JP2684387B2 JP2684387B2 JP63212885A JP21288588A JP2684387B2 JP 2684387 B2 JP2684387 B2 JP 2684387B2 JP 63212885 A JP63212885 A JP 63212885A JP 21288588 A JP21288588 A JP 21288588A JP 2684387 B2 JP2684387 B2 JP 2684387B2
- Authority
- JP
- Japan
- Prior art keywords
- plasma
- electronic device
- molding
- film
- plasma treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01007—Nitrogen [N]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0101—Neon [Ne]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01018—Argon [Ar]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 「産業上の利用分野」 この発明は、半導体装置等の電子装置のワイヤボンデ
ィング後、これら全体にモールド処理を施し、このモー
ルド（樹脂モールドまたはモールド後の樹脂封止をした
ことを示す）剤に外部より水分の浸透を防ぐため、その
表面に緻密層を設けたものである。本発明は、そのた
め、非生成物気体（分解して固体の反応生成物を成膜し
ない気体）を用いてプラズマ処理を施し、モールド剤の
表面を緻密層に変成する、または緻密層をモールド材の
表面に形成せんとしたものである。DETAILED DESCRIPTION OF THE INVENTION “Industrial field of application” The present invention relates to an electronic device such as a semiconductor device, which is wire-bonded and then subjected to a molding treatment on the whole of the electronic device, and the mold (resin molding or resin sealing after molding is performed. In order to prevent the permeation of moisture into the agent, the dense layer is provided on the surface of the agent. Therefore, the present invention, therefore, performs plasma treatment using a non-product gas (a gas that does not decompose to form a solid reaction product into a film) to transform the surface of the molding agent into a dense layer, or to form the dense layer into a molding material. It is formed on the surface of.
プラスチック・モールド・パッケージは一般に信頼性
を低下させる水等がモールド剤中に外部より浸透し、リ
ードフレームのダイの裏面に集まる傾向がある。そして
この水分は、半田付（一般に260℃、３〜10秒の溶融半
田中への浸漬を行う）の際、急激に気化し、その結果、
この加熱により柔らかくなったモールド剤が膨張してモ
ールド剤自体にクラックまたはふくれを誘発する。この
発明は、このクラックの発生を防ぐため、ダイとそれに
密着するモールド剤または保護膜との密着性を向上させ
ることにより、クラック、ふくれ（ダイの裏面側のモー
ルド剤が半田付の際の温度上昇のため、ダイ近傍の水の
気化により膨れてしまう現象をいう）の発生を防がんと
したものである。In the plastic mold package, water or the like which generally lowers reliability tends to permeate the molding agent from the outside and collect on the back surface of the lead frame die. Then, this water vaporizes rapidly during soldering (generally, it is immersed in molten solder at 260 ° C. for 3 to 10 seconds), and as a result,
The heating causes the softened molding material to expand and induce cracks or blisters in the molding material itself. In order to prevent the occurrence of this crack, the present invention improves the adhesiveness between the die and the molding agent or protective film that adheres to it, so that cracks and blisters (the temperature when the molding agent on the back side of the die is soldered) Due to the rise, the phenomenon of swelling due to vaporization of water near the die) is prevented.
この発明は、モールド工程後のモールド剤に対し、ア
ルゴンガス等の不活性気体また弗化物気体によるプラズ
マ処理、またはモールド剤上に窒化珪素、DLC（ダイヤ
モンド状炭素）等の水のモールド剤中へ浸透することを
防ぐいわゆる劣化防止用の保護膜形成（ファイナル・コ
ーティング）をウエハ・レベルにて行うのではなく、電
子部品外側をモールド処理（有機樹脂でモールド処理）
をした後行わんとしたものである。In this invention, the molding agent after the molding process is subjected to plasma treatment with an inert gas such as argon gas or a fluoride gas, or the molding agent is placed in a water molding agent such as silicon nitride or DLC (diamond-like carbon). Rather than performing a so-called deterioration-preventing protective film (final coating) at the wafer level to prevent permeation, the outside of electronic parts is molded (molded with organic resin).
It was done after doing.
「従来の技術」 従来のフレームのリード（35）およびフレームのダイ
が第４図に示されている。図面において、ICチップ（2
8）がダイアタッチされるダイ（35′）は、銅、42アロ
イ等の金属よりなり、この表面（裏面）には、電子部品
（28）をダイアタッチ（24）させる際の100〜350℃の熱
処理の時、低級酸化物（32）が形成されてしまう。この
ため、この後、ただちに有機樹脂のモールド剤（41）に
よるモールド処理を行うと、モールド剤と銅または42ア
ロイとの間にきわめてはがれやすい酸化物層（32）が残
存してしまう。この電子装置を長期間保存しておくと、
大気よりの水分をモールド剤が吸収し、酸化物（32）の
近傍に集まってしまう。そのため、その後工程の260
℃、３〜10秒の半田付の際の急激な熱衝撃に耐えること
ができず、ダイの周辺部のモールド剤にクラック（3
3），（33′）が発生したり、またダイの裏面にたまっ
た水分が蒸気化してボイド（42）ができ、裏面のモール
ド剤にふくれ（41′）が発生してしまった。そしてPCB
上にマウントされた後における長期間の使用に対し、ク
ラック箇所よりの水、不純物の侵入による半導体装置の
特性劣化、信頼性低下を誘発してしまっていた。"Prior Art" A conventional frame lead (35) and frame die are shown in FIG. In the drawing, the IC chip (2
The die (35 ') to which 8) is die attached is made of metal such as copper or 42 alloy, and the front surface (back surface) is 100 to 350 ° C when the electronic component (28) is die attached (24). During the heat treatment, the lower oxide (32) is formed. For this reason, if the molding process with the organic resin molding agent (41) is immediately performed thereafter, the oxide layer (32) that is extremely easily peeled off remains between the molding agent and the copper or 42 alloy. If you store this electronic device for a long time,
Moisture from the atmosphere is absorbed by the molding agent and collects in the vicinity of the oxide (32). Therefore, the subsequent process 260
It cannot withstand a sudden thermal shock when soldering at 3 ℃ for 10 seconds, and cracks (3
3) and (33 ') were generated, and the water accumulated on the back surface of the die was vaporized to form voids (42), causing blisters (41') in the backside molding agent. And PCB
When used for a long period of time after being mounted on the semiconductor device, the characteristics of the semiconductor device are deteriorated and the reliability is lowered due to the intrusion of water and impurities from the cracked portion.
「発明の構成」 本発明はかかる従来のDIPにおきる信頼性の低下を防
ぐため、モールド処理を完了した後、これらモールド剤
上表面部に水分の浸入を防ぐ緻密層を設けたものであ
る。この緻密な層を設けるための手段として、これら全
体をアルゴン等のプラズマ処理により表面近傍の有機樹
脂モールドをプラズマ硬化せしめる方法、およびこの表
面に水分の浸透を防ぐ窒化珪素膜またはDLC膜をプラズ
マCVD法によりコートし保護膜としたことを特徴として
いる。[Structure of the Invention] In order to prevent the deterioration of the reliability of the conventional DIP, the present invention provides a dense layer for preventing the infiltration of moisture on the upper surface of these molding agents after the completion of the molding process. As a means for providing this dense layer, a method of plasma-curing the organic resin mold in the vicinity of the surface by plasma treatment of argon or the like on the whole, and a silicon nitride film or a DLC film for preventing the permeation of moisture on the surface by plasma CVD It is characterized by being coated by a method to form a protective film.
本発明においては、さらにこのモールド剤を形成する
前に、プラズマ処理を用いてリードフレームおよびチッ
プ全体を窒化珪素膜等で覆ってしまうことにより、より
高信頼性の電子装置を作ってもよい。In the present invention, a further highly reliable electronic device may be manufactured by covering the entire lead frame and the chip with a silicon nitride film or the like by using plasma treatment before forming the molding agent.
第１図は本発明構造のプラスチックDIP（デュアルイ
ンライン型パッケイジ）またはフラットパックパッケイ
ジの縦断面図を示す。FIG. 1 shows a longitudinal sectional view of a plastic DIP (dual in-line type package) or flat pack package of the structure of the present invention.
図面において、リードフレームのダイ（35′）に銀ペ
ースト（24）等で密着させた電子部品チップ（28）と、
このチップのアルミニューム・パッド（38）と金属リー
ド（ステム）（35）との間に金線（39）のワイヤボンド
を行った。In the drawing, an electronic component chip (28) adhered to a lead frame die (35 ') with a silver paste (24) or the like,
A gold wire (39) was wire-bonded between the aluminum pad (38) and the metal lead (stem) (35) of this chip.
さらに高信頼性化のため、このチップ（28）表面、パ
ッド（38）表面、ワイヤ（39）表面およびダイ（35′）
の裏面に対し、非生成物気体のプラズマ処理により、ダ
イアタッチの際発生した低級酸化物およびナチュラルオ
キサイトを除去し、金属表面を露呈（30）させ、これら
上に劣化防止用保護膜、特に窒化珪素膜（27），（2
7′）のプラズマCVD法によるコーティングを行う。For higher reliability, this chip (28) surface, pad (38) surface, wire (39) surface and die (35 ')
On the back surface of the non-product gas, plasma treatment of non-product gas removes the lower oxides and natural oxides generated at the time of die attachment to expose the metal surface (30), and a protective film for deterioration prevention, especially on these. Silicon nitride film (27), (2
7 ') Plasma CVD method is applied.
かくの如くして、窒化珪素膜の如き劣化防止用保護膜
を300〜5000Å、一般には約1000Åの厚さに形成した
後、公知のインジェクション・モールド法により有機樹
脂例えばエポキシ（例えば410B）モールド法により注入
・封止させた。さらにフレームをリード部（37）にて曲
げ、かつタイバーを切断する。さらにリード部を酸洗い
を行った後、リードにハンダメッキを行った。Thus, after forming a protective film for preventing deterioration such as a silicon nitride film to a thickness of 300 to 5000Å, generally about 1000Å, an organic resin such as an epoxy (for example 410B) molding method by a known injection molding method. Was injected and sealed. Further, the frame is bent at the lead portion (37) and the tie bar is cut. Further, the leads were pickled and then the leads were solder-plated.
これらの後、本発明のモールド剤（41）の表面および
裏面全体に対し、水の浸透を防ぎ緻密層（43）を形成す
る。モールド剤（41）中には信頼性低下をさせる有機物
気体、塩素、水分がモールドの際存在する。これらを除
去するため、これら全体をまず真空引きをして外部に除
去する。そしてこの表面にプラズマ処理を行う。After that, the dense layer (43) is formed to prevent water from permeating the entire front and back surfaces of the molding agent (41) of the present invention. In the molding agent (41), organic gas, chlorine, and water that reduce reliability are present during molding. In order to remove them, the whole of them is first evacuated and removed to the outside. Then, plasma treatment is performed on this surface.
この本発明のプラズマ処理方法はアルゴン、ネオン、
ヘリウム、クリプトン等の不活性物気体、または弗化窒
素、弗化炭素、窒素を用いてもよい。実験的には、質量
が大きくかつ比較的安価でプラズマ化しやすい気体であ
るアルゴンが好ましい。これを後述の第２図の如きプラ
ズマ処理装置を用い、プラズマ処理を行った。かくして
緻密層（43）を形成した。またこれに引き続き、これら
全体にプラズマCVD法によりDLC膜また窒化珪素膜を0.1
〜１μの厚さに保護膜（43′）として形成した。This plasma processing method of the present invention is performed by using argon, neon,
An inert gas such as helium or krypton, or nitrogen fluoride, carbon fluoride, or nitrogen may be used. Experimentally, it is preferable to use argon, which is a gas having a large mass, relatively inexpensive, and easily turned into plasma. This was subjected to plasma treatment using a plasma treatment apparatus as shown in FIG. 2 described later. Thus, a dense layer (43) was formed. Further, subsequently to this, a DLC film or a silicon nitride film is formed on the entire surface by a plasma CVD method.
It was formed as a protective film (43 ') with a thickness of ~ 1μ.
この窒化珪素膜の如き保護膜は室温において、珪素物
気体とアンモニアまたは窒素とをプラズマ反応炉に導入
し、そこに電気エネルギを供給するいわゆるプラズマ気
相法により形成せしめた。DLC膜はエチレンのプラズマC
VD法により室温で形成した。この中に弗化窒素を混入
し、熱膨張の調整を行うことは有効である。The protective film such as the silicon nitride film was formed at room temperature by a so-called plasma vapor phase method in which a silicon gas and ammonia or nitrogen were introduced into a plasma reactor and electric energy was supplied to the plasma reactor. DLC film is plasma C of ethylene
It was formed at room temperature by the VD method. It is effective to mix nitrogen fluoride into this to adjust the thermal expansion.
第２図は、本発明のチップがフレームにボンディング
されモールド剤のコートがなされたフラットパック構造
の基板およびそれを複数個集合させた基体（２）（基板
および基体をまとめて基体とも以下では略記する）を複
数配設させ、プラズマ処理方法により有機樹脂モールド
のプラズマ硬化処理またはプラズマCVD法により、窒化
珪素膜またはDLC膜のコーティングを行うための装置の
概要を示す。FIG. 2 shows a substrate having a flat pack structure in which the chip of the present invention is bonded to a frame and coated with a molding agent and a plurality of bases (2) (both the substrate and the base are collectively referred to as a base hereinafter). The outline of an apparatus for coating a silicon nitride film or a DLC film by a plasma hardening method of an organic resin mold by a plasma processing method or a plasma CVD method will be described.
図面において、反応系（６），ドーピング系（５）を
有している。The drawing has a reaction system (6) and a doping system (5).
反応系は、反応室（１）と予備室（７）とを有し、ゲ
ード弁（８），（９）とを有している。反応室（１）は
内側に供給側フード（13）を有し、入口側（３）からの
反応性気体をフード（14）のノズル（13）より下方向に
吹き出し、プラズマ反応をさせ、基板または基体（２）
上での低級酸化物の除去および保護膜形成を行った。プ
ラズマ処理または反応後は排出側フード（14′）のノズ
ル（13′）より排気口（４）を経てバルブ（21），真空
ポンプ（20）に至る。高周波電源（10）よりの電気エネ
ルギは、マッチングトランス（26）をへて、１〜500MHz
例えば13.56MHzの周波数を上下間の一対の同じ大きさの
網状電極（11），（11′）に加える。さらにマッチング
トランスの中点（25′）は接地レベル（25）とした。ま
た周辺の枠構造のホルダ（40）は導体の場合は接地レベ
ル（22）とし、また絶縁体であってもよい。そして反応
性気体は、一対の電極（11），（12）により供給された
高周波エネルギにより励起させている。またプラズマ処
理およびプラズマCVD法において、被形成体（２）（以
下基体（２）という）はサポータ（40′）上に配設され
た枠構造のホルダ（40）内に一対の電極間の電界の方向
に平行に、さらに、いずれの電極（11），（12）からも
離間させている。そして複数の基体（２）は互いに一定
の間隔（２〜13cm例えば6cm）または概略一定の間隔を
有して配設されている。この多数の基体（２）は、グロ
ー放電により作られるプラズマ中の陽光柱内に配設され
る。この基体の要部を第３図（Ｃ）に示す。The reaction system has a reaction chamber (1) and a preliminary chamber (7), and has gated valves (8) and (9). The reaction chamber (1) has a supply side hood (13) inside, and a reactive gas from the inlet side (3) is blown downward from a nozzle (13) of the hood (14) to cause a plasma reaction and a substrate. Or substrate (2)
Removal of the lower oxide and formation of a protective film were performed. After the plasma treatment or reaction, it reaches the valve (21) and the vacuum pump (20) from the nozzle (13 ') of the discharge hood (14') through the exhaust port (4). The electric energy from the high frequency power supply (10) goes through the matching transformer (26) to 1 ~ 500MHz.
For example, a frequency of 13.56 MHz is applied to a pair of upper and lower mesh electrodes (11) and (11 ') of the same size. Furthermore, the midpoint (25 ') of the matching transformer was set to the ground level (25). Further, the holder (40) of the peripheral frame structure is the ground level (22) in the case of a conductor, and may be an insulator. The reactive gas is excited by the high frequency energy supplied by the pair of electrodes (11) and (12). In the plasma processing and the plasma CVD method, an object to be formed (2) (hereinafter referred to as a substrate (2)) is placed in a frame-shaped holder (40) provided on a supporter (40 ') and an electric field between a pair of electrodes is formed. In parallel with the direction of, the electrodes (11) and (12) are separated from each other. The plurality of bases (2) are arranged at regular intervals (2 to 13 cm, for example 6 cm) or at regular intervals. The multiple substrates (2) are arranged in a positive column in a plasma created by glow discharge. The main part of this substrate is shown in FIG.
第３図（Ａ）は基体（２）において基体（35），（3
5′）を複数個一体化した金属リードフレーム上（45）
に電子装置（28）がボンディングされたモールド処理後
の電子装置（29）を５〜25ケ、ユニット化したフレーム
（45）を有する。そして複数の電子部品、例えば半導体
チップがボンディングされモールド処理された１本のフ
レーム（45）における１つの電子装置のある部分のフレ
ーム（基板）を第３図（Ｂ）に示す。そしてこのＡ−
Ａ′での縦断面図を第３図（Ｃ）の（29）に示す。第３
図（Ｃ）において、リードフレーム（35），ダイ（3
5′），半導体チップ（28），金属ワイヤ（39）、モー
ルド剤（41）よりなる電子装置を５〜25ケユニット化し
たフレーム（45−１），（45−２）・・・をさらに５〜
300本集め、ジグ（44）により一体化シ、基体（２）と
して構成させている。この基体（２）が第２図における
基体（２）に対応している。そしてこれをさらに５〜50
枚（図面では７枚）陽光柱内に第２図では配設してい
る。FIG. 3 (A) shows the base body (2) with the base bodies (35) and (3).
On a metal lead frame with multiple 5 ') integrated (45)
The frame (45) is formed by uniting 5 to 25 electronic devices (29) after the molding process, to which the electronic device (28) is bonded. FIG. 3 (B) shows a frame (substrate) of a portion of one frame (45) on which a plurality of electronic components, for example, semiconductor chips are bonded and molded, is provided with one electronic device. And this A-
A vertical sectional view taken along line A'is shown in FIG. 3 (C) at (29). Third
In the figure (C), the lead frame (35) and the die (3
5 '), a semiconductor chip (28), a metal wire (39), and a frame (45-1), (45-2) ... ~
300 pieces are gathered and integrated as a base body (2) by a jig (44). This base body (2) corresponds to the base body (2) in FIG. And 5 to 50 more
Two (7 in the drawing) are arranged in a positive column in FIG.
第２図における反応性気体は、フード（13）より枠構
造のホルダ（40）の内側およびフード（13′）により囲
まれた内側にてプラズマ活性状態を呈し、モールド剤上
をプラズマ処理して緻密層を形成する。さらにこのモー
ルド剤上に保護膜としての緻密層形成がなされる。The reactive gas in FIG. 2 is in a plasma activated state inside the holder (40) having a frame structure and inside the hood (13 ') from the hood (13), and plasma treatment is performed on the molding agent. Form a dense layer. Further, a dense layer as a protective film is formed on this molding agent.
第２図に示すごとき本発明方法におけるプラズマ処理
方法は、室温のアルゴンプラズマ陽光柱内に保持され、
かつ非生成物気体のプラズマ処理また生成物気体を用い
たDLC膜、窒化珪素膜を形成するに際し、外部より加熱
をしなくても充分に緻密な層を作ることができる。The plasma treatment method in the method of the present invention as shown in FIG. 2 is held in an argon plasma positive column at room temperature,
In addition, when performing plasma treatment of non-product gas or forming a DLC film or a silicon nitride film using a product gas, a sufficiently dense layer can be formed without external heating.
そのプロセス上の実施例を以下に示す。 An example of the process is shown below.
「実施例１」 第２図のプラズマ処理装置およびCVD装置において、
ドーピング系（５）は珪化物気体であるジシラン（Si2H
6）を（17）より、また窒化物気体であるアンモニアま
たは窒素を（16）より、プラズマ処理用の非生成物気体
であるアルゴンを（15）より供給している。それらは流
量計（18），バルブ（19）により制御されている。"Example 1" In the plasma processing apparatus and the CVD apparatus of FIG.
The doping system (5) is disilane (Si 2 H
6 ) is supplied from (17), nitride gas ammonia or nitrogen is supplied from (16), and non-product gas argon for plasma treatment is supplied from (15). They are controlled by a flow meter (18) and a valve (19).
例えば、基板温度は外部加熱を特に積極的に行わない
室温（プラズマによる自己加熱を含む）とした。そして
まず反応空間（１）に第３図に示したモールド処理後の
基体を保持し、アルゴンを導入した。そしてこれら全体
を１×10-1torr以下（10〜30分）に真空引きをし、モー
ルド剤中の有機ガス、塩素、水分を脱気した。そして、
基体（２）の特にモールド剤（41）表面のプラズマ処理
を行った。即ちこれらアルゴンに対し、13.56MHzの周波
数により1KWの出力を一対の電極（11），（11′）に10
〜30分供給してプラズマ化した。すると第３図に示した
このモールド剤（41）の表面に第１図に示す如く、緻密
層（43）を作ることができた。For example, the substrate temperature is set to room temperature (including self-heating by plasma) in which external heating is not particularly positively performed. Then, first, the substrate after the mold treatment shown in FIG. 3 was held in the reaction space (1), and argon was introduced. Then, the whole of these was evacuated to 1 × 10 -1 torr or less (10 to 30 minutes) to degas organic gas, chlorine, and water in the molding agent. And
Plasma treatment was performed on the surface of the base material (2), especially on the surface of the molding agent (41). That is, with respect to these argon, the output of 1 KW is applied to the pair of electrodes (11) and (11 ') at a frequency of 13.56MHz.
It was supplied for about 30 minutes and turned into plasma. Then, as shown in FIG. 1, a dense layer (43) could be formed on the surface of the molding agent (41) shown in FIG.
この緻密層を有する電子装置の工業的効果を調べるた
め、85℃/85％（相対湿度）で24時間放置し、半田付け
（260℃,5秒）を行った。その結果、このサンプルを50
ケ試みたが、クラック、フクレはまったくみられなかっ
た。しかし85℃/85％の条件を1000時間保持した試料の
半田付処理をすると、不良は50ケ中10ケみられた。もち
ろん本発明方法をまったく行わない緻密層のない電子装
置の信頼性試験を行った場合は、50ケのすべてが不良に
なった。In order to investigate the industrial effect of the electronic device having this dense layer, it was left at 85 ° C / 85% (relative humidity) for 24 hours and soldered (260 ° C, 5 seconds). As a result, this sample is 50
I tried, but no cracks or blisters were seen. However, when the soldering treatment of the sample kept at 85 ° C / 85% for 1000 hours was found, 10 out of 50 defects were found. Of course, when a reliability test of an electronic device without a dense layer was performed without performing the method of the present invention, all 50 were defective.
「実施例２」 この実施例は実施例１のプラズマ処理を行った基体に
対し、さらに保護膜形成を行ったものである。即ち、実
施例１に示す如きプラズマ処理がなされた被形成面上に
窒化珪素膜を形成する場合、反応性気体は例えば、NH3
／Si2H6／N2＝1/3/5とした。即ちこれらアルゴンに対
し、13.56MHzの周波数により1KWの出力を一対の電極（1
1），（11′）に供給した。かくして平均5000Å（5000
ű200Å）に約30分（平均速度3A/秒）の被膜形成を行
った。"Example 2" In this example, a protective film was further formed on the substrate which was subjected to the plasma treatment of Example 1. That is, when the silicon nitride film is formed on the surface to be plasma-treated as shown in Example 1, the reactive gas is, for example, NH 3
/ Si 2 H 6 / N 2 = 1/3/5. That is, for these argon, a 1 KW output at a frequency of 13.56 MHz is applied to a pair of electrodes (1
It was supplied to 1) and (11 '). Thus an average of 5000Å (5000
The film was formed on Å ± 200Å) for about 30 minutes (average speed 3A / sec).
窒化珪素膜はその絶縁耐圧８×106V/cm以上を有し、
比抵抗は２×1015Ωcmであった。赤外線吸収スペクトル
では864cm-1のSi−Ｎ結合の吸収ピークを有し、屈折率
は2.0であった。The silicon nitride film has a withstand voltage of 8 × 10 6 V / cm or more,
The specific resistance was 2 × 10 15 Ωcm. In the infrared absorption spectrum, it had an absorption peak of Si—N bond at 864 cm −1 and had a refractive index of 2.0.
かかる本発明方法で作られた電子装置に対し、85℃/8
5％（相対温度）で1000時間放置して、その後、半田付
けを260℃５秒行った。しかしこのモールドには何らの
クラックもまたふくれも発生しなかった。For an electronic device made by such a method of the present invention, 85 ° C / 8
It was left for 1000 hours at 5% (relative temperature), and then soldering was performed at 260 ° C. for 5 seconds. However, neither crack nor swelling occurred in this mold.
ホルダ（40）は枠の内側の大きさ60cm×60cmを有し、
電極間距離は30cm（有効20cm）としている。また第２図
の基体（２）の部分を拡大した図面を第３図に示す。The holder (40) has a size of 60 cm x 60 cm inside the frame,
The distance between the electrodes is 30 cm (effective 20 cm). FIG. 3 is an enlarged view of a portion of the base (2) in FIG.
なお本発明においては、プラズマ処理方法およびPCVD
法において、電気エネルギのみならず、10〜15μの波長
の遠赤外線または300nm以下の紫外光を同時に加えた光
エネルギを用いるフォトCVD（またはフォトFPCVD）法を
併用することは有効である。In the present invention, the plasma processing method and PCVD
In the method, it is effective to use not only electric energy but also photo-CVD (or photo-FPCVD) method in which far infrared rays having a wavelength of 10 to 15 μm or light energy to which ultraviolet light of 300 nm or less is added at the same time.
「効果」 本発明において、モールド上のプラズマ処理のみとす
ると、リードフレーム上に何らの不用物の付着がなく、
反応炉内に常に清潔なため、量産性に優れていた。しか
し超高信頼性に対しては不十分であった。他方、モール
ド上の緻密膜としてブロッキング膜を形成する場合、超
高信頼性を有していた。しかし成膜の際、リード上への
コートを防ぐジグを作る必要があり、またCVD後プラズ
マ装置内をクリーニングする工程を必要とする。本発明
は加熱に必要な電力、時間がいらず、生産性に優れてい
る。加えて、プラズマ処理を行う際、モールド剤中の不
純物ガス、水分の真空脱気工程を有するため、有機樹脂
中の水分、塩素とダイの金属との間で反応を起こして低
級酸化物ができ、信頼性を低下させるという欠点がな
い。そしてこの電子装置のPCBへの半導体による装着の
際、従来例に示す如く、モールド材が加熱により膨れて
しまうことを防ぐことができた。[Effect] In the present invention, when only the plasma treatment on the mold is performed, there is no adhesion of unnecessary matter on the lead frame,
Since it was always clean inside the reactor, it was excellent in mass production. However, it was insufficient for ultra-high reliability. On the other hand, when forming a blocking film as a dense film on the mold, it had an extremely high reliability. However, during film formation, it is necessary to form a jig that prevents coating on the leads, and a step of cleaning the inside of the plasma device after CVD is required. The present invention does not require electric power and time required for heating and is excellent in productivity. In addition, when performing the plasma treatment, since there is a vacuum degassing step of the impurity gas and moisture in the molding compound, the moisture in the organic resin, chlorine reacts with the metal of the die to form a lower oxide. , There is no drawback of reducing reliability. Then, when the electronic device was mounted on the PCB by the semiconductor, it was possible to prevent the molding material from swelling due to heating, as shown in the conventional example.
本発明における保護膜は窒化珪素膜とした。しかしこ
れはDLC（ダイヤモンド・ライク・カーボン）膜、酸化
珪素膜、その他の絶縁膜の単層または多層膜であっても
よい。The protective film in the present invention was a silicon nitride film. However, this may be a single layer or a multilayer film of a DLC (diamond-like carbon) film, a silicon oxide film, or another insulating film.
酸化珪素は本来吸水性を有するため、窒化珪素、DLC
ほどの長期間の耐水信頼性を期待できない。Since silicon oxide inherently has water absorbability, silicon nitride, DLC
It cannot be expected to have water resistance for a long time.
さらに本発明において、電子部品チップは半導体素子
として示したが、その他、抵抗、コンデンサであっても
よく、ボンディングもワイヤボンディングのみならずフ
リップチップボンディング、ハンダバンプボンディング
でもよい。Further, although the electronic component chip is shown as a semiconductor element in the present invention, it may be a resistor or a capacitor, and the bonding may be not only wire bonding but flip chip bonding or solder bump bonding.
本発明において、チップが大きくなって、ダイを用い
ることなしにモールドする場合がある。しかしその場合
も基体としてのリードフレーム、チップのすべてを覆っ
て保護膜を設けることは有効である。In the present invention, the chip may become larger and may be molded without using a die. However, even in that case, it is effective to provide the protective film to cover all of the lead frame and the chip as the base.
上述した説明においては、リードフレーム上に半導体
チップを埋置した場合について述べているが、本発明は
特に金属リードフレーム上に限ることなく、ハイブリッ
ドIC、厚膜IC等基体上に能動素子または受動する素子を
マウントし、これら全体にモールド処理をした基板また
は基体に対しても、同様の効果が基体できるものであ
る。In the above description, the case where the semiconductor chip is embedded in the lead frame has been described. However, the present invention is not limited to the metal lead frame, and the active element or the passive element may be provided on the substrate such as a hybrid IC or a thick film IC. The same effect can be obtained by mounting a device to be mounted on the substrate and molding the whole of them.
第１図は本発明の耐湿テストおよび半田付けテストをし
た後のプラスチック・パッケージ半導体装置の縦断面部
の要部を示す。 第２図は本発明方法を実施するためのプラズマ気相反応
装置の概要を示す。 第３図は第２図の装置のうちの基体部の拡大図を示す。 第４図は従来例のプラスチックパッケイジを耐湿テスト
および半田付けテストをした後の縦断面図の要部を示
す。FIG. 1 shows a main part of a vertical cross section of a plastic package semiconductor device after a moisture resistance test and a soldering test according to the present invention. FIG. 2 shows an outline of a plasma gas phase reactor for carrying out the method of the present invention. FIG. 3 is an enlarged view of a base portion of the apparatus shown in FIG. FIG. 4 shows an essential part of a vertical cross-sectional view after a moisture resistance test and a soldering test are performed on a conventional plastic package.
Claims (3)
ボンディングさせ、有機樹脂モールドを施した電子装置
において、前記有機樹脂モールドの表面に窒化珪素膜ま
たはDLC膜が設けられたことを特徴とする電子装置。1. An electronic device in which a metal lead of a frame and an electronic component are bonded and an organic resin mold is applied, wherein a silicon nitride film or a DLC film is provided on a surface of the organic resin mold. Electronic device to do.
ボンディングした基板または該基板を集合させた基体に
対し、有機樹脂のモールド封止を施した後、前記有機樹
脂の表面に非生成物気体によりプラズマ処理を施したこ
とを特徴とする電子装置作製方法。2. A non-product on the surface of the organic resin after mold sealing of an organic resin is performed on a substrate in which a metal lead of a frame is bonded to an electronic component or a base body in which the substrates are assembled. A method for manufacturing an electronic device, which is characterized in that plasma treatment is performed with a gas.
処理は外部より加熱することなく施すことを特徴とする
電子装置作製方法。3. A method for manufacturing an electronic device according to claim 2, wherein the plasma treatment is performed without external heating.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63212885A JP2684387B2 (en) | 1988-08-26 | 1988-08-26 | Electronic device and manufacturing method thereof |
| US07/667,231 US5147822A (en) | 1988-08-26 | 1991-02-25 | Plasma processing method for improving a package of a semiconductor device |
| US08/161,859 US6191492B1 (en) | 1988-08-26 | 1993-12-06 | Electronic device including a densified region |
| US09/698,055 US6756670B1 (en) | 1988-08-26 | 2000-10-30 | Electronic device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63212885A JP2684387B2 (en) | 1988-08-26 | 1988-08-26 | Electronic device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0260150A JPH0260150A (en) | 1990-02-28 |
| JP2684387B2 true JP2684387B2 (en) | 1997-12-03 |
Family
ID=16629871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63212885A Expired - Fee Related JP2684387B2 (en) | 1988-08-26 | 1988-08-26 | Electronic device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2684387B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5446620A (en) * | 1990-08-01 | 1995-08-29 | Staktek Corporation | Ultra high density integrated circuit packages |
| AU8519891A (en) * | 1990-08-01 | 1992-03-02 | Staktek Corporation | Ultra high density integrated circuit packages, method and apparatus |
| US6037652A (en) * | 1997-05-29 | 2000-03-14 | Nec Corporation | Lead frame with each lead having a peel generation preventing means and a semiconductor device using same |
| JP4649950B2 (en) * | 2004-10-27 | 2011-03-16 | トヨタ自動車株式会社 | Semiconductor device with cooler |
| JP6344981B2 (en) * | 2014-06-03 | 2018-06-20 | 日立オートモティブシステムズ株式会社 | Manufacturing method of semiconductor module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58199543A (en) * | 1982-05-17 | 1983-11-19 | Toshiba Corp | Package for semiconductor device |
-
1988
- 1988-08-26 JP JP63212885A patent/JP2684387B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0260150A (en) | 1990-02-28 |
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