JPS58199543A - Package for semiconductor device - Google Patents
Package for semiconductor deviceInfo
- Publication number
- JPS58199543A JPS58199543A JP57082810A JP8281082A JPS58199543A JP S58199543 A JPS58199543 A JP S58199543A JP 57082810 A JP57082810 A JP 57082810A JP 8281082 A JP8281082 A JP 8281082A JP S58199543 A JPS58199543 A JP S58199543A
- Authority
- JP
- Japan
- Prior art keywords
- package
- film
- plastic
- nickel
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置のパッケージに関し、特に耐環境
性を向上させたものに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a package for a semiconductor device, and particularly to a package with improved environmental resistance.
半導体装置のパッケージとしては、従来プラスチックパ
ッケージとセラミックパッケージが知られている。Plastic packages and ceramic packages are conventionally known as packages for semiconductor devices.
プラスチックパッケージは、第１図に示すような断面構
造を有しておシ、半導体ペレット１をリードフレーム（
図示せず）上に固定し、半導体ベレット１上の電極とリ
ードフレームの各リード２をワイヤ３のボンディングに
よ多接続したものをフェノール系等のプラスチック樹脂
４で４００℃程度の加熱下で成型したものである。The plastic package has a cross-sectional structure as shown in FIG.
(not shown), and the electrodes on the semiconductor pellet 1 and the leads 2 of the lead frame are connected multiple times by bonding wires 3, and then molded with a plastic resin 4 such as phenolic resin under heating at approximately 400°C. This is what I did.
また、セラミックパッケージは、第２図に示すような断
面構造を有しており、チップ接着のパッドと端子引出し
線をメタライズしたセラ電ツク基板５上にチップ１を接
着し、ワイヤ３のボンディングの後金属またはセラミッ
クのふた６を載せてガラスや金属の溶着によシシールし
たものである。The ceramic package has a cross-sectional structure as shown in FIG. After that, a metal or ceramic lid 6 is placed and sealed by glass or metal welding.
プラスチックパッケージはセ−）ミックパッケージと比
較して、安価で機械的強度に優れ寸法安定性が良いとい
う特長を有することから、最近はセラミックパッケージ
以上に多く使用されている。 ゛〔背景技術の問
題点〕
ところが、プラスチックパッケージにおいては、プラス
チック自体が持つ吸湿性、およびプラスチックとリード
の間の密着が完全になりにくいことから吸湿性、アルカ
リイオン透過性があるため耐環境性に劣り、高湿度雰囲
気中では半導体ペレット上の配線〈腐食を起し↑すいと
いう問題点があり、□こ″の点セラミックパッケージと
比較して不利表意と考えられている。Compared to ceramic packages, plastic packages are cheaper, have superior mechanical strength, and have better dimensional stability, so they have recently been used more frequently than ceramic packages.゛ [Problems with the background technology] However, in plastic packages, the plastic itself has hygroscopic properties, and the adhesion between the plastic and the leads is difficult to achieve, making it hygroscopic and alkali ion permeable, making it difficult to withstand the environment. However, there is a problem in that the wiring on the semiconductor pellet is more likely to corrode in a high humidity atmosphere, and this point is considered to be disadvantageous compared to ceramic packages.
そこで、本発明はプラスチックパッケージの持つ利点を
維持しつつ耐湿性、アルカリイオン阻止性を向上させた
プラスチックパッケージを提供することを目的とする。Therefore, an object of the present invention is to provide a plastic package that maintains the advantages of plastic packages and has improved moisture resistance and alkali ion blocking properties.
本発明は、従来の樹脂モールドによるプラスチックパッ
ケージのほぼ全表面上に少くとも１種類以上の金属又は
金属化合物を被着させたものであり、従来よシ優れた耐
環境性を有するものである。In the present invention, at least one metal or metal compound is coated on almost the entire surface of a conventional resin-molded plastic package, and the package has environmental resistance superior to that of the conventional plastic package.
以下図面を参照しながら本発明のいくつかの実施例につ
き説明する。Some embodiments of the present invention will be described below with reference to the drawings.
第３図は金属皮膜としてニッケル（Ｎｌ）膜ｌＯを成型
樹脂４上に約９μｍ形成した実施例である。FIG. 3 shows an example in which a nickel (Nl) film 1O was formed on the molded resin 4 to a thickness of about 9 μm as a metal film.
この実施例においてはリード間のショートを起さ・ な
いように、リード２とニッケル皮膜１０との間には午れ
らが直接接触しないようすき間が設けてあ′る！
第４図は絶縁体である金属化合物として封孔処□理した
酸化アルミニウム（ＡＩＯ）膜１１を成形樹脂３
４及びリード２上に約１０μｍ形成した実施例である。In this embodiment, a gap is provided between the leads 2 and the nickel film 10 to prevent direct contact between the leads 2 and the nickel film 10 to prevent short circuits between the leads! FIG. 4 shows an example in which a sealed aluminum oxide (AIO) film 11 made of a metal compound which is an insulator is formed on the molded resin 34 and the leads 2 to a thickness of about 10 μm.
この実施例においてはプラスチックパッケージとリード
の境界部を含めてプラスチックパッケージ全体が酸化ア
ルミニウム膜１１で被われてい、る。In this embodiment, the entire plastic package including the boundary between the plastic package and the leads is covered with an aluminum oxide film 11.
第５図は、第４図の実施例で施された酸化アルミニウム
被膜１１の上に更に金属皮膜としてニッケル皮膜１２を
約９μｍ形成した実施例である。FIG. 5 shows an example in which a nickel film 12 of about 9 μm is further formed as a metal film on the aluminum oxide film 11 applied in the example of FIG.
これらの製造は例えば次のように行わ□れる。These products are manufactured, for example, as follows.
（１）ニッケル皮膜の場合
被着前処理としてトリクロルエチレンボイル及び水洗に
よる脱脂洗浄と０２プラズマ処理による表面粗化を行う
。その後第６図に示すよう１′１．’、Ｊ’・１・・１
． ・に被着を要さない部分のマスキングを兼ね
たステンレス製のジグ（（転）１３に装着し、イオンブ
レーティング装置（図示せず）の真空チャンバ内に（３
）
セットしＡｒイオンの衝撃による吸着性分子除去のため
の密着性改善処理を行った後イオンブレーティング法に
よるニッケル蒸着を行う。なお、マスキングを完全にす
るため、ジグ（４）１３とプラスチックパッケージ４と
の間にはシリコンゴム１４による充填を行うことが適当
である。(1) In the case of a nickel film, pre-adhesion treatment includes degreasing by trichlorethylene boiling and water washing, and surface roughening by 02 plasma treatment. Then, as shown in FIG. 6, 1'1. ', J'・1・・1
．．・Attach a stainless steel jig (roller) 13 that also serves as masking of parts that do not require deposition, and place it in the vacuum chamber of an ion blating device (not shown).
) After setting and performing adhesion improvement treatment to remove adsorptive molecules by Ar ion bombardment, nickel deposition is performed by ion blating method. In order to ensure complete masking, it is appropriate to fill the space between the jig (4) 13 and the plastic package 4 with silicone rubber 14.
（２）酸化アルミニウム皮膜の場合
、 ニッケル皮膜の場合と同様の前処理を行った後、表
面粗化をされたプレ・スナックパッケージ４を第８図に
示すようにジグ（Ｂ） １５に装着し、まず真空中でイ
オンブレーティング法によシ約７．５μｍのアルミニウ
ム膜を形成しその後陽極酸化処理により第９図に示され
る約１０ ｐｍの酸化アルミニウム皮膜としさらに耐蝕
性向上のための封孔処理を行って膜特性を向上させてい
る。(2) In the case of aluminum oxide film, after performing the same pretreatment as in the case of nickel film, the surface-roughened pre-snack package 4 is attached to jig (B) 15 as shown in Fig. 8. First, an aluminum film with a thickness of about 7.5 μm was formed by ion blating in vacuum, and then an aluminum oxide film with a thickness of about 10 pm was formed by anodizing, as shown in Figure 9, and the pores were sealed to improve corrosion resistance. Treatment is performed to improve film properties.
（３）酸化アルミニウム皮膜上にニッケル皮膜を施した
場合
（２）において得られた封孔処理前の酸化アルミニウム
皮膜な被着したプラスチックパッケージ４をジグ（Ｃ）
１６に装着し、真空中でイオンプレー（４）
ティング法によるニッケル蒸着を行い、約加μｍのニッ
ケル皮膜を形成させる。(3) When a nickel film is applied on an aluminum oxide film The plastic package 4 with the aluminum oxide film adhered to it before the sealing process obtained in (2) is shown in a jig (C).
16, and perform nickel deposition by ion plating (4) in vacuum to form a nickel film with a thickness of approximately 1.0 μm.
以上のような実施例に対し信頼性試験を行った結果は次
のようであった。The results of a reliability test conducted on the above embodiments were as follows.
信頼性試験は、第１１図に示す幅Ｗが８μｍ１厚さが１
μｍの２本のアルミニウム配線１７を全長４龍にわたっ
て間隔Ｓが１０ ｆｉｍになるようにしたパターンをプ
レスチックパッケージ中に設け、従来のプラスチックパ
ッケージそのまま、ニッケル皮膜を被着したパッケージ
、酸化アルミニウム皮膜を被着したパッケージ、酸化ア
ル膚ニウム皮膜上にニッケル皮膜を被着したパッケージ
の４種類について行った。試験条件は、２．５気□圧の
飽和水蒸気中放置加時間と温度８５’（：における直流
電圧１５Ｖ印加状態放置加時間とを１サイクルとして試
料に加えるものとし、加え九サイクル数に対するアルミ
ニウム配線の腐食による不良の発生率を観察した。In the reliability test, the width W shown in Fig. 11 was 8 μm, the thickness was 1
A pattern in which two aluminum wires 17 of 10 μm are provided over the entire length with a spacing S of 10 fim is provided in a plastic package, and a conventional plastic package is used as is, a package coated with a nickel film, and a package coated with an aluminum oxide film. The test was conducted on four types of packages: a package with a nickel film coated on an aluminum oxide film, and a package with a nickel film coated on an aluminum oxide film. The test conditions were as follows: 1 cycle of exposure time in saturated steam at 2.5 atm pressure and 15V DC voltage application time at a temperature of 85'; The incidence of defects due to corrosion was observed.
結果は第１２図に示されており、プラスチックパッケー
ジ上に金属皮膜又は金属化合物を被着させたものは従来
のプラスチックパッケージより不良発牛車が著しく減少
していることがわかる。The results are shown in FIG. 12, and it can be seen that the number of defective bullock carts is significantly reduced in plastic packages coated with metal films or metal compounds compared to conventional plastic packages.
なお、本発明における被着材料は上記実施例のようなニ
ッケル、酸化アルミニウムに限られるものではなく、い
かなる金属や金属化合物（金属酸化物、金属窒化物等）
でも使用することができる。The material to be adhered in the present invention is not limited to nickel and aluminum oxide as in the above embodiments, but can be any metal or metal compound (metal oxide, metal nitride, etc.).
It can also be used.
またこれらを必要に応じ任意に重ねて被着させるととが
できる。さらに被着方法としてはイオンブレーティング
法のみでなく化学一つき法、溶射等公知のいかなる方法
も使用できる。また皮膜厚さも耐環境性の必要度合に応
じて任意に選択できる。Moreover, these can be arbitrarily overlapped and applied as necessary. Furthermore, as a deposition method, not only the ion blasting method but also any known method such as a chemical coating method or a thermal spraying method can be used. Further, the film thickness can be arbitrarily selected depending on the required degree of environmental resistance.
本発明にかかるプラスチックパッケージの略全表面上に
少くとも１種類以上の金属又は金属化合物を被着させた
半導体のパッケージを使用すれば、機械的強度にすぐれ
寸法安定性が良いというプラスチックパッケージの特徴
を生かしつつ、吸湿性、アルカリイオン透過性を大幅に
改善できるため耐環境性を向上させることができる。し
かも本発明の採用によるコストの増加はわずかである。By using a semiconductor package in which at least one kind of metal or metal compound is coated on substantially the entire surface of the plastic package according to the present invention, the plastic package has excellent mechanical strength and good dimensional stability. It is possible to significantly improve hygroscopicity and alkali ion permeability while making the most of the above properties, thereby improving environmental resistance. Moreover, the increase in cost due to the adoption of the present invention is small.
ｔた、被着膜が耐熱性、耐放射線性にすぐれるものであ
ることから本発明にかかるプラスチックパッケージの耐
熱性、耐放射線特性も向上する。Furthermore, since the deposited film has excellent heat resistance and radiation resistance, the heat resistance and radiation resistance of the plastic package according to the present invention are also improved.
さらに、被着膜が金属又は導電性金属化合物である場合
には、静電じゃへい効果、磁気じやへい効果、電磁じゃ
へい効果を与えることとなり、外部ノイズによる半導体
装置の誤動作を低減することができる。Furthermore, when the deposited film is a metal or a conductive metal compound, it provides an electrostatic barrier effect, a magnetic barrier effect, and an electromagnetic barrier effect, which reduces malfunctions of semiconductor devices caused by external noise. Can be done.
第１図は従来のプラスチックパッケージを示した断面図
、第２図はセラ電ツクパッケージの一例を示した断面図
、第３図はニッケル皮膜を被着させた本発明の一実施例
を示す断面図、第４図は酸化アルミニウム皮膜を被着さ
せた本発明の一実施例を示す断面図、第５図は一化アル
ミニウム皮膜の上にニッケル皮膜を被着させた李発明の
一実施例を示す断面図、第１・６−及び第７図はニッケ
ル皮膜を被着させる方法を示す説明図、第８図及び第９
図はアルミニウム皮膜を被着させる方法を示す・ 説明
図、第１０図はアルミニウム皮膜の上にニッケ（７）
ル皮膜を被着させるｐ法を示す説明図、第１１図は信頼
性試験用のパターンを示す構成図、第撃図は本発明を適
用したプラスチックパッケージと従来のプラスチックパ
ッケージの信頼性試験結果の比較を示ｊグラフである。
１・・・半導体ペレット、２・・・リード、３・・・ワ
イヤ、４・・・プラスチック樹脂、５・・・セラミック
基板、６・・・セラミックふた、１０・・・ニッケル皮
膜、１１・・・酸化アルミニウム皮膜、１２・・・ニッ
ケル皮膜、１３・・・ジグ（Ａ）、１４・・・シリコン
ゴム、１５・・・ジグ（Ｂ）、１６・・・ジグ（Ｃ）、
１７・・・アルミニウム配線。
出願人代理人 猪 股 清
（９） −２１１（８）
馬１図
壓３図Fig. 1 is a sectional view showing a conventional plastic package, Fig. 2 is a sectional view showing an example of a ceramic electric package, and Fig. 3 is a sectional view showing an embodiment of the present invention coated with a nickel film. Figure 4 is a sectional view showing an embodiment of the present invention in which an aluminum oxide film is applied, and Fig. 5 is a cross-sectional view showing an embodiment of the Lee invention in which a nickel film is applied on an aluminum monide film. The cross-sectional views shown in Figures 1, 6 and 7 are explanatory views showing the method of depositing the nickel film, and Figures 8 and 9 are
Figure 10 is an explanatory diagram showing the method of depositing an aluminum film, Figure 10 is an explanatory diagram showing the p method of depositing a nickel (7) film on an aluminum film, and Figure 11 is an explanatory diagram showing a method for depositing a nickel (7) film on an aluminum film. The block diagram showing the pattern and the first shot diagram are graphs showing a comparison of the reliability test results of the plastic package to which the present invention is applied and the conventional plastic package. DESCRIPTION OF SYMBOLS 1... Semiconductor pellet, 2... Lead, 3... Wire, 4... Plastic resin, 5... Ceramic substrate, 6... Ceramic lid, 10... Nickel film, 11...・Aluminum oxide film, 12... Nickel film, 13... Jig (A), 14... Silicon rubber, 15... Jig (B), 16... Jig (C),
17...Aluminum wiring. Applicant's agent Kiyoshi Inomata (9) -211 (8) Horse 1 figure 3 figure
Claims (1)
上に少くとも１種類以上の金属又は金属化合物を被着さ
せたことを特徴とする半導体装置の゛パッケージ。1. A package for a semiconductor device, characterized in that at least one kind of metal or metal compound is coated on substantially the entire surface of a plastic package formed by resin molding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57082810A JPS58199543A (en) | 1982-05-17 | 1982-05-17 | Package for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57082810A JPS58199543A (en) | 1982-05-17 | 1982-05-17 | Package for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58199543A true JPS58199543A (en) | 1983-11-19 |
| JPH0235467B2 JPH0235467B2 (en) | 1990-08-10 |
Family
ID=13784764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57082810A Granted JPS58199543A (en) | 1982-05-17 | 1982-05-17 | Package for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58199543A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4633573A (en) * | 1982-10-12 | 1987-01-06 | Aegis, Inc. | Microcircuit package and sealing method |
| JPS6212953U (en) * | 1985-07-09 | 1987-01-26 | ||
| JPH0260150A (en) * | 1988-08-26 | 1990-02-28 | Semiconductor Energy Lab Co Ltd | Electronic device and manufacture thereof |
| US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
| JPWO2006100768A1 (en) * | 2005-03-23 | 2008-08-28 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP2017034086A (en) * | 2015-07-31 | 2017-02-09 | 株式会社東芝 | Semiconductor device and semiconductor device manufacturing method |
| JP2017168701A (en) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223248U (en) * | 1975-08-08 | 1977-02-18 |
-
1982
- 1982-05-17 JP JP57082810A patent/JPS58199543A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5223248U (en) * | 1975-08-08 | 1977-02-18 |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4633573A (en) * | 1982-10-12 | 1987-01-06 | Aegis, Inc. | Microcircuit package and sealing method |
| JPS6212953U (en) * | 1985-07-09 | 1987-01-26 | ||
| JPH0260150A (en) * | 1988-08-26 | 1990-02-28 | Semiconductor Energy Lab Co Ltd | Electronic device and manufacture thereof |
| US6756670B1 (en) | 1988-08-26 | 2004-06-29 | Semiconductor Energy Laboratory Co., Ltd. | Electronic device and its manufacturing method |
| JPWO2006100768A1 (en) * | 2005-03-23 | 2008-08-28 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| JP2017034086A (en) * | 2015-07-31 | 2017-02-09 | 株式会社東芝 | Semiconductor device and semiconductor device manufacturing method |
| JP2017168701A (en) * | 2016-03-17 | 2017-09-21 | 東芝メモリ株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0235467B2 (en) | 1990-08-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3585461A (en) | High reliability semiconductive devices and integrated circuits | |
| KR100225148B1 (en) | Electrostatic chuck and fabricating method therefor | |
| US20160190028A1 (en) | Method and structure for fan-out wafer level packaging | |
| WO1982003727A1 (en) | Method of making a semiconductor device having a projecting,plated electrode | |
| JPH0530050B2 (en) | ||
| EP0354056A2 (en) | Coated electric devices and methods of manufacturing the same | |
| US6191492B1 (en) | Electronic device including a densified region | |
| JPS58199543A (en) | Package for semiconductor device | |
| EP1388167B1 (en) | Method of removing oxide from copper bond pads | |
| US10861794B2 (en) | Low frequency electromagnetic interference shielding | |
| KR101540583B1 (en) | Method of manufacturuing Electro-Magnetic Shielding Layer for semiconductor package | |
| JPH09237869A (en) | Resin-encapsulated power module device and manufacture thereof | |
| JPH05152362A (en) | Manufacture of semiconductor device | |
| JP2684387B2 (en) | Electronic device and manufacturing method thereof | |
| JPH05152378A (en) | Tape carrier package | |
| JP2002339079A (en) | Wafer fixture for plating | |
| JPS58158952A (en) | Semiconductor device and manufacture thereof | |
| CN110211886B (en) | Semiconductor manufacturing method | |
| JPH0260154A (en) | Lead frame and manufacture of electronic device incorporating the same | |
| JPS60182755A (en) | Manufacture of al-coated lead frame | |
| JPS6310547A (en) | Semiconductor device | |
| JP2017016957A (en) | Substrate junction body and manufacturing method thereof | |
| JPH0653570A (en) | Manufacture of surface acoustic wave device | |
| JPH04151858A (en) | Hybrid ic and ceramic cap for sealing semiconductor | |
| RU1378722C (en) | Contact system for photoelectric transducers |