JPS5771137A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5771137A
JPS5771137A JP55146792A JP14679280A JPS5771137A JP S5771137 A JPS5771137 A JP S5771137A JP 55146792 A JP55146792 A JP 55146792A JP 14679280 A JP14679280 A JP 14679280A JP S5771137 A JPS5771137 A JP S5771137A
Authority
JP
Japan
Prior art keywords
wiring
package
heat treatment
highly reliable
header
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55146792A
Other languages
Japanese (ja)
Inventor
Fumio Ichikawa
Shiro Hagiwara
Shintaro Ushio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP55146792A priority Critical patent/JPS5771137A/en
Publication of JPS5771137A publication Critical patent/JPS5771137A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Abstract

PURPOSE:To produce a highly reliable device capable of resisting moisture outside by a method wherein a protective coating is provided after completion of the bonding of the device to a header and of the wiring from the device to the package. CONSTITUTION:Diffusion layers 2, an insulator layer 3, and an Al wiring 4 are as usual formed on an Si substrate 1. The device is mounted on a package header 9 via an An-Si eutectic layer 11 and an Al lead 7 connects the pad 6 of the Al wiring 4 to a socket 8. Next, the device and package are placed in a heat treatment unit with the metal made socket 8 protected by a quartz made jig 12. The heat treatment consists of a reaction between SiH4 and NH4 at a temperature of approximately 300 deg.C, which results in an Si3N4 coating 5. The heat treated device is then potted. Thanks to the Si3N4 coating 5 keeping away moisture, C, O, N2 and the like when the device is live and thereby Al wiring deterioration and migrating ion caused fluctuations in MOS characteristics prevented, a highly reliable device is produced.
JP55146792A 1980-10-22 1980-10-22 Manufacture of semiconductor device Pending JPS5771137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55146792A JPS5771137A (en) 1980-10-22 1980-10-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55146792A JPS5771137A (en) 1980-10-22 1980-10-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5771137A true JPS5771137A (en) 1982-05-01

Family

ID=15415636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55146792A Pending JPS5771137A (en) 1980-10-22 1980-10-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5771137A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58206129A (en) * 1982-05-27 1983-12-01 Seiko Epson Corp Semiconductor device
JPS59231840A (en) * 1983-06-14 1984-12-26 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
JPS62186553A (en) * 1986-02-12 1987-08-14 Seiko Epson Corp Molded structure of wire bonding part
JPS63313829A (en) * 1988-05-06 1988-12-21 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JPH02346A (en) * 1989-02-10 1990-01-05 Semiconductor Energy Lab Co Ltd Semiconductor device
JPH02345A (en) * 1989-02-10 1990-01-05 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58206129A (en) * 1982-05-27 1983-12-01 Seiko Epson Corp Semiconductor device
JPS59231840A (en) * 1983-06-14 1984-12-26 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacture thereof
JPH0142629B2 (en) * 1983-06-14 1989-09-13 Handotai Energy Kenkyusho
JPS62186553A (en) * 1986-02-12 1987-08-14 Seiko Epson Corp Molded structure of wire bonding part
JPS63313829A (en) * 1988-05-06 1988-12-21 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device
JPH0143456B2 (en) * 1988-05-06 1989-09-20 Handotai Energy Kenkyusho
JPH02346A (en) * 1989-02-10 1990-01-05 Semiconductor Energy Lab Co Ltd Semiconductor device
JPH02345A (en) * 1989-02-10 1990-01-05 Semiconductor Energy Lab Co Ltd Manufacture of semiconductor device

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