JPS5570073A - Treating method of accelerating rom - Google Patents

Treating method of accelerating rom

Info

Publication number
JPS5570073A
JPS5570073A JP14345578A JP14345578A JPS5570073A JP S5570073 A JPS5570073 A JP S5570073A JP 14345578 A JP14345578 A JP 14345578A JP 14345578 A JP14345578 A JP 14345578A JP S5570073 A JPS5570073 A JP S5570073A
Authority
JP
Japan
Prior art keywords
package
semiconductor element
sio
oxide film
accelerating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14345578A
Other languages
Japanese (ja)
Inventor
Kazuo Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14345578A priority Critical patent/JPS5570073A/en
Publication of JPS5570073A publication Critical patent/JPS5570073A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To lower ON resistance in a MOS element, by directly introducing excessive ions from a packaging portion material into a gate oxide film when thermally treating a semiconductor element forming a PROM in order to package the element.
CONSTITUTION: A MOS semiconductor element is manufactured in such a manner that p+-diffusion regions 6, 7 functioning as a source and a drain are made up on a surface of a n-type Si substrate 1, an Al gate 3 is built up through a gate oxide film (SiO2) 2 and a SiO2 film 4 is formed by means of a CVD method, etc. A semiconductor chip is sent to a packaging stage. That is, the semiconductor element is incorporated into a package substrate in ceramics, etc., a portion between an electrode and a lead is bonded by means of a wire and a package is sealed through glass, etc.
COPYRIGHT: (C)1980,JPO&Japio
JP14345578A 1978-11-22 1978-11-22 Treating method of accelerating rom Pending JPS5570073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14345578A JPS5570073A (en) 1978-11-22 1978-11-22 Treating method of accelerating rom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14345578A JPS5570073A (en) 1978-11-22 1978-11-22 Treating method of accelerating rom

Publications (1)

Publication Number Publication Date
JPS5570073A true JPS5570073A (en) 1980-05-27

Family

ID=15339094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14345578A Pending JPS5570073A (en) 1978-11-22 1978-11-22 Treating method of accelerating rom

Country Status (1)

Country Link
JP (1) JPS5570073A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011517061A (en) * 2008-03-13 2011-05-26 エス．オー．アイ．テック シリコン オン インシュレータ テクノロジーズ Substrate having a charged region in an insulating buried layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011517061A (en) * 2008-03-13 2011-05-26 エス．オー．アイ．テック シリコン オン インシュレータ テクノロジーズ Substrate having a charged region in an insulating buried layer

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