JPS5740967A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS5740967A
JPS5740967A JP11627480A JP11627480A JPS5740967A JP S5740967 A JPS5740967 A JP S5740967A JP 11627480 A JP11627480 A JP 11627480A JP 11627480 A JP11627480 A JP 11627480A JP S5740967 A JPS5740967 A JP S5740967A
Authority
JP
Japan
Prior art keywords
drain
source
region
contact
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11627480A
Other languages
Japanese (ja)
Inventor
Seiichi Iwamatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP11627480A priority Critical patent/JPS5740967A/en
Publication of JPS5740967A publication Critical patent/JPS5740967A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688Integrated circuits having a three-dimensional layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce a resistance-occupied area and improve integration degree, by forming a region having a junction between two conductor or a semiconductor and a conductor, and making said region a resistor. CONSTITUTION:Two N<+> type regions or a source 2 and a drain 3 are formed on a main surface of a P type Si substrate 1 by means of ion injection. A polycrystalline Si gate 5 is provided via an SiO2 film 4 on the Si substrate between these two regions apart from the substrate 1. Thick protecting films 6 and 7 of SiO2 are formed to cover the P-N junction surface of the source region 2 and the drain region 3. Each surface contact is opened for the source and the drain. A metal film 9 is formed via an N-polycrystalline Si layer 8 on the source contact. An Al-evaporated wire 10 is applied on the contact resistor and a drain contact to constitute each electrode.
JP11627480A 1980-08-22 1980-08-22 Integrated circuit device Pending JPS5740967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11627480A JPS5740967A (en) 1980-08-22 1980-08-22 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11627480A JPS5740967A (en) 1980-08-22 1980-08-22 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5740967A true JPS5740967A (en) 1982-03-06

Family

ID=14683013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11627480A Pending JPS5740967A (en) 1980-08-22 1980-08-22 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5740967A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device
JPS585356U (en) * 1981-07-02 1983-01-13 三洋電機株式会社 resistance element
JPS6441243A (en) * 1987-08-07 1989-02-13 Nec Corp Semiconductor integrated circuit
JPH01108773A (en) * 1987-10-21 1989-04-26 Mitsubishi Electric Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745967A (en) * 1980-09-04 1982-03-16 Toshiba Corp Semiconductor device
JPS585356U (en) * 1981-07-02 1983-01-13 三洋電機株式会社 resistance element
JPS6441243A (en) * 1987-08-07 1989-02-13 Nec Corp Semiconductor integrated circuit
JPH01108773A (en) * 1987-10-21 1989-04-26 Mitsubishi Electric Corp Semiconductor device

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