JPH0142629B2 - - Google Patents

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Publication number
JPH0142629B2
JPH0142629B2 JP58106452A JP10645283A JPH0142629B2 JP H0142629 B2 JPH0142629 B2 JP H0142629B2 JP 58106452 A JP58106452 A JP 58106452A JP 10645283 A JP10645283 A JP 10645283A JP H0142629 B2 JPH0142629 B2 JP H0142629B2
Authority
JP
Japan
Prior art keywords
silicon nitride
chip
wire
nitride film
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP58106452A
Other languages
Japanese (ja)
Other versions
JPS59231840A (en
Inventor
Shunpei Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP58106452A priority Critical patent/JPS59231840A/en
Publication of JPS59231840A publication Critical patent/JPS59231840A/en
Publication of JPH0142629B2 publication Critical patent/JPH0142629B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/05624—Aluminium [Al] as principal constituent
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    • H01L2224/4805—Shape
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)

Description

【発明の詳細な説明】 この発明は半導体装置の封止に関する。[Detailed description of the invention] The present invention relates to the sealing of semiconductor devices.

この発明は、プラスチツク・モールド封止に関
し、窒化珪素膜を半導体チツプ（トランジスタま
たはそれが複数個集積化された半導体装置を以下
チツプという）の表面のみならず、ワイヤボンド
用バツドにボンデイングされた金細線（25μφ）
の少なくともパツド近傍にコーテイングすること
により、アルミニユーム・パツドまたはチツプ内
の５〜10μ巾のリード等でのコロージヨン（腐
食）を防ぐことを目的としている。 This invention relates to plastic mold encapsulation, and the present invention relates to a silicon nitride film not only on the surface of a semiconductor chip (a semiconductor device in which a plurality of transistors or transistors are integrated is hereinafter referred to as a chip), but also on metal bonded to wire bonding butts. Thin wire (25μφ)
By coating at least the vicinity of the pad, the purpose is to prevent corrosion on the aluminum pad or the 5 to 10 μm wide leads in the chip.

この発明は、プラスチツク・モールド・パツケ
ージにおいて、信頼性の低下をする水等の湿度が
単にプラスチツク・パツケージのバルクのみなら
ず、ワイヤを伝わり侵入する水、リードフレーム
の表面を伝わつて侵入する水に対しても、ブロツ
キング効果を有した、高信頼性の半導体装置を設
けたことを特徴としている。 In a plastic molded package, the present invention is designed to reduce the humidity of water, etc., which reduces reliability, not only in the bulk of the plastic package, but also in water that penetrates through wires and water that penetrates through the surface of the lead frame. It is also characterized by the provision of a highly reliable semiconductor device that has a blocking effect.

この発明は窒化珪素のフアイナル・コーテイン
グをウエハ・レベルにて行うのではなく、チツプ
をダイボンデイング（ダイアタツクともいう）
し、さらにワイヤ・ボンデイングを完了した後、
チツプ表面のみならずワイヤおよびアルミニユー
ム・パツドに対しても、同時に300℃以下好まし
くは100〜250℃の温度でプラズマ気相法、光プラ
ズマ気相法または光気相法により行うことによ
り、これら全ての表面に窒化珪素膜コーテイング
を施し、その後にプラスチツク・モールド処理に
よる封止を行うことを特徴としている。 This invention does not perform the final coating of silicon nitride at the wafer level, but instead performs die bonding (also called die attack) on the chips.
and after completing further wire bonding,
Not only the chip surface but also the wire and aluminum pad are simultaneously treated at a temperature of 300°C or less, preferably 100 to 250°C, by plasma vapor phase method, photo plasma vapor phase method, or photo vapor phase method. It is characterized by applying a silicon nitride film coating to the surface and then sealing it by plastic molding.

従来、チツプのフアイナル・コーテイングは、
ウエハ・レベルにて行つていた。このため、その
後工程にくるワイヤ・ボンデイング用のパツド部
のアルミニユーム（一般には100μ×100μ）は、
エポキシ・モールド一部に露呈してしまつてい
た。 Conventionally, the final coating of chips is
It was done at the wafer level. For this reason, the aluminum pad (generally 100μ x 100μ) used for wire bonding in the subsequent process is
Part of the epoxy mold was exposed.

このため、第１図に示すごときプラスチツク製
DIP（デイアル・イン・パツケージ）において、
プラスチツク３６のバルク３３からの水（湿度）
の侵入に対しては、窒化珪素３０はブロツキング
効果を有するが、ワイヤを伝わる侵入３４、さら
にリードフレーム３７とモールド３６との界面で
のクラツク３２からの侵入３１に対しては、まつ
たく効果を有さないことが判明した。 For this reason, plastic
In DIP (Deal-in-Package),
Water (humidity) from bulk 33 of plastic 36
Although silicon nitride 30 has a blocking effect against intrusion, it has no blocking effect against intrusion 34 transmitted through the wire and furthermore against intrusion 31 from cracks 32 at the interface between lead frame 37 and mold 36. It turned out that there was no such thing.

このためアルミニユーム・パッド３８はコロー
ジヨンを起こしやすく、半導体装置の特性劣化、
信頼性低下を誘発してしまつていた。 For this reason, the aluminum pad 38 is prone to corrosion, resulting in deterioration of the characteristics of the semiconductor device and
This caused a decrease in reliability.

特にモールド材例えばモートン社の410Bエポ
キシモールド材を用いた場合、そのモールド材中
に塩素が多量に残存し、水により塩素イオンとな
りアルミニユームと反応し、コロージヨン（腐
食）を起こし、アルミニユームが水酸化アルミニ
ユームとなり断線してしまう。そのためその半導
体装置としての信頼性低下が著しかつた。 In particular, when using a molding material such as Morton's 410B epoxy molding material, a large amount of chlorine remains in the molding material, and water turns into chlorine ions and reacts with the aluminum, causing corrosion, and the aluminum becomes aluminum hydroxide. This causes a disconnection. As a result, the reliability of the semiconductor device has significantly decreased.

また、フレームをリード部において曲げかつタ
イバーを切断する際起こりやすいリードフレーム
とエポキシモールドとの接着面でのクラツク３２
からの水の侵入によるパツド部でのコロージヨン
の発生には、まつたく無防備であつた。 Also, when bending the frame at the lead part and cutting the tie bar, cracks at the adhesive surface between the lead frame and the epoxy mold tend to occur.
The pads were completely defenseless against corrosion caused by water ingress.

本発明はかかる従来のDIPにおきる信頼性の低
下を防ぐためになされたものである。 The present invention was made in order to prevent the deterioration in reliability that occurs in such conventional DIP.

第２図は本発明構造のプラスチツクDIPの縦断
面図を示す。 FIG. 2 shows a longitudinal cross-sectional view of a plastic DIP constructed according to the invention.

図面において、ダイ２８に密着させたチツプ２
６と、このチツプのアルミニユーム・パツド３８
とステム３５との間に金線のワイヤボンドを行
い、さらにこのチツプ２６表面、パツド３８表
面、ワイヤ表面（特にパツド近傍表面）に対し、
窒化珪素膜３０のコーテイングを行う。 In the drawing, the chip 2 is in close contact with the die 28.
6 and this chip's aluminum pad 38
A gold wire wire is bonded between the chip 26, the pad 38, and the wire (especially the surface near the pad).
Coating with a silicon nitride film 30 is performed.

さらに好ましくはワイヤ全体のみならずステム
３５上面およびそこにボンデイングされたワイヤ
表面に対しても、コーテイングをしたものであ
る。 More preferably, not only the entire wire but also the upper surface of the stem 35 and the surface of the wire bonded thereto are coated.

この窒素珪素膜は100〜300℃好ましくは150〜
250℃の温度において、珪化物気体とアンモニア
とを反応炉に導入し、そこに電気エネルギーまた
は光エネルギーを供給するいわゆるプラズマ気相
法、フオト・プラズマ気相法またはフオトCVD
法により形成せしめた。 The temperature of this nitrogen silicon film is 100~300℃, preferably 150~300℃.
The so-called plasma vapor phase method, photo plasma vapor phase method or photo CVD, in which silicide gas and ammonia are introduced into a reactor at a temperature of 250°C and electrical or light energy is supplied thereto.
Formed by law.

かくの如くして、窒化珪素膜を300〜2500Å、
一般には約1000Åの厚さに形成した後、公知のイ
ンジエクシヨン・モールド法によりエポキシ（例
えば410B）モールド法により注入・封止させた。
さらにフレームをリード部３７にて曲げ、かつタ
イバーを切断する。さらにリード部を酸洗いを行
つた後、リードにハンダメツキを行つた。 In this way, a silicon nitride film with a thickness of 300 to 2500 Å,
Generally, after being formed to a thickness of about 1000 Å, it is injected and sealed using an epoxy (eg, 410B) molding method using a known injection molding method.
Further, the frame is bent at the lead portion 37 and the tie bar is cut. Furthermore, after acid-washing the lead portion, the lead was solder-plated.

かかる本発明の半導体装置の構造において、信
頼性が低下をするモールドバツクからの水の侵入
３３、ワイヤ２７表面を伝わる侵入、３４、クラ
ツク３２からの水の浸入３１のすべてに対しコロ
ージヨンを防ぐことができるようになつた。 In the structure of the semiconductor device of the present invention, corrosion can be prevented against all of the water intrusion 33 from the mold bag, the intrusion 34 transmitted through the surface of the wire 27, and the intrusion 31 of water from the crack 32, which reduce reliability. Now I can do it.

特にアルミニユーム・パッド３８の全ての表面
が直接モールド材に露呈・接触していない、加え
て窒化珪素膜は水、塩素に対するブロツキング効
果（マスク効果）が大きい。このため本発明構造
の半導体においては、PCT（プレツシヤー・クツ
カー・テスト）10atom、100時間、150℃の条件
下においても、まつたく不良が観察されず、従来
のICチツプ50〜100フイツトの不良率を有してい
たが、５〜10フイツトにまでその不良率を下げる
ことが可能になつた。 In particular, the entire surface of the aluminum pad 38 is not directly exposed or in contact with the molding material, and in addition, the silicon nitride film has a large blocking effect (mask effect) against water and chlorine. Therefore, in the semiconductor with the structure of the present invention, no defects were observed even under PCT (Pressure Cutcher Test) conditions of 10 atoms, 100 hours, and 150 degrees Celsius, and the defect rate was lower than that of conventional IC chips of 50 to 100 feet. However, it has become possible to reduce the defective rate to 5 to 10 feet.

第３図は本発明のチツプがフレームにボンデイ
ングされた構造にて、プラズマCVD法により窒
化珪素膜のコーテイングを行うための装置の概要
を示す。 FIG. 3 shows an outline of an apparatus for coating a silicon nitride film by the plasma CVD method in a structure in which the chip of the present invention is bonded to a frame.

図面において、反応系６、ドーピング系５を有
している。 In the drawing, it has a reaction system 6 and a doping system 5.

反応系は、反応室１と予備室７とを有し、ゲー
ト弁９，８とを有している。反応室１は一対のハ
ロゲンヒータ２２を有し、その内側に供給側フー
ドを有し、フード１３のノズルより入口側３より
の反応性気体を下方向に吹き出し、反応させ、被
膜形成を行つた。反応後は排出側フード１４によ
り排気口４を経てバルブ２１、真空ポンプ２０に
至る。高周波電源１０（周波数100〜500KHz）よ
り、電気エネルギーは一対の網状電極１１，１２
により反応性気体に供給される。被膜の被形成体
２（以下基板２という）は絶縁サポータ４１上に
配設された枠構造のホルダー４０内に平行に一定
の間隔（例えゃば５cm）を有して配設されてい
る。この基板２は、グロー放電により作られるプ
ラズマ中の陽光柱内に配設され、電気的にいずれ
の電極１１，１２からもフローテイング構造を有
している。 The reaction system has a reaction chamber 1 and a preliminary chamber 7, and gate valves 9 and 8. The reaction chamber 1 has a pair of halogen heaters 22, and has a supply side hood inside thereof, and the reactive gas from the inlet side 3 is blown downward from the nozzle of the hood 13 to react and form a film. . After the reaction, the reaction is carried out by the discharge side hood 14 through the exhaust port 4 to the valve 21 and the vacuum pump 20. Electrical energy is transmitted from a high frequency power source 10 (frequency 100 to 500KHz) to a pair of mesh electrodes 11 and 12.
The reactive gas is supplied by The object 2 on which the film is to be formed (hereinafter referred to as the substrate 2) is arranged in parallel in a frame-structured holder 40 arranged on an insulating supporter 41 at a constant interval (for example, 5 cm). This substrate 2 is disposed within a positive column in plasma created by glow discharge, and has a floating structure electrically floating from both electrodes 11 and 12.

反応性気体はフード１３より枠構造のホルダ４
０の内側およびフード１４により囲まれた内側に
てプラズマ活性状態で基板上に被膜形成がなさ
れ、フレークが反応室内で作られないようにさせ
ている。 The reactive gas is transferred from the hood 13 to the frame-structured holder 4.
A coating is formed on the substrate in a plasma-activated state inside the 0 and surrounded by the hood 14 to prevent flakes from being created within the reaction chamber.

第３図に示すごとき本発明方法におけるPCVD
法は、基板が電極的にフローテインクであるフロ
ーテイング・プラズマ気相法（FPCVD）法であ
るため、基板の一部に導体を用いても、放電が不
安定になることはないという特長を有する。 PCVD in the method of the present invention as shown in Figure 3
The method is a floating plasma vapor deposition (FPCVD) method in which the substrate is a floating ink electrode, so even if a conductor is used as part of the substrate, the discharge will not become unstable. have

ドーピング系は珪化物気体であるシランまたは
ジクロールシランを１７より、また窒化物気体で
あるアンモニアを１６より、キヤリアガスで窒素
または水素を１５より供給している。それらは流
量計１８、バルブ１９により制御している。 In the doping system, silane or dichlorosilane, which is a silicide gas, is supplied from 17, ammonia, which is a nitride gas, is supplied from 16, and nitrogen or hydrogen as a carrier gas is supplied from 15. These are controlled by a flow meter 18 and a valve 19.

例えば基板温度を220℃±10℃とし、NH3／
SiH4＝20とした。さらに200KHzの周波数により
100Wの出力を供給した。かくして平均1000Å
（1000ű200Å）に約15分の被膜形成を行つた。 For example, if the substrate temperature is 220℃±10℃, NH 3 /
SiH 4 =20. Furthermore, due to the frequency of 200KHz
It provided a power output of 100W. Thus on average 1000Å
(1000 Å ± 200 Å) for about 15 minutes.

ホルダー４０は枠の内側の大きさ60cm×60cmを
有し、電極間距離は30cm（有効20cm）としてい
る。 The holder 40 has an inner frame size of 60 cm x 60 cm, and the distance between the electrodes is 30 cm (effective 20 cm).

また第３図の基板２の部分を拡大した図面を第
４図に示す。 FIG. 4 shows an enlarged view of the substrate 2 in FIG. 3.

第４図において、Ａはサポータ２３の両表面に
コバール製フレーム４０のパツドにチツプ２６を
ダイアタツチし、さらにチツプのアルミニユー
ム・パツドとステム２５間にワイヤボンド２７さ
せたフレームを配設している。 In FIG. 4, A has a frame in which a chip 26 is die-attached to the pads of a Kovar frame 40 on both surfaces of the supporter 23, and a wire bond 27 is made between the aluminum pad of the chip and the stem 25.

リードフレーム４０において、少なくともリー
ドとする領域に対しては、フレーム４０の保持を
兼ねたカバー２４にて覆い、このリード部に窒化
珪素膜が形成されないようにしている。 In the lead frame 40, at least a region to be used as a lead is covered with a cover 24 which also serves to hold the frame 40, so that a silicon nitride film is not formed on this lead portion.

フレーム４０はこのカバー２４のため、第４図
Ｃの領域２９のみに窒化珪素膜が形成され、領域
２５には窒化珪素膜を形成させないことがきわせ
て重要である。 Since the frame 40 is the cover 24, it is extremely important that the silicon nitride film is formed only in the region 29 in FIG. 4C, and that the silicon nitride film is not formed in the region 25.

第４図Ｃは、リード部の下側を省略した16ピン
の例を示している。しかしこの形状以外の任意の
ピン数、形状を同様に有せしめることが可能であ
ることはいうまでもない。 FIG. 4C shows an example of 16 pins with the lower part of the lead portion omitted. However, it goes without saying that it is possible to have any number of pins and any shape other than this shape.

第４図ＢはＡにおけるサポータ２３を省略した
ものである。同様にチツプ２６の近傍のみを選択
的に窒化珪素膜でコーテイングをし、リード部に
はコーテイングされないようにリードのカバー２
４がフレームの保持を兼ねて設けられている。 FIG. 4B is a diagram in which the supporter 23 in A is omitted. Similarly, only the vicinity of the chip 26 is selectively coated with a silicon nitride film, and the leads are covered with a silicon nitride film so that the lead portions are not coated.
4 is provided to also hold the frame.

しかし第３図のFPCVD法においては、グロー
放電をさせ、各フレームに初期の電荷がチヤージ
アツプした後は、チヤージがリークすることがな
いため、絶縁膜上に被膜を形成させる場合とまつ
たく同様に窒化珪素膜をコーテイングすることが
できるという特長を有する。 However, in the FPCVD method shown in Figure 3, after the glow discharge is caused and the initial charge is increased in each frame, the charge does not leak, so it is similar to the case where a film is formed on an insulating film. It has the advantage of being able to coat a silicon nitride film.

即ち、本発明の作製方法は、単に窒化珪素膜を
ワイヤボンドした後にコーテイングするという特
長を有するのみならず、パツド、チツプ表面に対
しても均一な膜厚をコーテイングするため、
FPCVD法を用いたことを他の特長としている。 That is, the manufacturing method of the present invention not only has the feature of simply coating the silicon nitride film after wire bonding, but also coats the pad and chip surfaces with a uniform thickness.
Another feature is that it uses the FPCVD method.

なお本発明において、FPCVD法において、電
気エネルギーのみならず、10〜15μの波長の遠赤
外または300nm以下の紫外線を同時に加えたフロ
ーテイングであつて、かつ光エネルギーを用いる
フオトCVD（またはフオトFPCVD）法を用いる
ことは有効である。 In the present invention, in the FPCVD method, photoCVD (or photoFPCVD) is a floating method in which not only electric energy but also far infrared rays with a wavelength of 10 to 15 μm or ultraviolet rays of 300 nm or less are simultaneously applied, and which uses light energy. ) method is effective.

また第３図において、ハロゲンランプの加熱装
置２２の一部を紫外光の発生源とすることにより
可能とすることができる。 Further, in FIG. 3, this can be achieved by using a part of the halogen lamp heating device 22 as a source of ultraviolet light.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来のデユアル・イン・ライン製プラ
スチツク・パツケージ半導体装置を示す。第２図
は本発明のデユアル・イン・ライン製プラスチツ
ク・パツケージ半導体装置を示す。第３図は本発
明方法を実施するためのフローテイング・プラズ
マ気相反応装置の概要を示す。第４図は第３図の
装置のうちの基板部の拡大図を示す。 FIG. 1 shows a conventional dual-in-line plastic package semiconductor device. FIG. 2 shows a dual-in-line plastic package semiconductor device of the present invention. FIG. 3 schematically shows a floating plasma gas phase reactor for carrying out the method of the present invention. FIG. 4 shows an enlarged view of the substrate portion of the apparatus shown in FIG.

Claims (1)

【特許請求の範囲】[Claims] １ リードフレームに配設された半導体チツプと
該チツプのボンデイング用パツドと、前記リード
フレームのステム間にワイヤボンドがなされた半
導体装置を、減圧下の雰囲気内に保持し、珪化物
気体と窒化物気体とを導入し、電気エネルギーま
たは光エネルギーを供給することにより、半導体
チツプ表面、パツド表面およびワイヤ表面及びリ
ードフレーム表面を窒化珪素膜により覆うととも
に、半導体チツプ及びリードを包んでプラスチツ
ク・モールドにて封止した後、リード部を酸洗い
し、さらに該リード部にハンダメツキを行うこと
を特徴とする半導体装置作製方法。1. A semiconductor chip disposed on a lead frame, a bonding pad of the chip, and a semiconductor device with a wire bond formed between the stem of the lead frame are held in a reduced pressure atmosphere, and silicide gas and nitride are By introducing gas and supplying electrical energy or light energy, the semiconductor chip surface, pad surface, wire surface, and lead frame surface are covered with a silicon nitride film, and the semiconductor chip and leads are wrapped in a plastic mold. 1. A method for manufacturing a semiconductor device, which comprises, after sealing, pickling the lead portions and then solder-plating the lead portions.
JP58106452A 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof Granted JPS59231840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58106452A JPS59231840A (en) 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58106452A JPS59231840A (en) 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP63110193A Division JPS63313829A (en) 1988-05-06 1988-05-06 Manufacture of semiconductor device
JP1031960A Division JPH02346A (en) 1989-02-10 1989-02-10 Semiconductor device
JP1031959A Division JPH02345A (en) 1989-02-10 1989-02-10 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS59231840A JPS59231840A (en) 1984-12-26
JPH0142629B2 true JPH0142629B2 (en) 1989-09-13

Family

ID=14433990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58106452A Granted JPS59231840A (en) 1983-06-14 1983-06-14 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS59231840A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900019177A (en) * 1988-05-19 1990-12-24 야마자키 순페이 Electrical apparatus and manufacturing method
JPH01292846A (en) * 1988-05-19 1989-11-27 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
GB8815704D0 (en) * 1988-07-01 1988-08-10 Marconi Gec Ltd Tape automated bonded microchips
JPH0244738A (en) * 1988-08-05 1990-02-14 Semiconductor Energy Lab Co Ltd Manufacture of electronic device
JPH02102564A (en) * 1988-10-12 1990-04-16 Semiconductor Energy Lab Co Ltd Electronic device and manufacture thereof
JP2683694B2 (en) * 1988-10-17 1997-12-03 株式会社半導体エネルギー研究所 Method of manufacturing electronic device
JPH02106953A (en) * 1988-10-17 1990-04-19 Semiconductor Energy Lab Co Ltd Member for electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771137A (en) * 1980-10-22 1982-05-01 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5771137A (en) * 1980-10-22 1982-05-01 Oki Electric Ind Co Ltd Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS59231840A (en) 1984-12-26

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