JPH05275598A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05275598A JPH05275598A JP4071718A JP7171892A JPH05275598A JP H05275598 A JPH05275598 A JP H05275598A JP 4071718 A JP4071718 A JP 4071718A JP 7171892 A JP7171892 A JP 7171892A JP H05275598 A JPH05275598 A JP H05275598A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- lead frame
- die pad
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は樹脂封止した半導体装置
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】一般に樹脂封止半導体装置は、図６に断
面で示すように、リードフレーム１の中央部に半導体チ
ップ２を搭載するためのダイパッド３を有し、Ａｇペー
ストなどの接合材４で半導体チップ２をダイボンディン
グした後、該チップ上の電極パッド５とリードフレーム
１のインナ−リード１ａとをＡｕ線などのボンディング
ワイヤ６で接合して形成された構成体を、パッケージ内
に装入し樹脂封止７されて作製される。この様にして作
製された半導体装置は、リードフレーム１の先端（アウ
ターリード）１ｂにはんだ８を塗布し、回路基盤９には
んだ付けをするために熱照射や加熱してはんだを融解す
るリフロー処理がなされ、アウターリード１ｂと基盤９
を強固に接続する。2. Description of the Related Art Generally, a resin-sealed semiconductor device has a die pad 3 for mounting a semiconductor chip 2 in a central portion of a lead frame 1 and a bonding material 4 such as Ag paste 4 as shown in a cross section of FIG. After die-bonding the semiconductor chip 2 with, the electrode pad 5 on the chip and the inner lead 1a of the lead frame 1 are bonded by a bonding wire 6 such as an Au wire, and the package is mounted in the package. It is manufactured by putting in and resin-sealing 7. In the semiconductor device manufactured in this manner, the solder 8 is applied to the tips (outer leads) 1b of the lead frame 1, and heat is applied to the circuit board 9 for soldering or reflow processing for melting the solder by heating. Outer lead 1b and base 9
Connect firmly.
【０００３】一般に半導体装置の封止樹脂は吸湿性を有
するため経時的に水分を吸収し、また構成部品に付着し
ている水分もある。この様な含有水分は主に樹脂との界
面を破壊し、その隙間に溜った水分はリフロー加熱によ
って急激な気化を起こして膨脹し、樹脂破壊１０を生じ
させる。一方、潜在的に常温時においては、樹脂と構成
部品、特にダイパッド間でそれぞれの熱膨張差に起因す
る歪みが発生して界面に剪断剥離が起きることが分って
おり、リフロー加熱時にこの剥離した間隙部分に発生す
る水蒸気が剥離を助長する。特に応力集中が起きやすい
ダイパッドの端部では剥離が大きく、蒸気圧の作用と相
俟って図に示すようなクラック１０が発生する。このた
め半導体装置の封止性能を落し信頼性を損なうことにな
る。Generally, the sealing resin of a semiconductor device has a hygroscopic property, so that it absorbs moisture over time, and some of the moisture adheres to the components. Such contained water mainly destroys the interface with the resin, and the water accumulated in the gap causes rapid vaporization and expansion due to reflow heating, and causes resin destruction 10. On the other hand, potentially at room temperature, it has been known that strain due to the difference in thermal expansion between the resin and components, especially the die pad, causes shear peeling at the interface, and this peeling occurs during reflow heating. Water vapor generated in the gaps promotes peeling. In particular, peeling is large at the end portion of the die pad where stress concentration is likely to occur, and in combination with the action of vapor pressure, cracks 10 as shown in the figure occur. Therefore, the sealing performance of the semiconductor device is deteriorated and the reliability is impaired.
【０００４】そのため半導体装置の出荷に際して防湿の
ための特別梱包を行ったり、基盤実装時間を短時間にす
ることを要請したり、更には基盤実装前に吸湿品の空焼
きを実施するなどの対策がとられるが、これらの方法に
は極めた手数が掛ると共に需要先での対応が必要となり
って好ましくない。For this reason, measures such as special packaging for preventing moisture when shipping semiconductor devices, requesting that the board mounting time be shortened, and baking the hygroscopic product before board mounting are taken. However, these methods are not preferable because they require a great deal of trouble and need to be dealt with by the customer.
【０００５】一方、封止樹脂とダイパッドとの剥離を防
止するために、例えば特開昭５８−１９９５４８号公報
には、図８に断面で示すようにダイパッド（タブ）３の
裏面を凹凸形状１１に形成することを提示している。ま
た、特開昭５５−４９８３号公報には、図８に平面で示
すようなダイパッド（アイランド）３に部分的な切抜き
部１２を設けることを開示しており、さらに、特開平６
０−９７６４５号公報では、図９に断面で示すようにダ
イパッド（タブ）３の裏面に封止樹脂と近似した熱膨張
係数を有する熱硬化性或いは熱可塑性の有機樹脂（ポリ
イミド系）１３を取り付けた半導体装置を提案してい
る。On the other hand, in order to prevent the sealing resin and the die pad from peeling off, for example, in Japanese Unexamined Patent Publication No. 58-199548, the back surface of the die pad (tab) 3 is uneven 11 as shown in the cross section in FIG. It is proposed to form. Further, Japanese Patent Laid-Open No. 55-4983 discloses that a die pad (island) 3 as shown in FIG.
In JP-A-0-97645, a thermosetting or thermoplastic organic resin (polyimide-based) 13 having a thermal expansion coefficient similar to that of the sealing resin is attached to the back surface of the die pad (tab) 3 as shown in a cross section in FIG. We are proposing a semiconductor device.
【０００６】[0006]
【発明が解決しようとする課題】上記した従来の方法
は、ダイパッドを機械的に加工してその表面積を拡大し
たり、引っかかりを付けることにより、封止樹脂との接
触面を大きくして剪断剥離やクラックの発生を抑制しよ
うとするものであるが、ダイパッド自体の封止樹脂との
接合強度の改善は完全なものになっていなく、吸湿する
と接着が破壊し、水の溜まりができてリフロー時に急膨
脹を起こして封止樹脂が破壊する。また、ポリイミド系
の有機樹脂を使用する場合には、該樹脂自体にも吸湿性
を有しているので問題が残る。SUMMARY OF THE INVENTION In the above-mentioned conventional method, the die pad is mechanically processed to increase its surface area or to be caught, whereby the contact surface with the sealing resin is enlarged and shear peeling is performed. Although it is intended to suppress the occurrence of cracks and cracks, the bond strength of the die pad itself with the encapsulation resin is not completely improved. Sudden expansion causes the sealing resin to break. In addition, when a polyimide-based organic resin is used, the resin itself has a hygroscopic property, and thus a problem remains.
【０００７】本発明は上記したような従来の問題点を解
消するものであって、半導体チップを搭載するダイパッ
ドや樹脂フィルム、さらにはリードフレームの内部リー
ド等の封止樹脂との剥離が起きやすい部分を補強して接
着強度を向上せしめることにより、リフロー実装時およ
び実用時においてもクラック等の問題を起こさない信頼
性のある樹脂封止の半導体装置を提供することを目的と
するものである。The present invention solves the above-mentioned conventional problems, and easily peels off from a die pad for mounting a semiconductor chip, a resin film, and a sealing resin such as an inner lead of a lead frame. It is an object of the present invention to provide a reliable resin-encapsulated semiconductor device that does not cause problems such as cracks during reflow mounting and practical use by reinforcing the portion to improve the adhesive strength.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するため
に本発明は以下の構成を要旨とする。すなわち、 (1)半導体素子と、これを搭載するダイパッドを備えた
リードフレームと、前記素子に設けた電極とリードフレ
ームのインナーリードとを細線で連結した構成体を樹脂
封止した半導体装置において、前記ダイパッドの封止樹
脂と接触する上、下面および側面であって、これらの少
なくとも一部に無機物の薄膜で被覆したことを特徴とす
る半導体装置。 (2)半導体素子と、これを搭載するヒートスプレッダを
備えたリードフレームと、前記素子に設けた電極とリー
ドフレームのインナーリードとを細線で連結した構成体
を樹脂封止した半導体装置において、前記ヒートスプレ
ッダの封止樹脂に接触する上面および側面であって、こ
れらの少なくとも一部に無機物の薄膜で被覆したことを
特徴とする半導体装置。 (3)半導体素子と、これを搭載するデバイスホールを備
えたＴＡＢあるいはＦＰＣとリードフレームとが接合し
てなる複合リードフレームと、前記素子に設けた電極と
ＴＡＢ或いはＦＰＣのインナ−リードとを細線で連結し
た構成体を樹脂封止した半導体装置において、前記デバ
イスホールを構成する有機樹脂フィルムの封止樹脂に接
触する上、下面であって、これらの少なくとも一部に無
機物の薄膜で被覆したことを特徴とする半導体装置。 (4)上記 (3)項のデバイスホールを構成する有機樹脂フ
ィルムをヒートスプレッダで支承する樹脂封止した半導
体装置において、前記ヒートスプレッダの封止樹脂に接
触する面の少なくとも一部に無機物の薄膜で被覆したこ
とを特徴とする半導体装置。 (5)樹脂封止されるリードフレームのインナ−リード部
において、その封止樹脂に接触する下面、上面および側
面であって、それらの少なくとも一部に無機物の薄膜で
被覆したことを特徴とする前項 (1),(2),(3)或いは(4)
の何か記載の半導体装置である。In order to achieve the above object, the present invention has the following structures. That is, (1) in a semiconductor device in which a semiconductor element, a lead frame including a die pad on which the semiconductor element is mounted, a resin-sealed structure in which electrodes provided in the element and inner leads of the lead frame are connected by a thin wire, A semiconductor device, which is in contact with a sealing resin of the die pad and is a lower surface and a side surface, at least a part of which is covered with an inorganic thin film. (2) In a semiconductor device in which a semiconductor element, a lead frame equipped with a heat spreader for mounting the same, a resin-sealed structure in which electrodes provided in the element and inner leads of the lead frame are connected by a thin wire, 2. A semiconductor device, comprising: an upper surface and a side surface in contact with the sealing resin, and at least a part of these being covered with an inorganic thin film. (3) A semiconductor element, a composite lead frame formed by joining a lead frame and a TAB or FPC having a device hole for mounting the semiconductor element, an electrode provided on the element, and an inner lead of the TAB or FPC with a thin wire. In a semiconductor device in which the constituents connected with each other are resin-encapsulated, the organic resin film forming the device hole is in contact with the encapsulating resin, and is the lower surface, at least a part of which is covered with an inorganic thin film. A semiconductor device characterized by. (4) In a semiconductor device in which the organic resin film forming the device hole of the above item (3) is resin-sealed by a heat spreader, at least a part of the surface of the heat spreader that contacts the sealing resin is coated with an inorganic thin film. A semiconductor device characterized by the above. (5) In the inner lead portion of the lead frame to be resin-sealed, the lower surface, the upper surface and the side surface in contact with the sealing resin, at least a part of which is covered with a thin film of an inorganic material. (1), (2), (3) or (4)
The semiconductor device described in one of the above.
【０００９】この様に本発明は、半導体装置の構成体に
おける封止樹脂との剪断や剥離が起こりやすい部分に無
機物の薄膜被覆を形成することにより、この無機被膜が
封止樹脂との密着性が極めて良好であるため、両者が強
固に接合し、接着強度の大きい界面とすることができ
て、水分を吸着しても接着が破壊することがない。As described above, according to the present invention, a thin film coating of an inorganic material is formed on a portion of the structure of the semiconductor device which is likely to be sheared or peeled off from the sealing resin. Is extremely good, the two can be firmly bonded to form an interface having a high adhesive strength, and the adhesive will not be broken even if moisture is adsorbed.
【００１０】以下に本発明を詳細に説明する。本発明に
おける薄膜被覆を形成する無機物は、Ａｌ、Ａｌ酸化物
（Ａｌx Ｏy）、Ｓｉ酸化物（Ｓｉx Ｏy ）、Ｓｉ窒化
物（Ｓｉx Ｎy ）、Ｔｉ或いはＴｉ酸化物（Ｔｉ
x Ｏy ）、Ｃｒ酸化物（Ｃｒx Ｏy ）等であり、これら
を溶射、イオンプレーティング等のドライコーティング
法により一層或いは複数層に被覆する。このコーティン
グ工程の一例をリードフレームの被覆例で示せば、製品
厚さの素材をエッチィング或いはプレスで所定にリード
フレーム形状に成形し、電極部にＡｇメッキを施した
後、無機被覆の不要部分をマスキングしてから前記無機
物の少なくとも１種類をドライコーティングする。ま
た、素材上下面の少なくとも一面にドライコーティング
し、不要部分をエッチングで除去してリードフレームを
成形する方法でもよい。膜厚は１００オングストローム
から数十μｍの範囲とすれば十分である。その後ダイパ
ッドに半導体チップを搭載しダイボンディングしてから
所定の工程でワイヤボンディングし、モールド金型に導
入してエポキシ系樹脂でモールドする。上記無機物のド
ライコーティング法は特別な手段を必要とすることな
く、それ自体通常の方法を用いればよい。The present invention will be described in detail below. Inorganic material to form a thin film coating of the present invention, Al, Al oxide (Al x O y), Si oxide (Si x O y), Si nitride (Si x N y), Ti or Ti oxides (Ti
x O y ), Cr oxide (Cr x O y ), etc., and these are coated in a single layer or a plurality of layers by a dry coating method such as thermal spraying or ion plating. An example of this coating process is shown in the lead frame coating example. A material having a product thickness is formed into a predetermined lead frame shape by etching or pressing, and the electrode portion is plated with Ag. After masking, at least one kind of the inorganic material is dry-coated. Alternatively, the lead frame may be formed by dry-coating at least one of the upper and lower surfaces of the material and removing unnecessary portions by etching. It is sufficient that the film thickness is in the range of 100 angstrom to several tens of μm. Thereafter, a semiconductor chip is mounted on the die pad, die-bonded, wire-bonded in a predetermined process, introduced into a molding die and molded with an epoxy resin. The dry coating method of the above-mentioned inorganic substance does not require any special means and may be a usual method per se.
【００１１】無機物としてＡｌ，Ｓｉ，Ｔｉ等の酸化物
（一部窒化物）を用いるのは耐蝕性および耐熱性に優
れ、しかも、封止樹脂との密着性が極めて良好であるか
らである。また、ＡｌやＴｉは被覆後大気中に露される
と酸化（Ａｌ2 Ｏ3 ，ＴｉＯ2）し、上記と同様の効果
を奏する。上記酸化物の他にＣｒ2 Ｏ3 ，ＺｒＯ，Ｃｅ
Ｏ2 ，ＴｈＯ2 ，ＭｇＯ，ＢｅＯ等を用いてもよく、ま
た窒化物としてＺｒＮ，ＨｆＮ，ＶＮ，ＣｒＮ，Ａｌ
Ｎ，ＢＮ等の皮膜も適用可能とする。尚、リードフレー
ム、ダイパッド、或いはヒートスプレッダには、無機被
覆する前の工程で予めこれらの表面をダル加工しておく
ことが好ましい。すなわち表面を粗面にすることによ
り、封止樹脂との接着性或いは無機被膜の接合力を向上
させることができる。この粗面形成は、例えば粗面にす
る必要のない部分をマスキングし、必要部分をエッチン
グ等の手段で部分的に行うことも可能である。The use of oxides (partially nitrides) of Al, Si, Ti, etc. as the inorganic substances is because they are excellent in corrosion resistance and heat resistance, and also have extremely good adhesion with the sealing resin. Further, Al and Ti are oxidized (Al 2 O 3 , TiO 2 ) when exposed to the air after coating, and the same effect as described above is obtained. In addition to the above oxides, Cr 2 O 3 , ZrO, Ce
O 2 , ThO 2 , MgO, BeO, or the like may be used, and ZrN, HfN, VN, CrN, Al as nitrides may be used.
A coating of N, BN, etc. is also applicable. The lead frame, die pad, or heat spreader is preferably dull-processed on their surfaces in advance in a step before inorganic coating. That is, by roughening the surface, the adhesiveness with the sealing resin or the bonding force of the inorganic coating can be improved. The rough surface can be formed, for example, by masking a portion that does not need to be rough and partially performing a necessary portion by etching or the like.
【００１２】図１乃至図５は本発明半導体装置の実施態
様を断面で示す。図６と同一部分には同一符号を用いて
いるのでその説明は省略する。図１は半導体チップ２を
ダイパッド３に搭載接合したタイプの半導体装置であっ
て、ダイパッド３の裏面３ａおよび側面３ｂに無機被膜
１４を被覆している。図２は図１の半導体装置におい
て、更にリードフレーム１のインナ−リード１ａ下面１
ｂおよび側面１ｃに無機被膜１４を被覆している場合を
示している。本発明では上記態様の外に、ＴＡＢ(Tape
Automated Bondinng) やＦＰＣ(Flex Printed Curcuit)
とリードフレームとを組立てた複合リードフレームを使
用する半導体装置においても、ＴＡＢ或いはＦＰＣの裏
面、若しくはこれらの支持の基盤（ダイパド或いはヒー
トスプレッダ）を設ける場合には、この基盤の封止樹脂
に接触する上面および下面の一部又は全部に無機被膜の
形成を適用できる。図３はＴＡＢテープ１６とリードフ
レーム１を組立てた複合リードフレームタイプの半導体
装置であり、ダイパッド３を接合したデバイスホールを
構成する樹脂１９の下面１９ａに無機被膜１４を被覆し
てた例である。図４は半導体チップ２をヒートスプレッ
ダー１７に直接搭載接合したタイプの半導体装置であっ
て、該ヒートスプレッダ１７の封止樹脂に接する上面１
７ａ，側面１７ｂ、並びに必要によりインナーリード１
の下面１ｂ，側面１ｃ，更には上面を含めてそれらの少
なくとも一部分に無機被膜１８，１５を被覆している。
図５は、図３の半導体装置におけるダイパッド３接合の
樹脂１９を支承するヒートスプレッダ１７を設けたタイ
プであって、該ヒートスプレッダ１７の封止樹脂に接す
る上面１７ａおよび側面１７ｂにも無機被膜１８を被覆
している。なお、上記それぞれの態様において、図１、
図２および図３に示すように、リードフレームのインナ
−リードの無機被覆は必ずしも実施しなくてよく、必要
に応じて選択すればよい。また、ダイパッド、リードフ
レームのインナーリードおよびダイパッド等に行う無機
被覆は、封止樹脂と接触する全面に行うことがより好ま
しいが、下面やコーナ部のような封止樹脂との剥離、破
壊が起きやすい部分を選択して実施することができる。1 to 5 are sectional views showing an embodiment of the semiconductor device of the present invention. The same parts as those in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. FIG. 1 shows a semiconductor device of a type in which a semiconductor chip 2 is mounted on and bonded to a die pad 3, and a back surface 3a and a side surface 3b of the die pad 3 are covered with an inorganic coating 14. FIG. 2 shows the lower surface 1 of the inner lead 1a of the lead frame 1 in the semiconductor device of FIG.
The case where the inorganic coating 14 is coated on b and the side surface 1c is shown. In the present invention, in addition to the above aspect, TAB (Tape
Automated Bondinng) and FPC (Flex Printed Curcuit)
Also in a semiconductor device using a composite lead frame in which a lead frame and a lead frame are assembled, the back surface of the TAB or FPC, or a base (die pad or heat spreader) for supporting these is contacted with the sealing resin of the base. The formation of the inorganic coating can be applied to part or all of the upper surface and the lower surface. FIG. 3 shows a composite lead frame type semiconductor device in which the TAB tape 16 and the lead frame 1 are assembled, and is an example in which the lower surface 19a of the resin 19 forming the device hole to which the die pad 3 is bonded is coated with the inorganic coating 14. .. FIG. 4 shows a semiconductor device of a type in which a semiconductor chip 2 is directly mounted on and bonded to a heat spreader 17, and an upper surface 1 of the heat spreader 17 in contact with a sealing resin.
7a, side surface 17b, and inner lead 1 if necessary
At least a part of the lower surface 1b, the side surface 1c, and further the upper surface thereof are covered with the inorganic coatings 18 and 15.
FIG. 5 shows a type in which a heat spreader 17 for supporting a resin 19 for joining the die pad 3 in the semiconductor device of FIG. is doing. Note that in each of the above modes, FIG.
As shown in FIGS. 2 and 3, the inorganic coating of the inner leads of the lead frame does not necessarily have to be carried out, and may be selected as required. Further, it is more preferable to apply the inorganic coating on the die pad, the inner lead of the lead frame, the die pad, etc. to the entire surface in contact with the encapsulation resin, but peeling or destruction with the encapsulation resin such as the lower surface or the corner portion occurs. The easy part can be selected and implemented.
【００１３】[0013]
【実施例】図１に示す半導体装置を樹脂封止した後、温
度２８℃、湿度９５％に保持した雰囲気に表１に示す各
種時間放置し、その後回路基盤へのハンダ付けと同一条
件である２３０〜２６０℃×５〜１０秒の加熱を行っ
た。本発明装置にはダイパッド下面および側面にイオン
プレーティング法でＳｉＯx の薄膜を被覆した。比較の
ためにコーティングなしのものを同様に処理した。加熱
後の樹脂のくラック発生状況を調査した。結果を表１に
示す。EXAMPLE After the semiconductor device shown in FIG. 1 was sealed with resin, the semiconductor device was left in an atmosphere kept at a temperature of 28 ° C. and a humidity of 95% for various times shown in Table 1 and then the same conditions as soldering to a circuit board were applied. Heating was performed at 230 to 260 ° C. for 5 to 10 seconds. In the device of the present invention, the lower surface and the side surface of the die pad were coated with a thin film of SiO x by the ion plating method. For comparison, the uncoated one was treated similarly. The occurrence of resin racks after heating was investigated. The results are shown in Table 1.
【００１４】[0014]
【表１】 [Table 1]
【００１５】表１の検査結果において、分母は試料数、
分子はくラック発生試料数であり、これから明らかのよ
うに、本発明装置は加湿雰囲気で２００時間経過後もく
ラックの発生が見られなかったが、無機コーティングな
しの比較試料ではかなりの試料にくラックの発生が見ら
れた。In the inspection results of Table 1, the denominator is the number of samples,
It is the number of molecular racks generated. As is clear from this, the apparatus of the present invention showed no generation of racks even after 200 hours in a humidified atmosphere. The occurrence of racks was observed.
【００１６】[0016]
【発明の効果】以上のように本発明によれば、半導体装
置の構成体必要部分にドライコーティングによる無機物
の薄膜を被覆することにより、封止樹脂との接着が非常
に強固になされ、水分を吸着しても接着が剥離したり破
壊が起こらず、そのため水分が界面に溜まることがない
ので従来問題になっていたリフロー実装時の水分の急激
な膨脹によるくラックの発生も起きない。また接着剥離
も起きないのでダイパッドコーナーでの応力集中も無
く、極めて信頼性の高い半導体装置を提供できる。な
お、ドライコーティングも従来の方式を応用でき、安価
な製造が可能である。As described above, according to the present invention, by coating the thin film of the inorganic material by dry coating on the necessary portion of the semiconductor device structure, the adhesion with the encapsulating resin is made very strong and the moisture is prevented. Even if it is adsorbed, the adhesive does not peel off or break, and water does not accumulate at the interface. Therefore, the rack does not occur due to the rapid expansion of water during reflow mounting, which has been a problem in the past. Further, since no peeling of the adhesive occurs, stress concentration at the corners of the die pad does not occur, and a highly reliable semiconductor device can be provided. The conventional method can also be applied to dry coating, and inexpensive manufacturing is possible.
【図１】本発明半導体装置の実施態様を示す断面説明
図。FIG. 1 is a sectional explanatory view showing an embodiment of a semiconductor device of the present invention.
【図２】本発明半導体装置の他の実施態様を示す断面説
明図。FIG. 2 is an explanatory cross-sectional view showing another embodiment of the semiconductor device of the present invention.
【図３】本発明半導体装置その他の実施態様を示す断面
説明図FIG. 3 is an explanatory sectional view showing a semiconductor device according to another embodiment of the present invention.
【図４】本発明半導体装置の別の実施態様を示す断面説
明図。FIG. 4 is a cross-sectional explanatory view showing another embodiment of the semiconductor device of the present invention.
【図５】本発明半導体装置の更に別の実施態様を示す断
面説明図。FIG. 5 is an explanatory sectional view showing still another embodiment of the semiconductor device of the present invention.
【図６】従来の半導体装置の断面説明図。FIG. 6 is an explanatory cross-sectional view of a conventional semiconductor device.
【図７】従来のダイパッドの形態を示す図。FIG. 7 is a view showing a form of a conventional die pad.
【図８】従来の他のダイパッドの形態を示す図。FIG. 8 is a view showing another form of the conventional die pad.
【図９】従来の別のダイパッドの形態を示す図。FIG. 9 is a diagram showing another conventional die pad configuration.
１：リードフレーム １ａ：インナ−リード １ｂ：アウターリード ２：半導体チップ ３：ダイパッド ７：樹脂封止 １０：クラック １４，１５，１８：無機被膜 １６：ＴＡＢテープ １７：ヒートスプレッダ １９：樹脂 1: Lead frame 1a: Inner lead 1b: Outer lead 2: Semiconductor chip 3: Die pad 7: Resin encapsulation 10: Cracks 14, 15, 18: Inorganic coating 16: TAB tape 17: Heat spreader 19: Resin
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成５年３月１９日[Submission date] March 19, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００４[Correction target item name] 0004
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００４】そのため半導体装置の出荷に際して防湿の
ための特別梱包を行ったり、基盤実装時間を短時間にす
ることを要請したり、更には基盤実装前に吸湿品の空焼
きを実施するなどの対策がとられるが、これらの方法に
は極めて手数が掛ると共に需要先での対応が必要となり
って好ましくない。For this reason, measures such as special packaging for preventing moisture when shipping semiconductor devices, requesting that the board mounting time be shortened, and baking the hygroscopic product before board mounting are taken. However, these methods are not preferable because they are extremely troublesome and need to be dealt with by the customer.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１０[Correction target item name] 0010
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１０】以下に本発明を詳細に説明する。本発明に
おける薄膜被覆を形成する無機物は、Ａｌ、Ａｌ酸化物
（Ａｌx Ｏy）、Ｓｉ酸化物（Ｓｉx Ｏy ）、Ｓｉ窒化
物（Ｓｉx Ｎy ）、Ｔｉ或いはＴｉ酸化物（Ｔｉ
x Ｏy ）、Ｃｒ酸化物（Ｃｒx Ｏy ）等であり、これら
を溶射、イオンプレーティング、プラズマＣＶＤ、スパ
ッタリング等のドライコーティング法により一層或いは
複数層に被覆する。このコーティング工程の一例をリー
ドフレームの被覆例で示せば、製品厚さの素材をエッチ
ィング或いはプレスで所定にリードフレーム形状に成形
し、電極部にＡｇメッキを施した後、無機被覆の不要部
分をマスキングしてから前記無機物の少なくとも１種類
をドライコーティングする。また、素材上下面の少なく
とも一面にドライコーティングし、不要部分をエッチン
グで除去してリードフレームを成形する方法でもよい。
膜厚は１００オングストロームから数十μｍの範囲とす
れば十分である。その後ダイパッドに半導体チップを搭
載しダイボンディングしてから所定の工程でワイヤボン
ディングし、モールド金型に導入してエポキシ系樹脂で
モールドする。上記無機物のドライコーティング法は特
別な手段を必要とすることなく、それ自体通常の方法を
用いればよい。The present invention will be described in detail below. Inorganic material to form a thin film coating of the present invention, Al, Al oxide (Al x O y), Si oxide (Si x O y), Si nitride (Si x N y), Ti or Ti oxides (Ti
x O y), a Cr oxide (Cr x O y), and these
Spraying, ion plating, plasma CVD, spa
One layer or a plurality of layers are coated by a dry coating method such as tattering . An example of this coating process is shown in the lead frame coating example. A material having a product thickness is formed into a predetermined lead frame shape by etching or pressing, and the electrode portion is plated with Ag. After masking, at least one kind of the inorganic material is dry-coated. Alternatively, the lead frame may be formed by dry-coating at least one of the upper and lower surfaces of the material and removing unnecessary portions by etching.
It is sufficient that the film thickness is in the range of 100 angstrom to several tens of μm. Thereafter, a semiconductor chip is mounted on the die pad, die-bonded, wire-bonded in a predetermined process, introduced into a molding die and molded with an epoxy resin. The dry coating method of the above-mentioned inorganic substance does not require any special means and may be a usual method per se.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１３[Correction target item name] 0013
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１３】[0013]
【実施例】図１に示す半導体装置を樹脂封止した後、温
度２８℃、湿度９５％に保持した雰囲気に表１に示す各
種時間放置し、その後回路基盤へのはんだ付けと同一条
件である２３０〜２６０℃×５〜１０秒の加熱を行っ
た。本発明装置にはダイパッド下面および側面にプラズ
マＣＶＤ法でＳｉＯx の薄膜を被覆した。比較のために
コーティングなしのものを同様に処理した。加熱後の樹
脂のクラック発生状況を調査した。結果を表１に示す。EXAMPLE After the semiconductor device shown in FIG. 1 was sealed with resin, the semiconductor device was left in an atmosphere kept at a temperature of 28 ° C. and a humidity of 95% for various times shown in Table 1, and then soldered to a circuit board under the same conditions. Heating was performed at 230 to 260 ° C. for 5 to 10 seconds. Plasma die pad bottom surface and side surfaces to the present invention apparatus
A thin film of SiO x was coated by the CVD method . For comparison, the uncoated one was treated similarly. The crack generation state of the resin after heating was investigated. The results are shown in Table 1.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１５[Correction target item name] 0015
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１５】表１の検査結果において、分母は試料数、
分子はクラック発生試料数であり、これから明らかのよ
うに、本発明装置は加湿雰囲気で２００時間経過後もク
ラックの発生が見られなかったが、無機コーティングな
しの比較試料ではかなりの試料にクラックの発生が見ら
れた。In the inspection results of Table 1, the denominator is the number of samples,
The molecule is the number of cracked samples .
No racking was observed, but a significant amount of cracking was observed in the comparative sample without the inorganic coating.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１６】[0016]
【発明の効果】以上のように本発明によれば、半導体装
置の構成体必要部分にプラズマＣＶＤによる無機物の薄
膜を被覆することにより、封止樹脂との接着が非常に強
固になされ、水分を吸着しても接着が剥離したり破壊が
起こらず、そのため水分が界面に溜まることがないので
従来問題になっていたリフロー実装時の水分の急激な膨
脹によるクラックの発生も起きない。また接着剥離も起
きないのでダイパッドコーナーでの応力集中も少く、極
めて信頼性の高い半導体装置を提供できる。なお、ドラ
イコーティングも従来の方式を応用でき、安価な製造が
可能である。As described above, according to the present invention, by coating the required portion of the semiconductor device structure with the thin film of the inorganic material by plasma CVD , the adhesion with the sealing resin is made very strong and moisture is prevented. Even if it is adsorbed, the adhesive does not peel off or break, and therefore moisture does not accumulate at the interface, so that cracking due to rapid expansion of moisture during reflow mounting, which has been a problem in the past, does not occur. Further, since no peeling of the adhesive occurs, the stress concentration at the corners of the die pad is small, and a highly reliable semiconductor device can be provided. The conventional method can also be applied to dry coating, and inexpensive manufacturing is possible.
Claims (5)
ドを備えたリードフレームと、前記素子に設けた電極と
リードフレームのインナーリードとを細線で連結した構
成体を樹脂封止した半導体装置において、前記ダイパッ
ドの封止樹脂と接触する面の少なくとも一部分を無機物
の薄膜で被覆したことを特徴とする半導体装置。1. A semiconductor device comprising a semiconductor element, a lead frame provided with a die pad for mounting the semiconductor element, a resin-sealed structure in which electrodes provided on the element and inner leads of the lead frame are connected by a thin wire, A semiconductor device, wherein at least a part of a surface of the die pad that contacts the sealing resin is covered with an inorganic thin film.
プレッダを備えたリードフレームと、前記素子に設けた
電極とリードフレームのインナーリードとを細線で連結
した構成体を樹脂封止した半導体装置において、前記ヒ
ートスプレッダの封止樹脂に接触する面の少なくとも一
部を無機物の薄膜で被覆したことを特徴とする半導体装
置。2. A semiconductor device comprising a semiconductor element, a lead frame equipped with a heat spreader for mounting the semiconductor element, and a resin-sealed structure in which electrodes provided on the element and inner leads of the lead frame are connected by a thin wire. A semiconductor device, wherein at least a part of a surface of the heat spreader that contacts the sealing resin is covered with a thin film of an inorganic material.
ホールを備えたＴＡＢあるいはＦＰＣとリードフレーム
とが接合してなる複合リードフレームと、前記素子に設
けた電極とＴＡＢ或いはＦＰＣのインナ−リードとを細
線で連結した構成体を樹脂封止した半導体装置におい
て、前記デバイスホールを構成する有機樹脂フィルムの
上、下面又はその一部を無機物の薄膜で被覆したことを
特徴とする半導体装置。3. A composite lead frame formed by joining a semiconductor element, a TAB or FPC having a device hole for mounting the semiconductor element and a lead frame, an electrode provided on the element, and an inner lead of the TAB or FPC. A semiconductor device in which a structure in which the above are connected by a thin wire is resin-sealed, and an upper surface, a lower surface, or a part of the organic resin film forming the device hole is covered with a thin film of an inorganic material.
機樹脂フィルムをヒートスプレッダで支承する樹脂封止
した半導体装置において、前記ヒートスプレッダの封止
樹脂に接触する面の少なくとも一部を無機物の薄膜で被
覆したことを特徴とする半導体装置。4. A resin-sealed semiconductor device in which an organic resin film forming a device hole according to claim 3 is supported by a heat spreader, and at least a part of a surface of the heat spreader that contacts the sealing resin is covered with an inorganic thin film. A semiconductor device characterized by the above.
−リードを、その封止樹脂と接触する少なくとも一部に
無機物の薄膜で被覆したことを特徴とする請求項１，
２，３或いは４の何か記載の半導体装置。5. The inner lead of a resin-sealed lead frame is coated with an inorganic thin film on at least a portion thereof in contact with the sealing resin.
2. A semiconductor device according to 2, 3, or 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4071718A JPH05275598A (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4071718A JPH05275598A (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05275598A true JPH05275598A (en) | 1993-10-22 |
Family
ID=13468586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4071718A Pending JPH05275598A (en) | 1992-03-27 | 1992-03-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05275598A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883439A (en) * | 1996-03-19 | 1999-03-16 | Nec Corporation | Semiconductor device molded in plastic package free from crack by virtue of organic stress relaxation layer |
| JP2006165498A (en) * | 2004-11-10 | 2006-06-22 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method thereof |
| US8093713B2 (en) | 2007-02-09 | 2012-01-10 | Infineon Technologies Ag | Module with silicon-based layer |
| JP2018098251A (en) * | 2016-12-08 | 2018-06-21 | 株式会社豊田中央研究所 | Semiconductor module and method for manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59144159A (en) * | 1983-02-07 | 1984-08-18 | Sumitomo Electric Ind Ltd | Plastic-sealed ic |
| JPS62112356A (en) * | 1985-11-11 | 1987-05-23 | Furukawa Electric Co Ltd:The | Lead frame |
| JPS63308357A (en) * | 1987-06-10 | 1988-12-15 | Shinko Electric Ind Co Ltd | Lead frame for semiconductor device |
| JPH03191560A (en) * | 1989-12-20 | 1991-08-21 | Nec Corp | Resin-sealed semiconductor device |
-
1992
- 1992-03-27 JP JP4071718A patent/JPH05275598A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59144159A (en) * | 1983-02-07 | 1984-08-18 | Sumitomo Electric Ind Ltd | Plastic-sealed ic |
| JPS62112356A (en) * | 1985-11-11 | 1987-05-23 | Furukawa Electric Co Ltd:The | Lead frame |
| JPS63308357A (en) * | 1987-06-10 | 1988-12-15 | Shinko Electric Ind Co Ltd | Lead frame for semiconductor device |
| JPH03191560A (en) * | 1989-12-20 | 1991-08-21 | Nec Corp | Resin-sealed semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883439A (en) * | 1996-03-19 | 1999-03-16 | Nec Corporation | Semiconductor device molded in plastic package free from crack by virtue of organic stress relaxation layer |
| JP2006165498A (en) * | 2004-11-10 | 2006-06-22 | Fuji Electric Holdings Co Ltd | Semiconductor device and manufacturing method thereof |
| US8093713B2 (en) | 2007-02-09 | 2012-01-10 | Infineon Technologies Ag | Module with silicon-based layer |
| DE102008008515B4 (en) * | 2007-02-09 | 2012-10-04 | Infineon Technologies Ag | Module with silicon-based layer and manufacturing process |
| US8697497B2 (en) | 2007-02-09 | 2014-04-15 | Infineon Technologies Ag | Module with silicon-based layer |
| JP2018098251A (en) * | 2016-12-08 | 2018-06-21 | 株式会社豊田中央研究所 | Semiconductor module and method for manufacturing the same |
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