JPS6226834A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6226834A
JPS6226834A JP60166504A JP16650485A JPS6226834A JP S6226834 A JPS6226834 A JP S6226834A JP 60166504 A JP60166504 A JP 60166504A JP 16650485 A JP16650485 A JP 16650485A JP S6226834 A JPS6226834 A JP S6226834A
Authority
JP
Japan
Prior art keywords
oxide film
bonding
internal wiring
semiconductor device
sputtering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60166504A
Other languages
Japanese (ja)
Other versions
JPH04595B2 (en
Inventor
Shingo Ikeda
池田　慎悟
Shigeru Harada
繁 原田
Takeshi Noguchi
武志 野口
Reiji Tamaki
礼二 玉城
Mitsuyoshi Nakamura
充善 中村
Hiroshi Takagi
洋 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60166504A priority Critical patent/JPS6226834A/en
Publication of JPS6226834A publication Critical patent/JPS6226834A/en
Publication of JPH04595B2 publication Critical patent/JPH04595B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
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    • H01L2224/85009—Pre-treatment of the connector or the bonding area
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
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    • H01L2924/01—Chemical elements
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To limit the growth of the oxide film of the internal wirings to the exposing parts thereof, and at the same time, to facilitate the growth thereof by a method wherein an oxidizing process is executed after a sputtering process and a bonding process. CONSTITUTION:An oxide film 8 consisting of a material, such as metal, of internal wirings 3 is performed a sputtering on the exposing parts 3X and the part being covered with a fine metal wire 6 using argon gas before a wire bonding is executed. After that, they are dipped into hot water of about 80 deg.C for several minutes or several tens minutes, whereby the oxide film is formed on the surfaces of the exposing parts 3X as an insulating film 8 of a component consisting of Al2O3 and H2O. As the insulating film 8 is stable, an oxide film 8 protects the internal wirings 3 of a residual bonding pad 3A and so forth from corrosion due to moisture and so forth to intrude into the package during a long time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は劣化防止を施こした半導体装置の製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device in which deterioration is prevented.

〔従来の技術〕[Conventional technology]

第２図は従来の半導体装置を示す断面図であり、（１）
は半導体チップ、（２）は半導体チップの素子形成部分
、（３）は素子形成部分（２）上に設けられた内部配線
であって、こ＼ではアルミニウム配線、（４）は素子形
成部分（２）と内部配線（３）の上に形成され後者を湿
気等から守る保護用絶縁膜、（４Ａ）は保護用絶縁膜（
４）のボンディングのまめの開口部、（３Ａ）は内部配
線（３）の一部で開口部（４Ａ）の下にあるボンディン
グパッド、（５Ａ）はチップ（１）を固定するリードフ
レームのダイ部分、（５Ｂ）は半導体装置のリードとな
るリードフレームのリード部分、（６）は金属細線であ
って、と＼では金線、（７）はパッケージでありこ＼で
はプラスチックパッケージのプラスチック充填部分、（
ＳＸ）Ｖｉ内部配線（３）のチップ（１）の外部に露出
している露光部分である。FIG. 2 is a cross-sectional view showing a conventional semiconductor device, (1)
is a semiconductor chip, (2) is an element forming part of the semiconductor chip, (3) is an internal wiring provided on the element forming part (2), in this case aluminum wiring, and (4) is an element forming part ( 2) and internal wiring (3) to protect the latter from moisture, etc. (4A) is a protective insulating film (
4) The opening in the bonding hole, (3A) is a part of the internal wiring (3) and the bonding pad under the opening (4A), and (5A) is the die of the lead frame that fixes the chip (1). (5B) is the lead part of the lead frame that becomes the lead of the semiconductor device, (6) is the thin metal wire, and (7) is the package, and (7) is the plastic filling part of the plastic package. ,(
SX) This is the exposed portion of the Vi internal wiring (3) exposed to the outside of the chip (1).

従来の半導体装置は上記の如く構成されていたので、内
部配線の露出部分（３ｘ）はプラスチック充填部分（７
）で保護され、短時間酸につかる程度では劣化しないよ
うになっていた。Since the conventional semiconductor device was constructed as described above, the exposed portion (3x) of the internal wiring was replaced by the plastic filled portion (7x).
), so that it would not deteriorate even if exposed to acid for a short time.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記のような従来の半導体装置では、長時ｉＪをかけて
リード部分（５Ｂ）とプラスチック充填部分のすき間か
ら侵入して来る湿気等による劣化に露出部分（３Ｘ）は
無力であり、導通不良を起すといっな問題点が有った。In the conventional semiconductor device as described above, the exposed part (3X) is powerless against deterioration due to moisture, etc. that enters through the gap between the lead part (5B) and the plastic filling part after being subjected to iJ for a long time, resulting in poor conduction. There was a problem with it.

この発明はパッケージが湿気等の腐蝕の原因になるもの
の侵入を食い止められない場合でも、劣化を生じない半
導体装置の製造方法を提供することを目的としている。An object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause deterioration even when the package cannot prevent corrosion-causing substances such as moisture from entering the package.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置の製造方法は、チップの内部
配線の表面層を不活性元素を含むガスでスパッタリング
する工程と前記内部配線の一部であるポンディンパッド
に金属細線をボンディングする工程との後に前記内部配
線の表面層を酸化するようにした方法である。A method for manufacturing a semiconductor device according to the present invention includes the steps of sputtering the surface layer of internal wiring of a chip with a gas containing an inert element, and bonding a thin metal wire to a bond pad that is a part of the internal wiring. In this method, the surface layer of the internal wiring is oxidized later.

〔作用〕[Effect]

この発明においては、スパッタリングする工程とボンデ
ィングする工程の後に、酸化する工程を施こすことによ
り、内部配線の露出部分にその酸化被膜の成長する部分
を限定すると共に、その成長を容易にする。In the present invention, by performing an oxidation step after the sputtering step and the bonding step, the portion where the oxide film grows is limited to the exposed portion of the internal wiring, and the growth thereof is facilitated.

〔実施例〕〔Example〕

第１図はこの発明の一実施例を示す断面図であり、（８
）は内部配線（３）の金属等の材料の酸化膜、その他の
符号は第２図のものと同一のものである。FIG. 1 is a cross-sectional view showing an embodiment of the present invention.
) is an oxide film of a material such as metal of the internal wiring (3), and other symbols are the same as those in FIG.

この酸化膜〈８月よりイヤボンディングの前にアルゴン
ガスによるスパッタリングを第１図において露出部分（
３ｘ）と、金属細線（６）でかくれた部分に施こし、後
に約８０℃の温水に数分ないし数１０分間浸すことによ
り、露出部分（３ｘ）の表面上に化学式にして、Ａｌ２
Ｏ３・Ｈ２Ｏなる成分の絶縁膜（８）として形成される
。This oxide film was sputtered with argon gas from August before ear bonding on the exposed area (see Figure 1).
Al
It is formed as an insulating film (8) of O3.H2O.

この実施例は上記のようにして形成した絶縁膜（８）が
安定なため酸化膜（８）が長時間の内にパッケージ内に
浸入して来る湿気等による残りのボンデインパッド（３
Ａ）等の内部配線（３）ヲ腐触から保護することは明ら
かである。In this embodiment, since the insulating film (8) formed as described above is stable, the oxide film (8) will remain on the bond pad (3) due to moisture entering the package over a long period of time.
It is clear that the internal wiring (3) such as A) is protected from corrosion.

なお上記実施例ではアルゴンガスでスパッタリングする
例について述べたが他の不活性元素ガスであってもよく
、さらにこれらのガスに他のガスが含まれていてもよい
。In the above embodiments, an example in which sputtering is performed using argon gas has been described, but other inert element gases may be used, and other gases may also be included in these gases.

また、上記実施例ではスパッタリングする工程の後にボ
ンディング工程を施こしたが逆になってもよい。Further, in the above embodiment, the bonding process was performed after the sputtering process, but the process may be reversed.

また、上記実施例では約８０°Ｃの熱水で酸化する場合
について述べたがこれは最適条件であってこれより低温
でもまた高温でも同様の効果が期待できることは云うま
でもない。Further, in the above embodiment, the case of oxidation with hot water of about 80° C. was described, but this is the optimum condition, and it goes without saying that the same effect can be expected at lower or higher temperatures.

また、上記実施例は熱水で酸化する場合であったが他の
方法で酸化してもよく例えば過酸化水素水に浸したり、
＠極醇化したり、高温の水蒸気にさらしたり、酸化性プ
ラズマにさらしたりしてもよい０ また、上記実施例では内部配線の材料がアルミニウムで
ある場合について述べたが、その酸化膜が安定な絶縁膜
となるものなら他の材料でもよい。In addition, although the above example deals with oxidation using hot water, oxidation may be performed using other methods, such as immersion in hydrogen peroxide solution,
＠Although it is possible to make the material extremely thick, expose it to high-temperature water vapor, or expose it to oxidizing plasma, the above example describes the case where the material of the internal wiring is aluminum, but if the oxide film is stable. Other materials may be used as long as they serve as an insulating film.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の一実施例を示す断面図、第２図は従
来の半導体装置を示す断面図である。 図において、（１）はチップ、（３）は内部配線、（３
Ａ）はボンディングパッド、（３Ｘ）は内部配線の露出
部分、（６）は金属細線、（８）は酸化膜である。 なお、各図中、同一符号は同一ま念は相当部分を示す。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, (1) is the chip, (3) is the internal wiring, and (3) is the chip.
A) is a bonding pad, (3X) is an exposed portion of internal wiring, (6) is a thin metal wire, and (8) is an oxide film. In each figure, the same reference numerals indicate corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] （１）チップの内部配線の表面層を不活性元素を含むガ
スでスパッタリングする工程と 前記内部配線の一部であるボンディングパッドに金属細
線をボンディングする工程と 前記両工程完了後に前記内部配線の表面層を酸化する工
程とを 備えたことを特徴とする半導体装置の製造方法。(1) A step of sputtering the surface layer of the internal wiring of the chip with a gas containing an inert element, a step of bonding a thin metal wire to a bonding pad that is a part of the internal wiring, and a step of bonding the surface layer of the internal wiring after completing both of the above steps. A method for manufacturing a semiconductor device, comprising the step of oxidizing a layer.
JP60166504A 1985-07-26 1985-07-26 Manufacture of semiconductor device Granted JPS6226834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60166504A JPS6226834A (en) 1985-07-26 1985-07-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60166504A JPS6226834A (en) 1985-07-26 1985-07-26 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS6226834A true JPS6226834A (en) 1987-02-04
JPH04595B2 JPH04595B2 (en) 1992-01-08

Family

ID=15832581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60166504A Granted JPS6226834A (en) 1985-07-26 1985-07-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6226834A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529379A (en) * 1991-07-25 1993-02-05 Mitsubishi Electric Corp Semiconductor device and fabrication thereof
JP2008208442A (en) * 2007-02-28 2008-09-11 Hitachi Ltd Joining method using intermetallic compound

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232263A (en) * 1975-09-05 1977-03-11 Hitachi Ltd Semiconductor manufacturing process
JPS53141574A (en) * 1977-05-16 1978-12-09 Nec Corp Manufacture of semiconductor device
JPS5480679A (en) * 1977-12-09 1979-06-27 Nec Corp Manufacture for semiconductor device
JPS56116634A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5232263A (en) * 1975-09-05 1977-03-11 Hitachi Ltd Semiconductor manufacturing process
JPS53141574A (en) * 1977-05-16 1978-12-09 Nec Corp Manufacture of semiconductor device
JPS5480679A (en) * 1977-12-09 1979-06-27 Nec Corp Manufacture for semiconductor device
JPS56116634A (en) * 1980-02-20 1981-09-12 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0529379A (en) * 1991-07-25 1993-02-05 Mitsubishi Electric Corp Semiconductor device and fabrication thereof
JP2008208442A (en) * 2007-02-28 2008-09-11 Hitachi Ltd Joining method using intermetallic compound

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Publication number Publication date
JPH04595B2 (en) 1992-01-08

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