JPS643340B2 - - Google Patents
Info
- Publication number
- JPS643340B2 JPS643340B2 JP57192553A JP19255382A JPS643340B2 JP S643340 B2 JPS643340 B2 JP S643340B2 JP 57192553 A JP57192553 A JP 57192553A JP 19255382 A JP19255382 A JP 19255382A JP S643340 B2 JPS643340 B2 JP S643340B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- layer
- polysilicon layer
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010931 gold Substances 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 229910052737 gold Inorganic materials 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 10
- 239000000956 alloy Substances 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910018170 Al—Au Inorganic materials 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005275 alloying Methods 0.000 description 3
- 229910001020 Au alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- -1 Aluminum-gold Chemical compound 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
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- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
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- H01L2224/48505—Material at the bonding interface
- H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
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- Wire Bonding (AREA)
Description
【発明の詳細な説明】
本発明は、半導体集積回路等のボンデイング用
電極部の構造とその製造方法に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a bonding electrode portion of a semiconductor integrated circuit or the like and a method of manufacturing the same.
従来、この種の電極部は、第１図に示すよう
に、半導体基板１上に形成された、例えば二酸化
シリコン（SiO2）層のような絶縁層２を介し、
例えばアルミニウム（Al）からなるボンデイン
グ用電極３の形成し、さらに、半導体特性の安定
化と配線金属の保護のための絶縁膜４で、後に金
属細線を接続すべき箇所を除いて、覆われた構造
が一般的であつた。そして、外部回路との電気的
接続は、例えば金（Au）細線５を熱圧着技術に
よりAlからなるボンデイング用電極３に接着し
て行なわれていた。 Conventionally, as shown in FIG. 1, this type of electrode section has been formed on a semiconductor substrate 1 through an insulating layer 2 such as a silicon dioxide (SiO 2 ) layer.
For example, a bonding electrode 3 made of aluminum (Al) is formed, and then an insulating film 4 is formed to stabilize the semiconductor characteristics and protect the wiring metal, except for the areas where thin metal wires will be connected later. The structure was common. Electrical connection with an external circuit is made by bonding, for example, a thin gold (Au) wire 5 to a bonding electrode 3 made of Al using thermocompression bonding technology.
このため、Au細線５を電極３に接着した後に、
200〜300℃程度の熱処理工程を経た場合、Au細
線とAl電極の各金属が反応し、AuAl2、Au2Al等
の合金が不均一に形成されてしまい、これにより
Al層中に空孔が発生し、電気的抵抗が増大する
欠点および上記合金層と半導体基板上の絶縁層と
の接着強度が小さいため、Au細線が半導体基板
のボンデイング用電極からはく離してしまう欠点
等があつた。 For this reason, after bonding the Au thin wire 5 to the electrode 3,
When the heat treatment process is carried out at a temperature of about 200 to 300℃, each metal of the Au thin wire and the Al electrode reacts, and alloys such as AuAl 2 and Au 2 Al are formed non-uniformly.
Due to the disadvantage that vacancies are generated in the Al layer and the electrical resistance increases, and the adhesion strength between the alloy layer and the insulating layer on the semiconductor substrate is low, the Au thin wire peels off from the bonding electrode on the semiconductor substrate. There were some flaws.
さらに、本半導体素子を十分な気密封止を行な
わないで使用した場合には、電極部が保護用絶縁
膜で覆われていず、露出しているAl電極部が、
例えば水分等により容易に腐食されてしまうとい
う欠点があつた。 Furthermore, if this semiconductor element is used without sufficient hermetic sealing, the electrode part will not be covered with the protective insulating film and the exposed Al electrode part will be exposed.
For example, it has the disadvantage that it is easily corroded by moisture.
本発明はこれらの欠点を解消するため、ボンデ
イング用の新たな電極部構造を提供するものであ
り、以下図面について詳細に説明する。 In order to eliminate these drawbacks, the present invention provides a new electrode part structure for bonding, and will be described in detail below with reference to the drawings.
第２図は本発明の一実施例の断面図であつて、
１１は半導体基板、１２は絶縁層、１３はポリシ
リコン層、１４はAl−Au合金層、１５は保護用
絶縁膜、１６はAu細線である。このような半導
体装置は従来の同種装置の製造技術によつて容易
に製造できる。 FIG. 2 is a sectional view of an embodiment of the present invention,
11 is a semiconductor substrate, 12 is an insulating layer, 13 is a polysilicon layer, 14 is an Al-Au alloy layer, 15 is a protective insulating film, and 16 is an Au thin wire. Such a semiconductor device can be easily manufactured using conventional manufacturing techniques for similar devices.
本発明の電極構造は以上のようになつているた
め、Al−Au合金層１４はポリシリコン層１３と
広い面積で接合しており、さらに両者の境界面に
おいては、シリコン、金、アルミニウムの元素が
互いに反応し合い、機械的強度を大きくしてい
る。したがつて、従来、Al配線−Au細線の接合
で信頼性上問題とされていたボンデイング不良は
全く発生しないという利点がある。 Since the electrode structure of the present invention is configured as described above, the Al-Au alloy layer 14 is bonded to the polysilicon layer 13 over a wide area, and furthermore, at the interface between the two, elements of silicon, gold, and aluminum are formed. react with each other, increasing mechanical strength. Therefore, there is an advantage that bonding defects, which have conventionally been a reliability problem in bonding Al wiring and Au thin wire, do not occur at all.
なお、Al−Au合金の電気抵抗率は、例えば、
Au2Alで1.3×10-5Ω・cm、Au4Alで3.8×10-5
Ω・cmと一般の金属と同程度であり、得られる半
導体素子の電気的特性には全く影響を及ぼさない
ものである。 Note that the electrical resistivity of the Al-Au alloy is, for example,
1.3×10 -5 Ω・cm for Au 2 Al, 3.8×10 -5 for Au 4 Al
It has a resistance of Ω·cm, which is comparable to that of ordinary metals, and has no effect on the electrical characteristics of the resulting semiconductor device.
ところで、Alは、例えば水分の付着等によつ
て極めて短期間のうちに腐食されるのに対して、
Auは極めて高い耐食性を有しており、さらに、
Au−Al合金についても純Alに比して、著るしい
耐腐食性を有していることはよく知られている。
したがつて、第２図に示す本発明の構造は、配線
金属の耐腐食性の観点からも、従来構造に比べ、
大きな利点を有しているものである。とくに、現
在広く使用されているプラスチツクモールド集積
回路素子における故障がボンデイング部のAl層
の腐食によつて生じている事実から、本発明の構
造は、集積回路故障対策として大きな利点をもた
らすものである。 By the way, Al corrodes in a very short period of time due to adhesion of moisture, etc.
Au has extremely high corrosion resistance, and
It is well known that Au-Al alloys also have remarkable corrosion resistance compared to pure Al.
Therefore, the structure of the present invention shown in FIG. 2 is superior to the conventional structure from the viewpoint of corrosion resistance of wiring metal.
It has great advantages. In particular, in light of the fact that failures in plastic molded integrated circuit elements that are currently widely used are caused by corrosion of the Al layer in the bonding area, the structure of the present invention provides significant advantages as a countermeasure against integrated circuit failures. .
一方、本構造を作成するには、周知の方法によ
り半導体基板１１上に絶縁層１２、ポリシリコン
層１３を形成した後、AlとAuの少なくとも２層
を、最終的にAl−Au合金層１４が所定の形状に
なるように、例えば真空蒸着とホトリソグラフイ
ーにより形成する。次に、やはり周知の方法によ
り保護用絶縁膜１５を形成する。ついで、外部回
路との接続用としてAu細線１６をすでに形成し
たAu−Al多層膜上に熱圧着等により接着する。
以上の工程が終了した後に、200〜300℃の温度で
数分〜数十分間の熱処理を行なうことにより、
Al−Au合金層１４が形成され、極めて容易に本
発明の電極構造を形成することができる。 On the other hand, in order to create this structure, after forming an insulating layer 12 and a polysilicon layer 13 on a semiconductor substrate 11 by a well-known method, at least two layers of Al and Au are finally applied to an Al-Au alloy layer 14. For example, it is formed by vacuum evaporation and photolithography so that it has a predetermined shape. Next, a protective insulating film 15 is formed by a well-known method. Next, a thin Au wire 16 for connection to an external circuit is bonded onto the already formed Au--Al multilayer film by thermocompression bonding or the like.
After the above steps are completed, heat treatment is performed at a temperature of 200 to 300°C for several minutes to several tens of minutes.
An Al-Au alloy layer 14 is formed, and the electrode structure of the present invention can be formed very easily.
第３図は本発明の他の実施例の断面図であり、
やや厚く形成したAl層１７の両端に設けた保護
用絶縁膜１５の間のAl層上に金属をやや厚く設
けて熱処理し、Al−Au合金層１４が図示のよう
にでき、両端にAl層１７が存在する構造を示す。
本実施例の効果は上記の第２図の実施例と全く同
じである。 FIG. 3 is a sectional view of another embodiment of the present invention,
A slightly thicker metal layer is provided on the Al layer between the protective insulating films 15 provided at both ends of the Al layer 17 formed to be slightly thicker, and then heat treated to form an Al-Au alloy layer 14 as shown in the figure, with an Al layer at both ends. 17 is shown.
The effects of this embodiment are exactly the same as those of the embodiment shown in FIG. 2 above.
第４図は本発明のさらに他の実施例であり、上
述の第３図に述べた実施例において、Au層をよ
り薄く形成し、合金化熱処理を十分に施して保護
用絶縁膜１５に挾まれた部分を完全にAl−Au合
金層１４としたものであり、その効果は上述の第
２図の実施例と全く同じである。 FIG. 4 shows still another embodiment of the present invention, in which the Au layer is formed thinner and sufficiently heat-treated for alloying in the embodiment described in FIG. The covered portion is completely made into an Al--Au alloy layer 14, and the effect is exactly the same as the embodiment shown in FIG. 2 described above.
第５図は、上述のAlとAu層の合金化熱処理
（290℃、40時間）の前後（ａは熱処理前、ｂは熱
処理後）におけるAu細線の引張り強度の実測デ
ータであり、本発明の製法により、引張り強度が
大きくなることを示すものである。ここで、熱処
理時間を40時間としたが、合金化のためには上述
のようにせいぜい数十分程度の熱処理でよいが、
このデータはこれよりも長時間の熱処理を行なつ
ても悪影響のないことも示している。 Figure 5 shows the measured data of the tensile strength of the Au thin wire before and after the above-mentioned alloying heat treatment (290°C, 40 hours) of the Al and Au layers (a: before heat treatment, b: after heat treatment), and shows the tensile strength data of the thin Au wire of the present invention. This shows that the tensile strength increases depending on the manufacturing method. Here, the heat treatment time was set at 40 hours, but as mentioned above, heat treatment for at most several tens of minutes is sufficient for alloying.
This data also shows that longer heat treatments can be used without adverse effects.
以上説明したように、本発明の電極構造によれ
ば、AlまたはAuを主成分とする金属細線の電極
への接着不良、あるいは電極金属の腐食が防止で
き、さらに、金属細線の引張り強度が増大する等
の効果があり、半導体集積回路の長寿命化、故障
率の低下につながる利点がある。 As explained above, according to the electrode structure of the present invention, poor adhesion of the thin metal wire containing Al or Au as a main component to the electrode or corrosion of the electrode metal can be prevented, and the tensile strength of the thin metal wire can be increased. This has the advantage of extending the life of semiconductor integrated circuits and reducing failure rates.
第１図は従来の半導体装置の電極構造の断面
図、第２図、第３図、第４図はそれぞれ本発明の
半導体装置の電極構造の断面図、第５図は本発明
の製法により得た半導体装置の電極部に接続した
金属細線の引張り強度の実測データを示す図であ
る。
図において、１，１１……半導体基板、２，１
２……絶縁層、３，１７……アルミニウム電極、
４，１５……保護用絶縁膜、５，１６……金細
線、１３……ポリシリコン層、１４……アルミニ
ウム−金合金層。
FIG. 1 is a cross-sectional view of the electrode structure of a conventional semiconductor device, FIGS. 2, 3, and 4 are cross-sectional views of the electrode structure of the semiconductor device of the present invention, and FIG. 5 is a cross-sectional view of the electrode structure of the semiconductor device of the present invention. FIG. 2 is a diagram showing actual measurement data of the tensile strength of a thin metal wire connected to an electrode portion of a semiconductor device. In the figure, 1, 11...semiconductor substrate, 2, 1
2... Insulating layer, 3, 17... Aluminum electrode,
4, 15...Protective insulating film, 5, 16... Gold thin wire, 13... Polysilicon layer, 14... Aluminum-gold alloy layer.
Claims (1)
る半導体装置において、該半導体素子基板上に設
けた絶縁膜上にポリシリコン層および該ポリシリ
コン層に接してアルミニウムと金とを主成分とす
る合金層を有し、該合金層上に金または金を主成
分とする金属細線が接着されてなることを特徴と
する半導体装置の電極部構造。 ２ 半導体素子基板上に絶縁膜を介してポリシリ
コン層および該ポリシリコン層に接してアルミニ
ウムと金の少なくとも２層からなる多層金属膜を
形成した後、該多層金属膜上に金または金を主成
分とする金属細線を接着し、しかる後、加熱処理
により少なくとも前記金属細線下の前記多層金属
膜を合金化することを特徴とする半導体装置の電
極部構造の製造方法。[Claims] 1. In a semiconductor device in which a semiconductor element and an external circuit are connected by a thin metal wire, a polysilicon layer is provided on an insulating film provided on the semiconductor element substrate, and aluminum and gold are formed in contact with the polysilicon layer. 1. An electrode part structure for a semiconductor device, comprising an alloy layer containing gold as a main component, and gold or a thin metal wire containing gold as a main component bonded onto the alloy layer. 2. After forming a polysilicon layer and a multilayer metal film consisting of at least two layers of aluminum and gold in contact with the polysilicon layer through an insulating film on a semiconductor element substrate, gold or gold is mainly formed on the multilayer metal film. A method for manufacturing an electrode part structure of a semiconductor device, characterized in that thin metal wires as components are bonded, and then at least the multilayer metal film under the thin metal wires is alloyed by heat treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57192553A JPS5982737A (en) | 1982-11-04 | 1982-11-04 | Structure of electrode section of semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57192553A JPS5982737A (en) | 1982-11-04 | 1982-11-04 | Structure of electrode section of semiconductor device and its manufacture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5982737A JPS5982737A (en) | 1984-05-12 |
| JPS643340B2 true JPS643340B2 (en) | 1989-01-20 |
Family
ID=16293191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57192553A Granted JPS5982737A (en) | 1982-11-04 | 1982-11-04 | Structure of electrode section of semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5982737A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW426980B (en) * | 1999-01-23 | 2001-03-21 | Lucent Technologies Inc | Wire bonding to copper |
-
1982
- 1982-11-04 JP JP57192553A patent/JPS5982737A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5982737A (en) | 1984-05-12 |
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