JPH0693466B2 - Silicon semiconductor device manufacturing method - Google Patents
Silicon semiconductor device manufacturing methodInfo
- Publication number
- JPH0693466B2 JPH0693466B2 JP61130809A JP13080986A JPH0693466B2 JP H0693466 B2 JPH0693466 B2 JP H0693466B2 JP 61130809 A JP61130809 A JP 61130809A JP 13080986 A JP13080986 A JP 13080986A JP H0693466 B2 JPH0693466 B2 JP H0693466B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- chip
- semiconductor device
- back surface
- ohmic contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/03505—Sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05139—Silver [Ag] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置のチップの製造に関するもので、チ
ップを固着する時のチップ裏面のオーミック接触金属の
製法に関するものである。Description: TECHNICAL FIELD The present invention relates to manufacturing of a chip of a semiconductor device, and more particularly to a method of manufacturing an ohmic contact metal on the back surface of the chip when the chip is fixed.
従来、半導体装置に於て、ソフトソルダーを用いて、シ
リコンチップを固着する場合、チップ裏面のオーミック
接触金属材料として一般にNiが用いられている。Niで良
好なオーミック接触を得るためには450℃以上の高温で
不活性ガス雰囲気中でシンター処理を行ないしかる後
に、Niのシンター層を残し余分なNiを除去し、再度Niを
付着し、更に半田のなじみを良くするためAuを付着して
いた。Conventionally, in a semiconductor device, when a silicon chip is fixed by using a soft solder, Ni is generally used as an ohmic contact metal material on the back surface of the chip. In order to obtain a good ohmic contact with Ni, after performing sintering treatment in an inert gas atmosphere at a high temperature of 450 ° C. or higher, excess Ni is removed leaving the sintering layer of Ni, Ni is attached again, and further Au was attached to improve the familiarity of the solder.
この様な複雑な工程を採用する理由としては高温でシン
ター処理を行なう場合不活性ガス中の微量な酸素と反応
し、Niの表面が酸化され、次工程でのチップ固着に於け
る半田付け作業に不具合が生じるためである。The reason for adopting such a complicated process is that when performing sintering treatment at high temperature, it reacts with a small amount of oxygen in the inert gas, the surface of Ni is oxidized, and soldering work in the chip fixing in the next process. This is because there is a problem with.
上述した従来のNiのオーミック接触を得る方法では、シ
ンター後余分なNiを除去し、再度Niを付着する場合付着
する前の前処理のバラツキ及び蒸着する時の真空度のバ
ラツキ及び有機性の汚れ等の極小量の影響で、チップを
ソフトソルダーで固着した後に、機械的接触強度にバラ
ツキが大きく、信頼性又は、電気的特性に悪影響を及ぼ
していた。In the conventional method for obtaining the ohmic contact of Ni described above, excess Ni is removed after sintering, and when Ni is attached again, variations in pretreatment before attachment and variations in vacuum degree during vapor deposition and organic contamination Due to the influence of an extremely small amount, the mechanical contact strength greatly fluctuated after the chips were fixed by the soft solder, and the reliability or the electrical characteristics were adversely affected.
本発明の半導体装置に於けるシリコンチップ裏面のオー
ミック接触の製法は、上述した従来方法の不具合な点を
改良するためにある。シリコンチップ裏面オーミック接
触の電極構造としてNi−Ag−Auの３層構造を有すること
を特徴とする。先ずNi−Agを同一真空系で蒸着を行い、
しかる後に良好なオーミック接触を得るために比較的高
温（450℃以上）で、不活性ガス雰囲気中でシンター処
理を行い、Ni−Siのシンター層を得る。シンターを行う
際、不活性ガス中の微量なO2と従来はNiの表面と反応し
Niの酸化物が生成されると言う不具合が避けられなかっ
た。本発明によれば、Ni−Agの二層構造により、シンタ
ー中の不活性ガス中の微量なO2は貴金属であるAgにより
Niの表面はほぼ完全に保護される。又シンターの熱処理
により、NiとAgの界面で互いに拡散し合い、密着強度が
高まり、良好なオーミックが得られる。しかる後に更に
チップ固着時に半田ぬれ性を良くするためにNi−AgのAg
の表面にAuを蒸着しNi−Ag−Auの三層構造を得る。Auを
Agの表面に蒸着する際の熱でAuの粒子がAgと反応し良好
な密着が得られる。この様にして得られたシリコンチッ
プの裏面電極は次工程でチップを固着する時、ソフトソ
ルダーとのなじみが良好となる。The method of manufacturing the ohmic contact on the back surface of the silicon chip in the semiconductor device of the present invention is to improve the drawbacks of the above-mentioned conventional method. It is characterized in that it has a three-layer structure of Ni-Ag-Au as an electrode structure of ohmic contact on the back surface of the silicon chip. First, deposit Ni-Ag in the same vacuum system,
Then, in order to obtain a good ohmic contact, a sintering treatment is performed at a relatively high temperature (450 ° C. or higher) in an inert gas atmosphere to obtain a Ni—Si sintering layer. When sintering, the trace amount of O 2 in the inert gas reacts with the surface of Ni, which was traditionally used.
The problem that Ni oxide was generated was unavoidable. According to the present invention, due to the Ni-Ag double-layer structure, a trace amount of O 2 in the inert gas in the sinter is caused by the noble metal Ag.
The Ni surface is almost completely protected. Also, the heat treatment of the sinter causes the Ni and Ag to diffuse at the interface with each other, increasing the adhesion strength and obtaining a good ohmic contact. After that, in order to improve solder wettability when the chip is fixed, Ni-Ag Ag
Au is vapor-deposited on the surface of to obtain a three-layer structure of Ni-Ag-Au. Au
The heat of vapor deposition on the surface of Ag causes Au particles to react with Ag, and good adhesion can be obtained. The back surface electrode of the silicon chip thus obtained has good compatibility with the soft solder when the chip is fixed in the next step.
次に本発明について、第１図から第２図を参照して説明
する。第２図は、従来のシリコンチップ裏面の電極構造
断面図である。シリコンウェハ１の裏面に蒸着又はメッ
キによりNiを付着し、比較的高温で、シンターを行い、
Niシリサイド層２を形成し、コレクター層のオーミック
接触を得る。次に余分なNiの酸化物を硝酸等でエッチン
グし、Niシリサイド層の表面を露出させる。しかる後に
再度Ni.3を蒸着又はメッキにより約5000Å付着する。更
に半田とのなじみを良好ならしめるためにAu.5を蒸着又
はメッキにより付着し、しかる後に、ダイシングを行な
い、シリコン素子のチップ６を得ていた。Next, the present invention will be described with reference to FIGS. FIG. 2 is a sectional view of an electrode structure on the back surface of a conventional silicon chip. Ni is attached to the back surface of the silicon wafer 1 by vapor deposition or plating, and sintering is performed at a relatively high temperature.
The Ni silicide layer 2 is formed to obtain ohmic contact with the collector layer. Then, excess Ni oxide is etched with nitric acid or the like to expose the surface of the Ni silicide layer. After that, Ni.3 is attached again by vapor deposition or plating to about 5000 Å. Further, Au.5 was attached by vapor deposition or plating in order to make it fit well with the solder, and then dicing was performed to obtain a silicon element chip 6.
第１図は、本発明の製造方法によるシリコン素子チップ
裏面の電極構造断面図である。シリコンウェハ１の裏面
に蒸着法により、Ni及びAgの２層を同一真空系にて付着
する。この場合、Ni.3は約5000Å,Ag4は約10,000Åの厚
さにすればシンター工程中でNi表面の酸化は防止可能で
ある。次にNi−Agが蒸着されたウェハは一旦蒸着装置に
より取出し、不活性ガス雰囲気例えばN2,Ar中で比較的
高温450℃〜500℃の温度でシンター処理を行ないニッケ
ルシリサイド層２を生成することにより良好なオーミッ
ク接触を得る。しかる後にソフトソルダーとのぬれ性を
良くするため更にAu.5を約3000Åの厚さを蒸着する。こ
の場合Auの粒子が蒸着される際、Agと反応し、良好な密
着が得られるため新らためて熱処理を行う必要はない。
後にダイシングを行ない、シリコン素子のチップ６を得
る。FIG. 1 is a sectional view of an electrode structure on the back surface of a silicon element chip according to the manufacturing method of the present invention. Two layers of Ni and Ag are attached to the back surface of the silicon wafer 1 by the vapor deposition method in the same vacuum system. In this case, if the thickness of Ni.3 is about 5000Å and the thickness of Ag4 is about 10,000Å, the oxidation of Ni surface can be prevented during the sintering process. Next, the wafer on which Ni-Ag is vapor-deposited is once taken out by the vapor-deposition apparatus and subjected to sintering treatment at a relatively high temperature of 450 ° C. to 500 ° C. in an inert gas atmosphere such as N 2 or Ar to form a nickel silicide layer 2. As a result, good ohmic contact is obtained. Then, to improve the wettability with the soft solder, Au.5 is evaporated to a thickness of about 3000Å. In this case, when the Au particles are vapor-deposited, they react with Ag, and good adhesion is obtained, so that it is not necessary to newly perform heat treatment.
After that, dicing is performed to obtain a silicon element chip 6.
以上説明した様に、本発明の製造方法を用いてシリコン
素子チップの裏面の電極構造をNi−Ag−Auの３層構造に
することにより、次工程であるチップ固着工程に於ける
ソフトソルダーとのなじみ及びぬれ性の良好な安定した
プロセスが確立出来、これを応用した半導体装置に於て
は電気的特性，信頼度，及び歩留等が飛躍的に改善され
てその効果は非常に大きい。As described above, by using the manufacturing method of the present invention to form the electrode structure on the back surface of the silicon element chip into the three-layer structure of Ni-Ag-Au, the soft solder in the next chip fixing step can be obtained. A stable process with good compatibility and wettability can be established, and in a semiconductor device to which the process is applied, electrical characteristics, reliability, yield, etc. are dramatically improved, and the effect is very large.
第１図は、本発明の製造方法を用いたシリコンチップの
裏面電極構造の断面図、第２図は従来のシリコンチップ
の裏面電極構造の断面図である。 １……シリコンチップ、２……ニッケルシリサイド層、
３……Ni層、４……Ag層、５……Au層、６……シリコン
素子チップ。FIG. 1 is a sectional view of a back surface electrode structure of a silicon chip using the manufacturing method of the present invention, and FIG. 2 is a sectional view of a back surface electrode structure of a conventional silicon chip. 1 ... Silicon chip, 2 ... Nickel silicide layer,
3 ... Ni layer, 4 ... Ag layer, 5 ... Au layer, 6 ... Silicon element chip.
Claims (1)
同一真空系にて形成する工程と、シンター処理により前
記Ni層とシリコンウェハとの界面にニッケルシリサイド
層を形成する工程と、前記Ag層上にAu層を形成する工程
とを含むことを特徴とするシリコン半導体装置の製造方
法。1. A step of sequentially forming a Ni layer and an Ag layer on the back surface of a silicon wafer in the same vacuum system, a step of forming a nickel silicide layer at an interface between the Ni layer and the silicon wafer by a sintering process, And a step of forming an Au layer on the Ag layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61130809A JPH0693466B2 (en) | 1986-06-04 | 1986-06-04 | Silicon semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61130809A JPH0693466B2 (en) | 1986-06-04 | 1986-06-04 | Silicon semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62286236A JPS62286236A (en) | 1987-12-12 |
| JPH0693466B2 true JPH0693466B2 (en) | 1994-11-16 |
Family
ID=15043212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61130809A Expired - Lifetime JPH0693466B2 (en) | 1986-06-04 | 1986-06-04 | Silicon semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693466B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5027189A (en) * | 1990-01-10 | 1991-06-25 | Hughes Aircraft Company | Integrated circuit solder die-attach design and method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5287360A (en) * | 1976-01-16 | 1977-07-21 | Nec Home Electronics Ltd | Semiconductor device |
| JPS5614233A (en) * | 1979-07-17 | 1981-02-12 | Ricoh Co Ltd | Photosensitive heat-sensitive type recording member |
| JPS58164232A (en) * | 1982-03-24 | 1983-09-29 | Toshiba Corp | Semiconductor device |
-
1986
- 1986-06-04 JP JP61130809A patent/JPH0693466B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62286236A (en) | 1987-12-12 |
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