JPS62286236A - Silican semiconductor device - Google Patents
Silican semiconductor deviceInfo
- Publication number
- JPS62286236A JPS62286236A JP61130809A JP13080986A JPS62286236A JP S62286236 A JPS62286236 A JP S62286236A JP 61130809 A JP61130809 A JP 61130809A JP 13080986 A JP13080986 A JP 13080986A JP S62286236 A JPS62286236 A JP S62286236A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- silicon
- rear surface
- improve
- ohmic contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 6
- NTHWMYGWWRZVTN-UHFFFAOYSA-N sodium silicate Chemical compound [Na+].[Na+].[O-][Si]([O-])=O NTHWMYGWWRZVTN-UHFFFAOYSA-N 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910002696 Ag-Au Inorganic materials 0.000 claims description 3
- 150000003376 silicon Chemical class 0.000 claims description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 23
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract description 10
- 239000011261 inert gas Substances 0.000 abstract description 7
- 229910021334 nickel silicide Inorganic materials 0.000 abstract description 3
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052709 silver Inorganic materials 0.000 abstract description 2
- 238000009736 wetting Methods 0.000 abstract 2
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 238000005476 soldering Methods 0.000 abstract 1
- 238000007740 vapor deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4827—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/035—Manufacturing methods by chemical or physical modification of a pre-existing or pre-deposited material
- H01L2224/03505—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05083—Three-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05139—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05155—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体装置のチップの製造に関するもので、チ
ップを固着する時のチップ裏面のオーミック接触金属の
構造及びその製法に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the manufacture of chips for semiconductor devices, and relates to the structure of the ohmic contact metal on the back surface of the chip when the chip is fixed, and its method. It is related to the manufacturing method.
従来、半導体装置に於て、ソフトソルダーを用いて、シ
リコンチップを固着する場合、チップ裏面のオーミック
接触金属材料として一般にＮｉ が用いられている。Conventionally, when a silicon chip is fixed using a soft solder in a semiconductor device, Ni is generally used as an ohmic contact metal material on the back surface of the chip.
Ｎｉ で良好なオーミック接触を得るためには４５０℃
以上の高温で不活性ガス雰囲気中でンンター処理を行な
いしかる後に、Ｎｉのシンタ一層を残し余分なＮｉ を
除去し、再度Ｎｉを付着し、更に半田のなじみを良くす
るためＡｕを付着していた。450℃ to obtain good ohmic contact with Ni
After performing a nter treatment in an inert gas atmosphere at a high temperature above, excess Ni was removed leaving a layer of Ni sinter, Ni was re-deposited, and Au was further deposited to improve solder adhesion. .
この様な複雑な工程を採用する理由としてケよ高温でン
ンター処理を行なう場合不活性ガス中の微ｔな酸素と反
応し、Ｎｉ の表面が酸化され、次工程でのチップ固
着に於ける半田付は作業に不具合が生じるためである。The reason why such a complicated process is adopted is that when Ninter treatment is performed at a high temperature, the Ni surface reacts with a small amount of oxygen in the inert gas, oxidizing the Ni surface, and causing the solder to adhere to the chip in the next process. This is because problems may occur during the work.
上述した従来のＮｉ のオーミック接触を得る方法では
、シンター後余分なＮｉ を除去し、再度Ｎｉを付着
する場合付着する前の前処理のバラツキ及び蒸着する時
の真空度のバラツキ及び有機性の汚れ等の極小量の影響
で、チップをソフトソルダーで固着した後に、機械的接
触強度にバラツキが大きく、信頼性又は、を気的特性に
悪影響を及ぼしていた。In the conventional method of obtaining Ni ohmic contact described above, excess Ni is removed after sintering, and when Ni is re-deposited, there are variations in pretreatment before deposition, variations in the degree of vacuum during vapor deposition, and organic contamination. Due to the influence of extremely small amounts of , etc., after the chips are fixed with soft solder, there is a large variation in mechanical contact strength, which has an adverse effect on reliability and mechanical properties.
本発明の半導体装置に於けるシリコンチップ裏面のオー
ミック接触の構造及び製法は、上述した従来方法の不具
合な点を改良するためにある。シリコンチップ裏面オー
ミック接触の電極構造としてＮ ｉ −Ａｇ −ｋｌｌ
の３層構造を有することを特徴とする。先ずＮｉ−Ａｇ
を同−真空系で蒸着を行い、しかる後に良好なオーミッ
ク接触を得るために比較的高温（４５０℃以上）で、不
活性ガス雰囲気中でシンター処理を行い、Ｎｉ−８ｉの
シンタ一層を得る。シンターを行う際、不活性ガス中の
微量なＯｌと従来はＮｉの表面と反応しＮｉ の酸化物
が生成されると言う不具合が避けらｎなかった。本発明
によれば、Ｎｉ−Ａｇの二層構造により、シンター中の
不活性ガス中の微量なＯｌは貴金属であるＡｇによ）Ｎ
ｉの表面はほば完全に保護される。The structure and manufacturing method of the ohmic contact on the back surface of the silicon chip in the semiconductor device of the present invention are intended to improve the disadvantages of the above-mentioned conventional methods. Ni-Ag-kll as an electrode structure for ohmic contact on the back surface of silicon chip
It is characterized by having a three-layer structure. First, Ni-Ag
is vapor-deposited in the same vacuum system, and then sintered in an inert gas atmosphere at a relatively high temperature (450° C. or higher) to obtain good ohmic contact, thereby obtaining a sintered layer of Ni-8i. When performing sintering, conventionally, a small amount of O in the inert gas reacts with the Ni surface, resulting in the unavoidable problem that Ni oxide is produced. According to the present invention, due to the Ni-Ag two-layer structure, a trace amount of Ol in the inert gas in the sinter is replaced by the noble metal Ag)N.
The surface of i is almost completely protected.
又シンターの熱処理により、Ｎｉと勾の界面で互いに拡
散し合い、密着強度が高まυ、良好なオーミックが得ら
れる。しかる後に更にチップ固着時に半田ぬれ性を艮く
するためにＮｉ−ＡｇのＡｇの表面にＡｕを蒸着しＮｉ
−Ａｇ −Ａｕの三層構造を得る。ＡｕをＡｇの表面
に蒸着する際の熱でＡｕの粒子がＡｇ と反応し良好な
密着が得られる。この様にして得られたシリコンチップ
の裏面電極は次工程でチップを固着する時、ソフトソル
ダーとのなじみが良好となる。Furthermore, due to the heat treatment of the sinter, the Ni and the gradient diffuse into each other at the interface, increasing the adhesion strength υ and obtaining good ohmic properties. After that, Au was vapor-deposited on the Ag surface of the Ni-Ag to improve solder wettability when the chip was fixed.
A three-layer structure of -Ag-Au is obtained. The heat generated when Au is deposited on the Ag surface causes the Au particles to react with the Ag, resulting in good adhesion. The back electrode of the silicon chip obtained in this manner has good compatibility with the soft solder when the chip is fixed in the next step.
欠に本発明について、第１図から第２図を参照して説明
する。第２図は、従来のシリコンチップ裏面の電極構造
断面図である。シリコンウェハ１の裏面に蒸着又はメッ
キによシＮｉ を付着し、比較的高温で、シンターを
行い、Ｎｉ クリサイド層２を形成し、コレクタ一層
のオーミック接触を得る。次に余分なＮｉ の酸化物を
硝酸等でエツチングし、Ｎｉ シリサイド層の表面を
露出させる。しかる後に再度Ｎｉ、３を蒸着又はメッキ
により約５００ＯＡ付着する。更に半田とのなじみを良
好ならしめるためにＡｕ 、 ５を蒸着又はメッキによ
り付着し、しかる後に、ダイシングを行ない、シリコン
素子のチップ６を得ていた。The present invention will be briefly described with reference to FIGS. 1 and 2. FIG. 2 is a cross-sectional view of the electrode structure on the back surface of a conventional silicon chip. Ni is deposited on the back surface of the silicon wafer 1 by vapor deposition or plating, and sintered at a relatively high temperature to form a Ni crystallization layer 2 to obtain ohmic contact with the collector layer. Next, excess Ni oxide is etched with nitric acid or the like to expose the surface of the Ni silicide layer. Thereafter, about 500 OA of Ni is deposited again by vapor deposition or plating. Further, in order to improve the compatibility with solder, Au, 5 was attached by vapor deposition or plating, and then dicing was performed to obtain a silicon element chip 6.
第１図は、本発明によるシリコン素子チップ裏面の電極
構造断面図である。シリコンウェハ１の裏面に蒸着法に
より、Ｎｉ及び々の２層を同−真空系にて付着する。こ
の場合、Ｎｉ、３は約５０００工程中でＮｉ 表面の酸
化は防止可能である。次にＮｉ−Ａｇが蒸着されたウェ
ハは一旦蒸着装置より取出し、不活性ガス雰囲気例えば
Ｎ、、Ａｒ中で比較的高温４５０℃〜５００°Ｃの温度
でシンター処理を行ないニッケルシリサイド層２ｔ−生
成することにより良好なオーミック接触を得る。しかる
後にソフトソルダーとのぬれ性を良くするため更にＡｕ
、５ｔ−約３００ＯＡの厚さを蒸着する。この場合Ａｕ
の粒子が蒸着される際％ Ａｇと反応し、良好な密着が
得られるため新らためて熱処理を行う必要はない。最後
にダイシングを行ない、シリコン素子のチップ６を得る
。FIG. 1 is a sectional view of the electrode structure on the back surface of a silicon element chip according to the present invention. Two layers of Ni and the like are deposited on the back surface of the silicon wafer 1 by vapor deposition in the same vacuum system. In this case, Ni,3 can prevent oxidation of the Ni surface during about 5000 steps. Next, the wafer on which Ni-Ag has been vapor-deposited is temporarily taken out from the vapor deposition apparatus, and sintered at a relatively high temperature of 450°C to 500°C in an inert gas atmosphere, such as N or Ar, to form a nickel silicide layer 2T. By doing so, good ohmic contact can be obtained. After that, further Au was added to improve the wettability with the soft solder.
, 5t - deposit a thickness of about 300OA. In this case Au
When the particles are vapor-deposited, they react with %Ag and good adhesion is obtained, so there is no need for a new heat treatment. Finally, dicing is performed to obtain silicon element chips 6.
以上説明した様に、本発明はシリコン素子チップの裏面
の電極構をＮｉ −Ａｇ −Ａｕの３層構造にすること
により、次工程であ゛るチップ固着工程に於けるソフト
ソルダーとのなじみ及びぬれ性の良好な安定したプロセ
スが確立出来、これを応用した半導体装置に於ては電気
的特性、信頼度、及び歩留等が飛躍的に改善されその効
果は非常に大きい。As explained above, the present invention makes the electrode structure on the back side of the silicon element chip a three-layer structure of Ni-Ag-Au, thereby improving compatibility with the soft solder in the next chip fixing process. A stable process with good wettability can be established, and the electrical characteristics, reliability, yield, etc. of semiconductor devices using this process are dramatically improved, and the effects are very large.
第１図は、本発明のシリコンチップの裏面電極構造の断
面図、第２図は従来のシリコンチツプの裏面電極構造の
断面図である。
１・・・・・・シリコンチップ、２・・・・・・ニッケ
ルシリサイド層、３・・・・・・Ｎｉ層、４・・・・−
・Ａｇ層、５・・・・・・Ａｕ層、６・・・・・・シリ
コン素子チップ。FIG. 1 is a sectional view of the back electrode structure of a silicon chip according to the present invention, and FIG. 2 is a sectional view of the back electrode structure of a conventional silicon chip. 1...Silicon chip, 2...Nickel silicide layer, 3...Ni layer, 4...-
・Ag layer, 5...Au layer, 6...Silicon element chip.
Claims (1)
層構造で構成したことを特徴とするシリコン半導体装置
。A silicon semiconductor device characterized in that a back electrode structure of a silicon chip is formed of a three-layer structure of Ni-Ag-Au.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61130809A JPH0693466B2 (en) | 1986-06-04 | 1986-06-04 | Silicon semiconductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61130809A JPH0693466B2 (en) | 1986-06-04 | 1986-06-04 | Silicon semiconductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62286236A true JPS62286236A (en) | 1987-12-12 |
| JPH0693466B2 JPH0693466B2 (en) | 1994-11-16 |
Family
ID=15043212
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61130809A Expired - Lifetime JPH0693466B2 (en) | 1986-06-04 | 1986-06-04 | Silicon semiconductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0693466B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04211137A (en) * | 1990-01-10 | 1992-08-03 | Hughes Aircraft Co | Structure and method for solder die bonding of integrated circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5287360A (en) * | 1976-01-16 | 1977-07-21 | Nec Home Electronics Ltd | Semiconductor device |
| JPS5614233A (en) * | 1979-07-17 | 1981-02-12 | Ricoh Co Ltd | Photosensitive heat-sensitive type recording member |
| JPS58164232A (en) * | 1982-03-24 | 1983-09-29 | Toshiba Corp | Semiconductor device |
-
1986
- 1986-06-04 JP JP61130809A patent/JPH0693466B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5287360A (en) * | 1976-01-16 | 1977-07-21 | Nec Home Electronics Ltd | Semiconductor device |
| JPS5614233A (en) * | 1979-07-17 | 1981-02-12 | Ricoh Co Ltd | Photosensitive heat-sensitive type recording member |
| JPS58164232A (en) * | 1982-03-24 | 1983-09-29 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04211137A (en) * | 1990-01-10 | 1992-08-03 | Hughes Aircraft Co | Structure and method for solder die bonding of integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0693466B2 (en) | 1994-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3144328B2 (en) | Thermoelectric conversion element and method of manufacturing the same | |
| US3200490A (en) | Method of forming ohmic bonds to a germanium-coated silicon body with eutectic alloyforming materials | |
| JPH04326534A (en) | Chip bonding method of semiconductor device | |
| CN105009295A (en) | Semiconductor device and manufacturing method for semiconductor device | |
| US6191485B1 (en) | Semiconductor device | |
| JPS62286236A (en) | Silican semiconductor device | |
| JP3407839B2 (en) | Method of forming solder bump for semiconductor device | |
| JPS61220344A (en) | Manufacture of semiconductor device | |
| JPS5916353A (en) | Lead frame | |
| US3702787A (en) | Method of forming ohmic contact for semiconducting devices | |
| JPS63161631A (en) | Silicon semiconductor element | |
| JPH0472764A (en) | Rear electrode of semiconductor device | |
| JPH03209725A (en) | Method for forming bump of semiconductor device | |
| JPS592175B2 (en) | semiconductor equipment | |
| JPS59189625A (en) | Manufacture of semiconductor device | |
| JPH0793329B2 (en) | How to fix semiconductor pellets | |
| JP4055399B2 (en) | Chip-type semiconductor device and manufacturing method thereof | |
| JPS6057219B2 (en) | semiconductor equipment | |
| JPH038346A (en) | Brazing material | |
| JP4104506B2 (en) | Manufacturing method of semiconductor device | |
| JPS6220338A (en) | Manufacture of semiconductor device | |
| JPS5917860B2 (en) | Manufacturing method of semiconductor device | |
| JPH1197618A (en) | Bonding of silicon wafer | |
| JPS6353693B2 (en) | ||
| JPS6057221B2 (en) | semiconductor equipment |