JPS6353693B2 - - Google Patents

Info

Publication number
JPS6353693B2
JPS6353693B2 JP53149850A JP14985078A JPS6353693B2 JP S6353693 B2 JPS6353693 B2 JP S6353693B2 JP 53149850 A JP53149850 A JP 53149850A JP 14985078 A JP14985078 A JP 14985078A JP S6353693 B2 JPS6353693 B2 JP S6353693B2
Authority
JP
Japan
Prior art keywords
thin film
nickel
vanadium
semiconductor device
solder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53149850A
Other languages
Japanese (ja)
Other versions
JPS5575226A (en
Inventor
Susumu Watanabe
Shusuke Kotake
Eiji Jimi
Fumio Tanabe
Tetsuo Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP14985078A priority Critical patent/JPS5575226A/en
Publication of JPS5575226A publication Critical patent/JPS5575226A/en
Publication of JPS6353693B2 publication Critical patent/JPS6353693B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は半導体装置の製造方法に関し、詳しく
は放熱用金属基板で半導体素子を固定した構造の
半導体装置の製造方法の改良に係る。 周知の如く、この種の半導体装置はシリコン単
結晶製の半導体素片(ペレツト)及びこのペレツ
トに接続した導線からなる半導体素子をヒートシ
ンクと称する放熱用金属基板に固定し、かつこれ
らを支持基板に組み立てた構造になつている。 ところで、上述した構造の半導体装置は従来、
次のような方法により製造されている。まず、半
導体素子のシリコンペレツトにニツケル薄膜を形
成した後、500〜550℃程度の温度で約30分間シン
ター処理を施し、シリコンペレツトとニツケル薄
膜を反応させてニツケルシリサイド金属間化合物
層を生成させる。次いで、このシリコンペレツト
と放熱用金属基板とを500℃以下の強度ではんだ
接合して半導体装置を製造する。 しかしながら、上記従来法にあつてはシンター
処理に際してニツケル薄膜表面の酸化等が避け難
く、ニツケル薄膜とはんだとのぬれ不良に伴なう
半導体装置の不良化が起こる。また、シンター処
理は本質的にニツケル薄膜とシリコンペレツトを
反応させる熱処理であるため、シンター処理条件
を充分に管理するか、ニツケル薄膜の厚さを十分
厚くするかしないと、ニツケル薄膜は全てニツケ
ルシリサイド金属間化合物となり、その結果、は
んだとの接合が困難になつたり、強度低下を招い
たりする。したがつて、従来法では、シンター処
理後に表面が酸化され、かつニツケルシリサイド
に変換された薄膜を硝酸等で浄化し、再度ニツケ
ル薄膜を形成しなければならず、作業工程が増大
化すると共に煩雑化し、半導体装置の生産性に支
障をきたす欠点がある。 更に、シリコン基板上にニツケル層を形成する
際に、間に金属を介在させることを知られている
(特公昭50―27990号公報)。しかしながら、金は
常温程度でもシリコンと反応し金シリサイドとし
てシリコン中に拡散してしまうために、ニツケル
シリサイドの生成を効果的に阻止することができ
ず、はんだとの接合が困難であるという前記従来
法の欠点は依然として改善されてない。 そこで、本発明者はシリコンペレツトとニツケ
ル薄膜との間にバナジウム薄膜を介在させて、ニ
ツケルシリサイド金属間化合物の生成温度につい
て、X線分析とイオンマイクロアナライザーによ
る分析によつて検討したところ、下記表に示すご
とく、380℃以下の熱処理温度ではニツケルシリ
サイド金属化合物が生成せず、バナジウム薄膜に
よるシリサイド生成の障壁作用により更に実質上
ニツケルシリサイド生成温度が高められることが
わかつた。
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to an improvement in a method for manufacturing a semiconductor device having a structure in which a semiconductor element is fixed to a heat dissipating metal substrate. As is well known, in this type of semiconductor device, a semiconductor element consisting of a silicon single crystal semiconductor piece (pellet) and a conductive wire connected to this pellet is fixed to a heat dissipating metal substrate called a heat sink, and these are attached to a support substrate. It has an assembled structure. By the way, the semiconductor device with the above-mentioned structure has conventionally
It is manufactured by the following method. First, a nickel thin film is formed on the silicon pellet of the semiconductor device, and then sintered at a temperature of about 500 to 550°C for about 30 minutes to cause the silicon pellet and nickel thin film to react to form a nickel silicide intermetallic compound layer. let Next, the silicon pellets and the heat dissipating metal substrate are soldered together with a strength of 500° C. or less to manufacture a semiconductor device. However, in the above conventional method, it is difficult to avoid oxidation of the surface of the nickel thin film during the sintering process, resulting in defective semiconductor devices due to poor wetting between the nickel thin film and the solder. Additionally, since sintering is essentially a heat treatment that causes the nickel thin film to react with silicon pellets, unless the sintering conditions are well controlled or the nickel thin film is made sufficiently thick, the nickel thin film will turn into nickel. It becomes a silicide intermetallic compound, and as a result, it becomes difficult to join with solder and strength decreases. Therefore, in the conventional method, the surface is oxidized after sintering, and the thin film converted to nickel silicide must be cleaned with nitric acid, etc., and a nickel thin film must be formed again, which increases the number of work steps and is complicated. This has the disadvantage that it hinders the productivity of semiconductor devices. Furthermore, it is known that when a nickel layer is formed on a silicon substrate, a metal is interposed therebetween (Japanese Patent Publication No. 50-27990). However, since gold reacts with silicon even at room temperature and diffuses into the silicon as gold silicide, the formation of nickel silicide cannot be effectively prevented, making it difficult to bond with solder. The shortcomings of the law have not yet been improved. Therefore, the present inventor interposed a vanadium thin film between the silicon pellet and the nickel thin film, and examined the formation temperature of the nickel silicide intermetallic compound by X-ray analysis and analysis using an ion microanalyzer. As shown in the table, it was found that the nickel silicide metal compound was not formed at a heat treatment temperature of 380°C or lower, and the nickel silicide formation temperature was further substantially raised by the vanadium thin film's barrier effect on silicide formation.

【表】【table】

【表】 但し、表中の○はシリサイド生成
×はシリサイドが生成しない
ことを意味する。
しかして、本発明者は上記知見に基づき、鋭意
研究を重ねた結果、半導体素子のシリコンペレツ
トにバナジウム薄膜を介してニツケル薄膜を形成
し、380℃以下の熱処理にて放熱用金属基板とは
んだ接合せしめることによつて、ニツケル薄膜が
シリサイド化されず十分なはんだぬれ性と強度を
有し、煩雑な浄化処理、再度のニツケル薄膜形成
を行なわずに良好なはんだ接合を遂行でき、十分
な接合強度を保有する半導体装置を生産性よく製
造し得る方法を見い出した。さらにはんだ接合時
の熱処理温度を更に高めることができ、使用され
るはんだの種類の拡大化、ひいてははんだ信頼性
の向上化を図ることができ、しかもはんだ作業の
迅速化を達成できる半導体装置の製造方法を見い
出した。 すなわち、本願発明は半導体素子にバナジウム
薄膜を被覆し、さらのこの薄膜上にニツケル薄膜
を形成した後、この半導体素子を放熱用金属基板
に該素子のニツケル薄膜側が該基板と対向するよ
うに配置し、これら素子と基板を380℃以下の熱
処理にてはんだ接合しめることを特徴とするもの
である。 本願発明におけるニツケル薄膜の形成手段とし
ては、メツキによりニツケルメツキ薄膜を形成す
る方法、或いはスパツタ、蒸着によりニツケル薄
膜を被着する方法等が採用し得る。とくに、スパ
ツタにより形成されたニツケル薄膜は緻密性に富
み、機械的強度が優れているため有益である。 本願発明におけるニツケル薄膜の厚さは十分な
熱伝導性、機械的特性を付与する観点から、2500
(0.25μt)〜30000(3μt)Åの範囲にすることが望
ましい。 また、本願発明におけるバナジウム薄膜の形成
手段としては、スパツタ蒸着によりバナジウム薄
膜を被着する方法等を挙げることができる。とく
に、スパツタにより形成されたバナジウム薄膜は
緻密性に富み、ニツケルシリサイド生成の障壁作
用が高いため、該薄膜の厚さに規制されず、シリ
サイド生成温度を400℃まで高める効果を有する。 本願発明におけるバナジウム薄膜の厚さは、
100Å以上あれば十分ニツケルシリサイド生成の
障壁作用が発現されるが、とくにその厚さを250
Å以上にすればシリサイド生成温度を380℃から
400℃に高めることができ、さらに使用されるは
んだの種類の拡大化、はんだ作業の迅速化を図る
ことができる。 次に本発明の実施例を説明する。 実施例 1 半導体素子のシリコンペレツト裏面にバナジウ
ムを真空蒸着して厚さ500Åのバナジウム薄膜を
被覆した後、この薄膜上にニツケルを真空蒸着し
て厚さ4000Åのニツケル薄膜を形成した。次い
で、上記素子のシリコンペレツト裏面を銅製の放
熱用金属基板に95Pb―3Sn―2Agのプリフオーム
はんだを介して載せた後、350℃の温度下にて1
分間熱処理してはんだ接合し、半導体装置を造つ
た。 得られた半導体装置はニツケルシリサイド層が
生成されず、良好なはんだ接合がなされ、しかも
熱疲労試験の結果も良好な特性を有することが確
認された。 実施例 2 半導体素子のシリコンペレツトにバナジウムを
真空蒸着して厚さ300Åのバナジウム薄膜を被覆
し、さらにこの上にニツケルを真空蒸着して厚さ
6000Åのニツケル薄膜を形成した。次いで、上記
半導体素子のシリコンペレツト裏面を銅製の放熱
用金属基板に95Pb―5Sb―のプリフオームはんだ
を介して載せた後、300℃で2分間熱処理しては
んだ接合し、半導体装置を造つた。 得られた半導体装置はニツケルシリサイド層が
生成されず、良好なはんだ接合がなされ、しかも
熱疲労試験の結果も良好であることが確認され
た。 以上詳述した如く、本発明によれば、ニツケル
薄膜がシリサイド化されず充分なはんだぬれ性と
強度を有し、煩雑な浄化処理、再度のニツケル薄
膜形成を行なわずに良好なはんだ接合を遂行で
き、十分な接合強度を有する半導体装置を生産性
よく製造できる等顕著な効果を有する。また、本
願発明によればはんだ接合時の熱処理温度を更に
高めることができ、もつて使用されるはんだの種
類の拡大化、ひいてははんだ信頼性の向上化を図
ることができ、しかもはんだ作業の迅速化を達成
できる半導体装置の製造方法を提供できるもので
ある。
[Table] However, ○ in the table indicates silicide formation.
× means that silicide is not generated.
Based on the above findings, the inventors of the present invention have conducted extensive research, and as a result, formed a nickel thin film on the silicon pellet of a semiconductor element via a vanadium thin film, and soldered it to a heat dissipating metal substrate by heat treatment at 380°C or less. By bonding, the nickel thin film is not silicided and has sufficient solderability and strength, and a good solder joint can be achieved without complicated purification treatment or re-formation of the nickel thin film, resulting in a sufficient bond. We have discovered a method for manufacturing semiconductor devices with high productivity with high strength. Furthermore, it is possible to manufacture semiconductor devices that can further increase the heat treatment temperature during soldering, expand the types of solder that can be used, improve solder reliability, and speed up the soldering process. I found a way. That is, the present invention coats a semiconductor element with a vanadium thin film, further forms a nickel thin film on this thin film, and then arranges this semiconductor element on a heat dissipation metal substrate such that the nickel thin film side of the element faces the substrate. However, the device is characterized in that these elements and the substrate are soldered together by heat treatment at 380°C or less. As a means for forming a nickel thin film in the present invention, a method of forming a nickel plating thin film by plating, a method of depositing a nickel thin film by sputtering or vapor deposition, etc. can be adopted. In particular, a nickel thin film formed by sputtering is advantageous because it is highly dense and has excellent mechanical strength. The thickness of the nickel thin film in the present invention is 2500 mm from the viewpoint of providing sufficient thermal conductivity and mechanical properties.
(0.25 μt) to 30000 (3 μt) Å is desirable. Further, as a means for forming a vanadium thin film in the present invention, a method of depositing a vanadium thin film by sputter deposition, etc. can be mentioned. In particular, the vanadium thin film formed by sputtering is highly dense and has a high barrier effect for nickel silicide formation, so it is not limited by the thickness of the thin film and has the effect of increasing the silicide formation temperature to 400°C. The thickness of the vanadium thin film in the present invention is
A thickness of 100 Å or more is sufficient to provide a barrier effect for the formation of nickel silicide, but especially if the thickness is 250 Å or more,
If the temperature is Å or more, the silicide formation temperature can be reduced from 380°C.
It is possible to increase the temperature to 400℃, expand the types of solder that can be used, and speed up the soldering process. Next, examples of the present invention will be described. Example 1 Vanadium was vacuum-deposited on the back side of a silicon pellet of a semiconductor device to cover a vanadium thin film with a thickness of 500 Å, and then nickel was vacuum-deposited on this thin film to form a nickel thin film with a thickness of 4000 Å. Next, the back side of the silicon pellet of the above device was placed on a heat-dissipating metal substrate made of copper via a 95Pb-3Sn-2Ag preform solder, and then heated at 350℃ for 1 hour.
After heat treatment for a minute and solder bonding, a semiconductor device was fabricated. It was confirmed that the obtained semiconductor device did not produce a nickel silicide layer, had good solder joints, and had good characteristics in thermal fatigue test results. Example 2 Vanadium was vacuum-deposited onto a silicon pellet of a semiconductor device to cover it with a vanadium thin film with a thickness of 300 Å, and nickel was further vacuum-deposited on top of this to form a thin vanadium film with a thickness of 300 Å.
A nickel thin film of 6000 Å was formed. Next, the back side of the silicon pellet of the semiconductor element was placed on a heat-dissipating metal substrate made of copper via 95Pb-5Sb- preform solder, and then heat treated at 300°C for 2 minutes and soldered together to produce a semiconductor device. It was confirmed that in the obtained semiconductor device, no nickel silicide layer was formed, good solder bonding was achieved, and the results of the thermal fatigue test were also good. As detailed above, according to the present invention, the nickel thin film is not silicided and has sufficient solderability and strength, and good solder joints can be achieved without complicated purification treatment or re-formation of the nickel thin film. This has remarkable effects such as making it possible to manufacture semiconductor devices with sufficient bonding strength with high productivity. Furthermore, according to the present invention, it is possible to further increase the heat treatment temperature during solder bonding, expand the types of solder that can be used, improve solder reliability, and speed up the soldering process. Accordingly, it is possible to provide a method for manufacturing a semiconductor device that can achieve the following.

Claims (1)

【特許請求の範囲】 1 半導体素子にバナジウム薄膜を被覆し、さら
にこの薄膜上にニツケル薄膜を形成した後、この
半導体素子を放熱用金属基板に該素子のニツケル
薄膜側が該基板と対向するように配置し、これら
素子と基板を380℃以下の熱処理にてはんだ接合
せしめることを特徴とする半導体装置の製造方
法。 2 バナジウム薄膜の厚さが250Å以上であるこ
とを特徴とする特許請求の範囲第1項記載の半導
体装置の製造方法。
[Claims] 1. After coating a semiconductor element with a vanadium thin film and further forming a nickel thin film on this thin film, the semiconductor element is placed on a heat dissipating metal substrate such that the nickel thin film side of the element faces the substrate. 1. A method for manufacturing a semiconductor device, which comprises arranging these elements and soldering them to a substrate by heat treatment at 380°C or less. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the vanadium thin film has a thickness of 250 Å or more.
JP14985078A 1978-12-04 1978-12-04 Manufacturing semiconductor device Granted JPS5575226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14985078A JPS5575226A (en) 1978-12-04 1978-12-04 Manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14985078A JPS5575226A (en) 1978-12-04 1978-12-04 Manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS5575226A JPS5575226A (en) 1980-06-06
JPS6353693B2 true JPS6353693B2 (en) 1988-10-25

Family

ID=15484008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14985078A Granted JPS5575226A (en) 1978-12-04 1978-12-04 Manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5575226A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59198727A (en) * 1983-04-26 1984-11-10 Nec Home Electronics Ltd Manufacture of semiconductor device
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027990A (en) * 1973-07-13 1975-03-22

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5027990A (en) * 1973-07-13 1975-03-22

Also Published As

Publication number Publication date
JPS5575226A (en) 1980-06-06

Similar Documents

Publication Publication Date Title
JPH06196349A (en) Copper lead frame material for tantalum capacitor and manufacture thereof
JPH04329891A (en) Tin plated copper alloy material and its production
US3209450A (en) Method of fabricating semiconductor contacts
JPH0133278B2 (en)
US6191485B1 (en) Semiconductor device
JPS6353693B2 (en)
JPH03179793A (en) Surface structure of ceramic board and manufacture thereof
JPS6040185B2 (en) Method for manufacturing a solderable metal layer with high lateral conductivity on a substrate
JPS63204620A (en) Method of forming connection between bonding wire and contact region in hybrid thick film circuit
JPH0472764A (en) Rear electrode of semiconductor device
US3577275A (en) Semi-conductor crystal supports
JPH038346A (en) Brazing material
JP4055399B2 (en) Chip-type semiconductor device and manufacturing method thereof
JPS58509B2 (en) Metsukihouhou
JPH0783172B2 (en) Wiring board
JPS6125471B2 (en)
JPS60195953A (en) Semiconductor device and manufacture thereof
JPS6041860B2 (en) Manufacturing method for airtight terminals
JPS60107845A (en) Circuit substrate for semiconductor
JPH0693466B2 (en) Silicon semiconductor device manufacturing method
JPH0222831A (en) Thermal-expansion adjusting material for high-temperature use
JPS5821430B2 (en) Manufacturing method of semiconductor device
JPS60143636A (en) Electronic component parts
JPS61225839A (en) Forming method for bump electrode
JPS6010674A (en) Manufacture of semiconductor element