JPS61121435A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61121435A JPS61121435A JP24401684A JP24401684A JPS61121435A JP S61121435 A JPS61121435 A JP S61121435A JP 24401684 A JP24401684 A JP 24401684A JP 24401684 A JP24401684 A JP 24401684A JP S61121435 A JPS61121435 A JP S61121435A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- angstrom
- evaporated
- wafer
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 8
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000005245 sintering Methods 0.000 abstract description 3
- 229910015365 Au—Si Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 15
- 239000010931 gold Substances 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 10
- 239000000758 substrate Substances 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 239000010408 film Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 230000008020 evaporation Effects 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置の製造方法、特に電極と半導体との
オーミノク工程に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a semiconductor device, particularly to an ohminok process between an electrode and a semiconductor.
（従来の技術）
従来、電極形成は主として拡散層上にＮｉメッキ、Ａｆ
ｉ蒸着、Ａｕ蒸着、更にはＮｉ、Ｎｉ−Ａｇ蒸着などを
行い熱処理を行ってオーム接触を形成と、このチップを
ハンダ付けや、ボンディングを行うことによシ外部リー
ドと接続し、市販されている半導体装置としている。(Prior art) Conventionally, electrode formation was mainly done by Ni plating or Af plating on the diffusion layer.
After applying I vapor deposition, Au vapor deposition, Ni and Ni-Ag vapor deposition, and heat treatment to form an ohmic contact, this chip is connected to external leads by soldering and bonding, and is commercially available. It is considered a semiconductor device.
この電極の系として要求される性質は、金属自体の抵抗
が小さいこと、シリコンとオーム接触をしていること、
出来たＡＵ−シリコンの系が種々の熱処理（シンター、
組立の工程）に対し安定であること、動作試験や環境試
験などの信頼性試験に対し安定なこと、更にはＡｕ、Ａ
ｕ線等のボンディング線、又はＡｕＳｉ、Ａｇ８ｎ、８
ｂＳｎ等（７） ハフ タトの結合状態が良好であるこ
となどである。The properties required for this electrode system are that the resistance of the metal itself is low, that it is in ohmic contact with silicon,
The resulting AU-silicon system undergoes various heat treatments (sintering,
It must be stable against reliability tests such as operation tests and environmental tests.
Bonding wire such as U line, or AuSi, Ag8n, 8
bSn, etc. (7) The bonding state of Haftato is good.
一般に、オーム接触は半導体表面の不純物濃度が高い場
合（ＩＱ”／Ｃｍ’以上）には問題とならない。Generally, ohmic contact does not become a problem when the impurity concentration on the semiconductor surface is high (IQ''/Cm' or higher).
それ故、高濃度の拡散層に蒸着した金属とシリコンとの
オーム接触はほとんど問題なく形成することが出来、蒸
着の金属の種類としても選択の自由度は太きい。Therefore, ohmic contact between the metal deposited in the high-concentration diffusion layer and silicon can be formed with almost no problems, and there is a wide degree of freedom in selecting the type of metal to be deposited.
しかし、拡散工程の省略化やウェハーの大口径化に伴い
、拡散工程でのウェハー歩留を向上させるためにはウェ
ハー厚が厚い状態で拡散工程を行ない、衆徒にウェハー
全うすく研磨し裏面にオーム接触をとることが可能にな
れば工程の省略化及び歩留の向上となる。しかし、従来
使われている金属でそのままオーム接触をとるのは基板
の不純物濃度が少い場合はむずかしく何らかの方法で、
シリコン表面の不純物濃度を上げることが必要となって
くる。このための一方法としてＡｕがシリコンと低い温
度で共晶を作ることを利用してＡｕＯ中に例えばＳｂの
ような不純物を含ませておき、熱処理することにより、
シリコン中に不純物を導入することがある。又組立時に
ハンダとのなじみを良くするためにＡｇを又、ソルダー
のストッパーとしてＮｉを蒸着したシ、又、ＡｕＯ上Ｋ
Ｎｉのみの単層蒸着を行ったシすると、一応低濃度不純
物基板にオーム接触がとれ、組立工程でもソルダーとな
じみが良く安定な蒸着系となる。っｔ ’） ８ ｉ
−Ａｕ（Ｓｂ）−Ｎｉ−Ａｇといった蒸着系である。However, as the diffusion process is omitted and the diameter of wafers becomes larger, in order to improve the wafer yield in the diffusion process, it is necessary to perform the diffusion process on thick wafers, polish the entire wafer thinly, and polish the backside with ohms. If it becomes possible to make contact, the process will be omitted and the yield will be improved. However, it is difficult to make ohmic contact with conventional metals when the impurity concentration of the substrate is low.
It becomes necessary to increase the impurity concentration on the silicon surface. One method for this is to take advantage of the fact that Au forms a eutectic with silicon at low temperatures, and impurities such as Sb are included in AuO, and then heat treated.
Impurities may be introduced into silicon. In addition, Ag was deposited to improve solder compatibility during assembly, Ni was deposited as a solder stopper, and K was deposited on AuO.
If a single layer of Ni is deposited, ohmic contact can be established with the low concentration impurity substrate, and the deposition system will be stable and compatible with the solder during the assembly process. t') 8 i
-Au(Sb)-Ni-Ag.
（発明が解決しようとする問題点）
この系の問題点としては、Ａｕが８ｉと反応しＡｕ−Ｎ
ｉの界面まで８ｉが容易に到達し、又ＮｉはＳｉと低温
度でシリサイドを形成するためＮ１ｘＳｉｙの合金化の
反応も進み、又Ｎｉ中へのＡｕの拡散も起るなど積層膜
の形成時の熱処理条件によって変化をうけやすいため同
一の状態に管理することは非常に面倒なことになる。(Problem to be solved by the invention) The problem with this system is that Au reacts with 8i and Au-N
8i easily reaches the interface of i, and since Ni forms silicide with Si at low temperature, the alloying reaction of N1xSiy also progresses, and Au diffuses into Ni. It is very troublesome to maintain the same condition because it is easily subject to changes depending on the heat treatment conditions.
本発明の目的は信頼性の高いオーム性接触を容易に得る
方法を提供することにある。An object of the present invention is to provide a method for easily obtaining reliable ohmic contact.
（問題点を解決するための手段）
本発明によれば、ＡｕとＮｉの層間に、Ａｕ、Ｎｉのい
づれとも反応しに＜＜、又Ｓｉとも比較的反応のしにく
い金属を介在させることによシ、熱処理状況が多少変化
しても常に安定な金属電極系を提供するものである。具
体的にはＡ１層とＮｉ層の間にＴ Ｈ（チタン）層を介
在させることによシ、オーム性接触をとるための３ｉ−
Ａｕ（８ｂ）の系とソルダーとの接続に使うＮｉ又はＮ
ｉ−Ａｇ系を分離するものである。Ｔｉはシリサイドが
出来る温度が比較的高いこと及び膜形成を行う際、例え
ばＥ−ガン蒸着を行うという工程をとっても高融点金属
にもかかわらず、パワーや蒸着速度のコントロールなど
が容易で扱いやすい金属であるという生産工程上のメリ
ットもある。(Means for Solving the Problems) According to the present invention, a metal that does not react with either Au or Ni and is relatively difficult to react with Si is interposed between the Au and Ni layers. This provides a metal electrode system that is always stable even if the heat treatment conditions change somewhat. Specifically, by interposing a TH (titanium) layer between the A1 layer and the Ni layer, 3i-
Ni or N used to connect Au (8b) system and solder
This separates the i-Ag system. Although Ti is a metal with a relatively high melting point because the temperature at which silicide can be formed is relatively high, and when forming a film, for example, using E-gun evaporation, it is an easy-to-handle metal with easy control of power and evaporation rate. There is also an advantage in terms of the production process.
（実施例） 次に本発明を実施例に基づきょシ詳細に説明する。(Example) Next, the present invention will be explained in detail based on examples.
第１回はトランジスターの断面図である。大口径の例え
ば４インチウェハーを用いて拡散を行う事を想定する。The first part is a cross-sectional view of a transistor. It is assumed that diffusion is performed using a large diameter wafer, for example, 4 inches.
ウェハーの歩留安定化のためには例えば３５０〜５００
μ程度の厚いウェハーを使用することを考える。ＮＴシ
リコン基板（１）上には気相成長させたＮ″″型領域（
２）を有している。このウェハーにＰ型のベース拡散領
域（３）の拡散及びＮ型のエミッター拡散領域を形成す
る。拡散終了後、表面の電極を形成するため、エミッタ
ー及びベース領域ｆ４）、 （３）のＳｉＯ宜膜１２を
選択除去した後、へ〇蒸着を行い、エミッター電極６及
びベース電極５を形成する。しかるのち、このウェハー
の裏面を研磨して、例えば２００〜２５０μ程度の所望
の厚さにする。For example, 350 to 500 to stabilize wafer yield.
Consider using a wafer as thick as μ. On the NT silicon substrate (1) there is an N″″ type region (
2). A P-type base diffusion region (3) and an N-type emitter diffusion region are formed on this wafer. After completion of the diffusion, in order to form electrodes on the surface, the emitter and base regions f4) and (3) of the SiO film 12 are selectively removed, and then evaporation is performed to form the emitter electrode 6 and the base electrode 5. Thereafter, the back side of this wafer is polished to a desired thickness of, for example, about 200 to 250 microns.
次にこの面に、例えばｓｂ″ｅｏ、１〜１ｗｔ％含有し
たＡｕ層８を５００〜ｚｏｏｏ４度蒸着する。次ｌｃ
Ｔ １（２）を例えば５００〜３ｏｏｏＡ程度蒸着した
のち、この上に連続的にＮ１Ｑｌ及びＡｇ（ＩＩＪを２
０００Ａ〜階程度蒸着する。次にこのウェハーを３００
〜５００℃程度の温度で数分〜１時時間区不活性ガス又
はＨａガスを用いて熱処理を行う。Next, on this surface, for example, an Au layer 8 containing 1 to 1 wt% of sb″eo is vapor-deposited 4 times at 500 to 100% by weight.Next lc
After depositing T1(2), for example, about 500 to 3oooA, N1Ql and Ag (IIJ) are continuously deposited on top of this.
Deposit from 000A onwards. Next, 300 pieces of this wafer
Heat treatment is performed at a temperature of about 500° C. for several minutes to 1 hour using an inert gas or Ha gas.
これによってコレクタ電極１３が形成される。この時ｓ
ｂを含有するＡｕ１ｊ、８ｉと合金化し冷却時に再結晶
化する再、あるいは低温の場合はシンタ一工程で８ｉの
結晶位置にｓｂが導入されることＫよシ高不純物濃度層
が形成され、Ａｕ −８ｉ （Ｓｂ ）の合金化層８が
形成される。その後、個々のチップに分割する。この方
法に於いて、Ａｕ（８ｈ）の合金は蒸着だけでなくスパ
ッター等の方法でつけて吃よい。又人Ｕ中の不純物とし
てはｓｂだけでなく、Ｐ、Ａｓ、Ａｆｉといったものも
基板の種類に応じて選択可能である。本発明の実施例は
Ｓｉ上に人Ｕを主体とする層を直接つけたが、量産時の
ラインの安定性（ハガレの発生）からは、自然酸化膜と
密着性のよいＴｉ、Ｃ，Ｖの薄膜（３００Å以下）をつ
けることも充分有効である。又、この蒸着系によるコレ
クタ電極ｊ３は高濃度のシリコン面に対しても問題なく
適用可能である。又それぞれの金属の膜厚、Ａｕ中の不
純物濃度は、実施例に示したのは一例でありて、その範
囲を逸脱しても問題はない。This forms the collector electrode 13. At this time s
sb is alloyed with Au1j and 8i containing b and recrystallized during cooling, or in the case of low temperature, sb is introduced into the crystal position of 8i in one step of sintering, and a high impurity concentration layer is formed. An alloyed layer 8 of -8i (Sb) is formed. Then split into individual chips. In this method, the Au (8h) alloy can be applied not only by vapor deposition but also by sputtering or the like. Moreover, as impurities in the human U, not only sb but also P, As, Afi, etc. can be selected depending on the type of substrate. In the embodiment of the present invention, a layer mainly composed of human U was directly applied on Si, but from the viewpoint of line stability during mass production (occurrence of peeling), Ti, C, and V, which have good adhesion to the natural oxide film, It is also sufficiently effective to apply a thin film (300 Å or less). In addition, the collector electrode j3 formed by this vapor deposition system can be applied to a highly-concentrated silicon surface without any problem. Furthermore, the film thicknesses of the respective metals and the impurity concentrations in Au are shown in the examples for illustrative purposes only, and there is no problem even if they deviate from these ranges.
本発明はトランジスターだけでなくダイオード、サイリ
スター、バリーＭＯ８ＦＥＴ等への適用はもち論可能で
あシ、従来のオーム接触形成のためだけの高濃度拡散は
不要となる。The present invention can of course be applied not only to transistors but also to diodes, thyristors, Barry MO8FETs, etc., and the conventional high-concentration diffusion only for forming ohmic contacts becomes unnecessary.
（発明の効果）
以上のとおシ、本発明によれば低濃度半導体に対して高
信頼性のオーミック接触を得ることができる。(Effects of the Invention) As described above, according to the present invention, highly reliable ohmic contact can be obtained with a low concentration semiconductor.
第１図は本発明の一実施例によるトランジスターの縦断
面である。
ｌ・・・・・・シリコン基板、２・・・・・・エピタキ
シャル層、３・・・・・・Ｐ型ベース領域、４・・・・
・・Ｎ型エミッター領域、５・・・・・・ベース電極、
６・・・・・・エミッター電極、１３・・・・・・コレ
クター電極、７・・・・・・Ａｕ−８ｉ（８ｂ）の合金
化領域、８・・・・・・ｓｂ金含有Ａｕ層、９・・・・
・・Ｔｉ層、１０・・・・・・Ｎｉ層、１１・・・・・
・Ａｇ層。
代理人 弁理士 内 原 晋ｆ４簸ニーｐ。
λ、 ・ ｌ
又 −FIG. 1 is a longitudinal section of a transistor according to an embodiment of the present invention. 1... Silicon substrate, 2... Epitaxial layer, 3... P-type base region, 4...
...N-type emitter region, 5...Base electrode,
6...Emitter electrode, 13...Collector electrode, 7...Au-8i (8b) alloyed region, 8...sb gold-containing Au layer , 9...
...Ti layer, 10...Ni layer, 11...
・Ag layer. Agent: Susumu Uchihara, patent attorney, f4-knee p. λ, ・l also −
Claims (1)
、Ａｕを主体とし不純物を 含有する層、Ｔｉ層及びＮｉ層を被着し、熱処理するこ
とを特徴とする半導体装置の製造方法。[Claims] A semiconductor device characterized in that a layer mainly composed of Au, a layer containing impurities, a Ti layer, and a Ni layer are deposited on a silicon semiconductor directly or via a metal thin film, and then heat-treated. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24401684A JPS61121435A (en) | 1984-11-19 | 1984-11-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24401684A JPS61121435A (en) | 1984-11-19 | 1984-11-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61121435A true JPS61121435A (en) | 1986-06-09 |
Family
ID=17112454
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24401684A Pending JPS61121435A (en) | 1984-11-19 | 1984-11-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61121435A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020102547A (en) * | 2018-12-21 | 2020-07-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
1984
- 1984-11-19 JP JP24401684A patent/JPS61121435A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020102547A (en) * | 2018-12-21 | 2020-07-02 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
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