JPS6217379B2 - - Google Patents
Info
- Publication number
- JPS6217379B2 JPS6217379B2 JP54165568A JP16556879A JPS6217379B2 JP S6217379 B2 JPS6217379 B2 JP S6217379B2 JP 54165568 A JP54165568 A JP 54165568A JP 16556879 A JP16556879 A JP 16556879A JP S6217379 B2 JPS6217379 B2 JP S6217379B2
- Authority
- JP
- Japan
- Prior art keywords
- gold
- layer
- silver
- silicon
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010931 gold Substances 0.000 claims description 30
- 229910052737 gold Inorganic materials 0.000 claims description 29
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 19
- 239000004332 silver Substances 0.000 claims description 19
- 229910052709 silver Inorganic materials 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
- 230000005496 eutectics Effects 0.000 claims description 9
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 229910001020 Au alloy Inorganic materials 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 28
- 239000011521 glass Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- PQTCMBYFWMFIGM-UHFFFAOYSA-N gold silver Chemical compound [Ag].[Au] PQTCMBYFWMFIGM-UHFFFAOYSA-N 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 150000002343 gold Chemical class 0.000 description 2
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01049—Indium [In]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01051—Antimony [Sb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は半導体素子およびその製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same.
ダブルヒートシンクダイオードはその製造にお
けるガラス封止時に650〜700℃もの高温になるこ
とから従来一般に用いているアルミニウム電極は
融点が低いこともあつて使用できない。このた
め、高温に強い金が使用される。 Double heat sink diodes are manufactured at temperatures as high as 650 to 700°C during glass sealing, and therefore the aluminum electrodes commonly used in the past cannot be used due to their low melting point. For this reason, gold, which is resistant to high temperatures, is used.
第１図はダブルヒートシンクダイオードの組立
に用いる半導体素子であり、Ｎ型のシリコン基板
１の主面中央の表層部にはＰ型導電領域２が形成
され、Ｐ型導電領域２の中央表面の電極取付部以
外のシリコン基板１の表面部は絶縁膜３が形成さ
れている。また、電極取付部（電極形成領域）に
は耐熱性の金層からなる電極４が形成されてい
る。また、この金層４の上面には銀層５が形成さ
れ、銀層５上には半球状の銀からなるバンプ電極
６が形成されている。なお、前記金層４にはシリ
コンとのオーミツク性を向上させるためにガリウ
ム（Ｎ型導電層に対してはアンチモン等）が含有
されている。一方、シリコン基板１の下面にはア
ンチモンを含む金層７が形成されるとともに、こ
の金層７の表面は銀層８で被われている。 FIG. 1 shows a semiconductor element used for assembling a double heat sink diode, in which a P-type conductive region 2 is formed in the surface layer at the center of the main surface of an N-type silicon substrate 1, and an electrode is formed on the center surface of the P-type conductive region 2. An insulating film 3 is formed on the surface portion of the silicon substrate 1 other than the mounting portion. Further, an electrode 4 made of a heat-resistant gold layer is formed in the electrode attachment portion (electrode formation area). Further, a silver layer 5 is formed on the upper surface of this gold layer 4, and a hemispherical bump electrode 6 made of silver is formed on the silver layer 5. The gold layer 4 contains gallium (eg, antimony for an N-type conductive layer) to improve ohmic properties with silicon. On the other hand, a gold layer 7 containing antimony is formed on the lower surface of the silicon substrate 1, and the surface of this gold layer 7 is covered with a silver layer 8.
このような半導体素子は１対のリードの端面間
に接続されるとともに、ガラス管で封止されてダ
ブルヒートシンクダイオード（DHD）となる。 Such a semiconductor element is connected between the end faces of a pair of leads and sealed with a glass tube to form a double heat sink diode (DHD).
ところで、このようなDHDにあつては特性の
劣化が生じることがある。この点について検討し
てみると、つぎのような事実が判明した。すなわ
ち、ガラス封止時に半導体素子は650℃〜700℃の
高温下に晒されるが、この際、相互に密着するシ
リコン基板と金層にあつては、金とシリコンの共
晶温度が370℃と低いことから、シリコン基板と
金層との界面では共晶化が進んで溶け、電極が劣
化してしまうことによつて電気特性が劣化する。 By the way, in such a DHD, deterioration of characteristics may occur. After considering this point, the following facts were discovered. In other words, semiconductor elements are exposed to high temperatures of 650°C to 700°C during glass sealing, but at this time, when the silicon substrate and gold layer are in close contact with each other, the eutectic temperature of gold and silicon is 370°C. Since the gold layer is low, eutectic formation progresses and melts at the interface between the silicon substrate and the gold layer, deteriorating the electrode and deteriorating the electrical characteristics.
したがつて、本発明の目的は650〜700℃の高温
下にあつても電極が劣化しない耐熱電極を提供す
ることにある。 Therefore, an object of the present invention is to provide a heat-resistant electrode that does not deteriorate even under high temperatures of 650 to 700°C.
このような目的を達成するために本発明の半導
体素子は、シリコン基板の主表面の所定領域に形
成された、該所定領域の導電型と同じ導電型の不
純物を含む金と銀の合金からなる下地電極と、こ
の下地電極上に形成された銀からなるバンプ電極
とを具備することを特徴とする。以下実施例によ
り本発明を説明する。 In order to achieve such an object, the semiconductor element of the present invention is made of a gold and silver alloy formed in a predetermined region of the main surface of a silicon substrate and containing impurities of the same conductivity type as that of the predetermined region. It is characterized by comprising a base electrode and a bump electrode made of silver formed on the base electrode. The present invention will be explained below with reference to Examples.
第２図ａ〜ｄは本発明の一実施例による半導体
素子の製造工程を示す。同図ａで示すように、主
面中央部にＰ型導電領域２を形成したＮ型のシリ
コン基板１を用意した後、通常のホトエツチング
技術を用いてＰ型導電領域２の中央電極形成領域
９を除くシリコン基板１の主面を絶縁膜３で被
う。その後、同図ｂで示すように、前記電極形成
領域９に蒸着によつて金層４を形成する。この
際、Ｐ型導電領域２に直接載る金とＰ型導電領域
のシリコンとの共晶化が生じないように、蒸着は
金―シリコン共晶温度（370℃）よりも低い温
度、たとえば200℃で行う。また、この蒸着時金
層内にガリウムも微量含ませ、Ｐ型シリコンとの
金のオーミツク性を向上させる。また、前記金層
４上には同様に共晶温度下で銀層５を蒸着する。
この際、銀層５は金層４よりも厚く形成し、金に
対する銀の体積比は3.5〜10倍となるようにする
（たとえば、金と銀とは２対７〜２対20とす
る。）。 FIGS. 2a to 2d show the manufacturing process of a semiconductor device according to an embodiment of the present invention. As shown in Figure a, after preparing an N-type silicon substrate 1 with a P-type conductive region 2 formed in the center of its main surface, a central electrode formation region 9 of the P-type conductive region 2 is etched using a normal photoetching technique. The main surface of the silicon substrate 1 except for the main surface is covered with an insulating film 3. Thereafter, as shown in FIG. 4B, a gold layer 4 is formed in the electrode forming region 9 by vapor deposition. At this time, the vapor deposition is carried out at a temperature lower than the gold-silicon eutectic temperature (370°C), for example, 200°C, to prevent eutecticization between the gold directly on the P-type conductive region 2 and the silicon of the P-type conductive region. Do it with Further, a small amount of gallium is also included in the gold layer during vapor deposition to improve the ohmic properties of gold with P-type silicon. Furthermore, a silver layer 5 is similarly deposited on the gold layer 4 at the eutectic temperature.
At this time, the silver layer 5 is formed to be thicker than the gold layer 4, and the volume ratio of silver to gold is 3.5 to 10 times (for example, the ratio of gold to silver is 2:7 to 2:20). ).
つぎに、金とシリコンの共晶温度よりも低い温
度で所望時間処理し、同図ｃで示すように金と銀
の相互拡散によつて合金化させ、少なくとも金層
４全体を金銀合金層１０に変化させる。この際、
処理温度は拡散促進のため高いほどよいことか
ら、たとえば300℃とする。 Next, treatment is performed at a temperature lower than the eutectic temperature of gold and silicon for a desired period of time, and as shown in FIG. change to On this occasion,
The treatment temperature is set to 300° C., for example, since the higher the better in order to promote diffusion.
つぎに、同図ｄで示すように、前記金銀合金層
１０および銀層５からなる下地電極上に銀からな
る半球状のバンプ電極６を形成するとともに、シ
リコン基板１の下面にアンチモンを含む金層７お
よび金層７上に重なる銀層８からなる電極を形成
し、半導体素子１１を形成する。 Next, as shown in FIG. An electrode consisting of a silver layer 8 overlapping the layer 7 and the gold layer 7 is formed to form a semiconductor element 11.
このような半導体素子１１は１対のリードの端
面間にそれぞれバンプ電極６および電極を介して
挾持させられるとともに、ガラス管で封止しされ
ることによつてダブルヒートシンクダイオードと
なる。 Such a semiconductor element 11 is sandwiched between the end faces of a pair of leads via the bump electrodes 6 and electrodes, and is sealed with a glass tube, thereby forming a double heat sink diode.
このような実施例による電極はガラス封止温度
においても劣化しない。すなわち、Ｐ型導電領域
に直接接触する層は金銀合金層であるため、金銀
合金とシリコンの三元合金の共晶温度は封止温度
よりも高い。このため、650〜700℃の高温におい
ても電極の劣化は生じない。 Electrodes according to such embodiments do not deteriorate even at glass sealing temperatures. That is, since the layer directly in contact with the P-type conductive region is a gold-silver alloy layer, the eutectic temperature of the ternary alloy of gold-silver alloy and silicon is higher than the sealing temperature. Therefore, the electrodes do not deteriorate even at high temperatures of 650 to 700°C.
なお、本発明は前記実施例に限定されない。た
とえば、電極はＮ型シリコン上に形成する際は金
層にアンチモンを含ませてシリコンとのオーミツ
ク性を向上させるようにする。また、金銀合金層
化の熱処理はバンプ電極形成後に行なつてもよ
い。 Note that the present invention is not limited to the above embodiments. For example, when an electrode is formed on N-type silicon, antimony is included in the gold layer to improve ohmic properties with silicon. Further, the heat treatment for layering the gold-silver alloy may be performed after the bump electrodes are formed.
また、本発明の電極はダイオードに限定される
ものでなくIC等にも適用できる。 Furthermore, the electrode of the present invention is not limited to diodes, but can also be applied to ICs and the like.
以上のように、本発明の耐熱電極は高温化にお
いても劣化しないことから、半導体素子の電気特
性は劣化しない。したがつて、歩留の向上、信頼
性の向上を図ることができる。 As described above, since the heat-resistant electrode of the present invention does not deteriorate even at high temperatures, the electrical characteristics of the semiconductor element do not deteriorate. Therefore, it is possible to improve yield and reliability.
第１図は従来の半導体素子の断面図、第２図ａ
〜ｄは本発明の一実施例による半導体素子の製造
方法を示す各工程での断面図である。
１……シリコン基板、２……Ｐ型導電領域、３
……絶縁膜、４……電極、５……銀層、６……バ
ンプ電極、７……金層、８……銀層、９……電極
形成領域、１０……金銀合金層、１１……半導体
素子。
Figure 1 is a cross-sectional view of a conventional semiconductor device, Figure 2a
-d are cross-sectional views at each step showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. 1... Silicon substrate, 2... P-type conductive region, 3
... Insulating film, 4 ... Electrode, 5 ... Silver layer, 6 ... Bump electrode, 7 ... Gold layer, 8 ... Silver layer, 9 ... Electrode formation region, 10 ... Gold-silver alloy layer, 11 ... ...Semiconductor element.
Claims (1)
た、該所定領域の導電型と同じ導電型の不純物を
含む金と銀の合金からなる下地電極と、この下地
電極上に形成された銀からなるバンプ電極とを具
備することを特徴とする半導体素子。 ２ シリコン基板の主表面に一導電型の所定領域
を形成する工程と、前記所定領域の表面の一部に
該所定領域と同一導電型の不純物を含む金層を金
とシリコンの共晶温度よりも低い温度で形成する
工程と、前記金属上に銀層を金とシリコンの共晶
温度よりも低い温度で形成する工程と、前記銀層
上に銀からなるバンプ電極を形成する工程とを有
し、かつ、前記金層は金と銀との合金層となるよ
うに前記シリコン基板を金とシリコンの共晶温度
より低い温度で加熱する工程とを有することを特
徴とする半導体素子の製造方法。 ３ 前記金層と銀層の体積比は２対７〜２対20と
することを特徴とする特許請求の範囲第２項記載
の半導体素子の製造方法。[Claims] 1. A base electrode formed in a predetermined region of the main surface of a silicon substrate and made of an alloy of gold and silver containing impurities of the same conductivity type as that of the predetermined region; 1. A semiconductor device comprising a bump electrode made of silver. 2. Forming a predetermined region of one conductivity type on the main surface of a silicon substrate, and forming a gold layer containing an impurity of the same conductivity type as the predetermined region on a part of the surface of the predetermined region at a temperature higher than the eutectic temperature of gold and silicon. a step of forming a silver layer on the metal at a temperature lower than the eutectic temperature of gold and silicon; and a step of forming a bump electrode made of silver on the silver layer. and heating the silicon substrate at a temperature lower than the eutectic temperature of gold and silicon so that the gold layer becomes an alloy layer of gold and silver. . 3. The method of manufacturing a semiconductor device according to claim 2, wherein the volume ratio of the gold layer to the silver layer is 2:7 to 2:20.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16556879A JPS5688340A (en) | 1979-12-21 | 1979-12-21 | Heat resistant electrode and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16556879A JPS5688340A (en) | 1979-12-21 | 1979-12-21 | Heat resistant electrode and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5688340A JPS5688340A (en) | 1981-07-17 |
| JPS6217379B2 true JPS6217379B2 (en) | 1987-04-17 |
Family
ID=15814827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16556879A Granted JPS5688340A (en) | 1979-12-21 | 1979-12-21 | Heat resistant electrode and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5688340A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59213145A (en) * | 1983-05-18 | 1984-12-03 | Toshiba Corp | Semiconductor device and manufacture thereof |
-
1979
- 1979-12-21 JP JP16556879A patent/JPS5688340A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5688340A (en) | 1981-07-17 |
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