KR19980025552A - Low Stress Semiconductor Chip Package - Google Patents

Abstract

A semiconductor chip having bonding pads formed on an upper surface thereof; A die pad bonded to a lower surface of the semiconductor chip by a predetermined bonding means; Internal leads electrically connected to the bonding pads; External leads formed integrally with the internal leads to connect with external terminals; And a package body in which the semiconductor chip, the die pad, and the internal leads are internally encapsulated, wherein the semiconductor chip has a plurality of grooves on a lower surface thereof. As a result, the bonding force is increased to prevent the occurrence of package cracks generated between the interface peel and the die pad and the semiconductor chip, thereby improving the reliability of the package.

Description

Low Stress Semiconductor Chip Package

The present invention relates to a semiconductor chip package, and more particularly, to a structure of a semiconductor chip package having improved reliability by preventing the occurrence of interfacial delamination due to stress concentration by increasing the bonding force between the semiconductor chip and the adhesive.

Recently, in the semiconductor industry, a plastic package encapsulated using an epoxy molding compound (EMC) in order to protect the semiconductor device from the external environment, to ensure easy connection with an external terminal, and reliability of the operation of the semiconductor device. Is mainly used.

1 is a cross-sectional view illustrating a general semiconductor chip package.

Referring to FIG. 1, in a general plastic package 70, a semiconductor chip 72 is mounted on a rectangular die pad 74, and spaced at predetermined intervals around the die pad 74 at regular intervals. Bonding pads 84 formed on one side of the inner leads 80 arranged and the upper surface of the semiconductor chip 72 are connected to the gold wire 86, and the die pad 74, the semiconductor chip 72, The bonding wire 86 and the inner leads 80 are formed with a package body 88 of an epoxy molding resin, and the outer leads 82 exposed to the outside of the package body 88 are bent into a shape suitable for mounting. Is completed.

Then, the semiconductor chip package thus completed is subjected to reliability test processes such as thermal cycling (-65 ° C. to 150 ° C.), soak process, and IR reflow process to ensure reliability. Will go through.

However, the molding process in which the package body is formed is performed at about 175 ° C. in which residual stress does not occur, and the semiconductor chip package is cooled again at room temperature (25 ° C.), wherein the coefficient of thermal expansion according to temperature change The difference causes warpage of the semiconductor chip package and, in addition, the semiconductor chip package contains residual thermal stress. Then, when the thermal test process proceeds, interfacial peeling due to the difference in thermal expansion coefficient between materials occurs at each interface of the epoxy molding resin, the lead frame, the adhesive, the semiconductor chip, the semiconductor chip, and the epoxy molding resin. Furthermore, the soak process (85 ° C, 85%) forces the semiconductor chip package to absorb moisture, and during the high temperature (about 240 ° C) infrared reflow process, the moisture present in the semiconductor chip package generates water vapor pressure. It causes a popcorn crack.

Various measures have been introduced to reduce the occurrence of package cracks and interfacial delamination due to the thermal stress. An embodiment thereof is described below.

2 is a cross-sectional view illustrating a state in which interfacial peeling occurs in an embodiment of a semiconductor chip package according to the related art.

Referring to FIG. 2, a plurality of dimples 76 are formed on a lower surface of the die pad, and thus, the die pad 74 and the package body 88 are increased by increasing the bonding force of the epoxy molded resin material with the package body 88. The peeling phenomenon at the interface between them was prevented. However, a gap 90 is formed at the interface between the semiconductor chip 72 and the adhesive 78.

In the above-described embodiment, although the interface peeling phenomenon between the die pad and the epoxy molding resin is reduced, the interface peeling phenomenon occurs due to the concentration of thermal stress at the interface between the semiconductor chip and the adhesive and at the corners of the die pad. Reduce the reliability of the semiconductor chip package.

Accordingly, an object of the present invention is to provide a high reliability low stress semiconductor chip package by preventing the occurrence of interfacial peeling by increasing the bonding force between the semiconductor chip and the adhesive.

1 is a cross-sectional view showing a general semiconductor chip package.

2 is a cross-sectional view showing a state in which interfacial peeling occurs in an embodiment of a semiconductor chip package according to the prior art.

3 is a cross-sectional view showing an embodiment of a semiconductor chip package according to the present invention.

4 to 7 are process diagrams illustrating a process of forming grooves on a rear surface of the semiconductor chip package of FIG. 3.

Explanation of symbols for the main parts of the drawings

10,70 semiconductor chip package 12,72 semiconductor chip

14,74: die pad 16,76: dimple

18,78: adhesive 20,80: internal lead

22,82: external lead 24,84: bonding pad

26,86 gold wire 28,88 package body

30,48: groove 40: wafer

42 photoresist layer 44 mask

46: scribe line

A low stress semiconductor chip package according to the present invention for achieving the above object is a semiconductor chip having bonding pads formed on the upper surface; A die pad bonded to a lower surface of the semiconductor chip by a predetermined bonding means; Internal leads electrically connected to the bonding pads; External leads formed integrally with the internal leads to connect with external terminals; And a package body in which the semiconductor chip, the die pad, and the internal leads are internally encapsulated, wherein the semiconductor chip has a plurality of grooves on a lower surface thereof.

Hereinafter, a low stress semiconductor chip package according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view showing an embodiment of a semiconductor chip package according to the present invention.

Referring to FIG. 3, the semiconductor chip 12 is attached to the upper surface of the die pad 14 by an adhesive 18, and the inner lead 20 and the semiconductor chip spaced apart from the die pad 14 by a predetermined distance. The bonding pads 24 formed on the upper surface of the wire 12 are wire-bonded with gold wires 26, and the package body 28 is made of epoxy molding resin in order to ensure reliability in the operation of the semiconductor chip 12 from an external environment. ) Is formed. At this time, the lower surface of the semiconductor chip 12 attached to the die pad 14 has a plurality of grooves 30. A portion having such a shape is attached so as to be in the adhesive 18 portion. Usually, package cracks occur at the bonding interface portion of the semiconductor chip 12 and the die pad 14, but the semiconductor chip 12 and the adhesive 18 are formed by having the grooves 30 in the lower surface of the semiconductor chip 12. The bond area with is increased. Increasing the bonding area may result in an increase in the bonding force, thereby preventing the occurrence of peeling phenomenon at the interface. Forming the grooves 30 on the lower surface of the semiconductor chip 12 may be performed in the wafer state by the following process.

4 to 7 are process diagrams illustrating a process of forming a groove in a lower surface of a semiconductor chip in the semiconductor chip package of FIG. 3.

First, as shown in FIG. 4, a photoresist is applied to the lower surface of the wafer 40 to form a photoresist layer 42. As the photoresist used herein, a photoresist generally used in a wafer process may be used. An exposure mask 44 is covered on the photoresist layer 42 formed on the rear surface of the wafer 40 as shown in FIG. 5. In this case, the grooves of the mask 44 are configured to expose the inner portion of the scribe line 46. It exposes in this state. Etching the wafer 40 after the exposure is completed, a plurality of grooves 48 are formed in the inner portion of the scribe line 46 as shown in FIG. When the mask 44 is removed and the photoresist layer 42 is removed while the groove 48 is formed, the wafer 40 having the grooves 48 formed on the inner portion of the scribe line 46 is formed as shown in FIG. 7. You can get it. Each semiconductor chip formed through the wafer cutting process has a groove on its lower surface. As such, having a groove on the lower surface of the semiconductor chip may be easily performed in a wafer process.

Therefore, according to the structure according to the present invention, by increasing the bonding force between the semiconductor chip and the adhesive, there is an advantage that can improve the reliability of the package by preventing the occurrence of interfacial peeling and package cracks.

Claims (2)

A semiconductor chip having bonding pads formed on an upper surface thereof; A die pad bonded to a lower surface of the semiconductor chip by a predetermined bonding means; Internal leads electrically connected to the bonding pads; External leads formed integrally with the internal leads to connect with external terminals; And a package body in which the semiconductor chip, the die pad, and the internal leads are internally encapsulated, wherein the semiconductor chip has a plurality of grooves on a lower surface thereof. The low stress semiconductor chip package of claim 1, wherein the grooves of the semiconductor chip are formed by etching in a wafer process.