KR0169821B1 - Semiconductor chip package - Google Patents
Semiconductor chip package Download PDFInfo
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- KR0169821B1 KR0169821B1 KR1019950025678A KR19950025678A KR0169821B1 KR 0169821 B1 KR0169821 B1 KR 0169821B1 KR 1019950025678 A KR1019950025678 A KR 1019950025678A KR 19950025678 A KR19950025678 A KR 19950025678A KR 0169821 B1 KR0169821 B1 KR 0169821B1
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- chip package
- package
- die pad
- metal plate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 칩 패키지에 관한 것으로서, 복수의 본딩패드를 갖는 반도체 칩과, 반도체 칩이 실장되는 다이패드와, 본딩패드들에 대응하여 전기적으로 연결된 내부리드들과, 내부리드들과 일체형으로 형성되어 외부 단자들과 접속을 하기 위한 외부리드들과, 반도체 칩과 다이패드와 내부리드들을 봉지하는 패키지 몸체를 포함하는 반도체 칩 패키지에 있어서, 다이패드를 중심으로 상부와 하부 중 적어도 어느 하나의 패키지 몸체 영역에 다이패드와 이격되도록 하여 내부리드에 적어도 하나 이상의 홈이 형성된 금속판이 부착되어 있으며, 홈에 흡습성 폴리이미드 테이프가 부착된 것을 특징으로 한다. 이에 따르면, 에폭시계 성형수지와 반도체 칩 패키지 내부소자와의 접착계면에 미치는 열응력을 완화시켜 줌과 동시에 계면박리 및 초기 균열을 줄일 수 있으며 패키지 내부 특히 다이패드 밑면 부위로 수분이 침투하는 경로를 차단하여 패키지 크랙을 방지할 수 있다.The present invention relates to a semiconductor chip package, comprising a semiconductor chip having a plurality of bonding pads, a die pad on which the semiconductor chip is mounted, internal leads electrically connected to the bonding pads, and integrally formed with the internal leads. A semiconductor chip package including external leads for connecting to external terminals, and a package body for encapsulating the semiconductor chip, the die pad, and the internal leads, wherein at least one package of the upper and lower portions of the upper and lower portions of the semiconductor chip package includes: a package body; A metal plate having at least one groove formed on the inner lead is attached to the body region so as to be spaced apart from the die pad, and a hygroscopic polyimide tape is attached to the groove. According to this, the thermal stress on the adhesion interface between the epoxy resin and the semiconductor chip package element can be alleviated, and the interfacial peeling and initial cracking can be reduced. This prevents package cracks.
Description
제1도는 종래 기술의 일 실시예에 따른 반도체 칩 패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a semiconductor chip package according to an embodiment of the prior art.
제2도는 본 발명의 일 실시예에 따른 반도체 칩 패키지의 구조를 나타낸 단면도.2 is a cross-sectional view showing the structure of a semiconductor chip package according to an embodiment of the present invention.
제3도는 제2도의 반도체 칩 패키지 일부를 절개한 단면도.3 is a cross-sectional view of a portion of the semiconductor chip package of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체 칩 12 : 접착제10 semiconductor chip 12 adhesive
14 : 다이패드 15 : 리이드프레임14: die pad 15: lead frame
16 : 리드 16A : 내부리드16: Lead 16A: Internal Lead
16B : 외부리드 18 : 본딩와이어16B: external lead 18: bonding wire
20 : 패키지 몸체 22 : 제1성형층20: package body 22: first molding layer
24 : 제2성형층 30 : 금속판24: second molding layer 30: metal plate
32 : 홈 34 : 폴리이미드 테이프32: groove 34: polyimide tape
36 : 관통구멍 38 : 비전도성 접착제36 through hole 38 non-conductive adhesive
본 발명은 반도체 칩 패키지에 관한 것으로, 더욱 상세하게는 반도체 칩이 실장된 다이패드의 상부와 하부 중 적어도 하나의 패키지 몸체 영역에 금속판이 형성되어 있으며, 그 금속판에 흡습성 폴리이미드 테이프를 갖는 반도체 칩 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip package, and more particularly to a semiconductor chip having a metal plate formed on at least one package body region of an upper portion and a lower portion of a die pad on which the semiconductor chip is mounted, and having a hygroscopic polyimide tape on the metal plate. It's about packages.
최근의 반도체 산업에 있어서, 반도체 소자를 외부 환경으로부터 보호하고 외부 단자와의 용이한 연결 및 반도체 소자의 동작에 대한 신뢰성을 확보하기 위하여 에폭시계 성형 수지(EMC: Epoxy Molding Compound)를 사용하여 봉지된 플라스틱 패키지가 주로 사용되고 있다.In the recent semiconductor industry, an epoxy molding compound (EMC) is encapsulated in order to protect a semiconductor device from an external environment, to facilitate connection with an external terminal, and to secure reliability of the operation of the semiconductor device. Plastic packages are mainly used.
일반적인 플라스틱 패키지는 사각형상의 다이패드 상에 반도체 칩이 실장되고, 다이패드의 주변에 소정의 간격으로 이격되어 있으며, 일정 간격으로 배열되어 있는 리드들의 일측과 반도체 칩의 상면에 형성되어 있는 본딩패드들이 와이어로 연결되며, 다이패드, 반도체 칩, 본딩와이어, 내부리드들은 에폭시계 성형 수지로 봉지되며(성형된 에폭시계 성형 수지 부분은 이하 패키지 몸체라고 함), 패키지 몸체의 외부로 돌출되어 있는 외부 리드들이 실장에 적합한 형상으로 절곡됨으로써 완성된다.In a typical plastic package, semiconductor chips are mounted on a rectangular die pad, spaced at predetermined intervals around the die pad, and bonding pads formed on one side of the leads and the upper surface of the semiconductor chip are arranged at regular intervals. Connected by wire, the die pad, semiconductor chip, bonding wire, and inner leads are encapsulated with epoxy-based molding resin (molded epoxy-based resin part is hereinafter referred to as package body), and external leads protruding out of the package body. This is completed by bending them into a shape suitable for mounting.
그리고 나서, 이렇게 완성된 반도체 칩 패키지는 신뢰성을 확보하기 위하여 열적 검사 공정(Temperature Cycling; -65℃∼150℃; 이하 T/C공정이라고 함)과 소우크(soak)공정 및 적외선 리플로우(IR Reflow) 공정 등과 같은 신뢰성 테스트 공정을 거치게 된다.The semiconductor chip package thus completed is then subjected to a thermal inspection process (Temperature Cycling; -65 ° C to 150 ° C; hereinafter referred to as a T / C process), a soak process, and an infrared reflow (IR). Reliability process, such as reflow process.
그러나, 패키지 몸체가 형성되는 성형 공정은 약 175℃에서 이루어지며, 성형이 끝난 반도체 칩 패키지는 다시 상온 상태(25℃)로 냉각되는데, 이때 온도변화에 따라 반도체 칩 패키지를 구성하는 각 구성요소들간의 열팽창의 차이는 반도체 칩 패키지의 휨을 발생시키고, 더불어 반도체 칩 패키지는 잔류 열응력을 내포하게 된다. 그리고, T/C공정이 진행될 때 에폭시 성형 수지의 각 계면에서는 재료간의 열팽창 차이에 의한 계면 박리가 발생한다.However, the molding process in which the package body is formed is performed at about 175 ° C., and the semiconductor chip package after the molding is cooled to room temperature (25 ° C.) again, at which time between the components constituting the semiconductor chip package according to the temperature change. The difference in thermal expansion causes the warpage of the semiconductor chip package, and the semiconductor chip package also contains residual thermal stress. In addition, when the T / C process proceeds, the interface peeling due to the difference in thermal expansion between materials occurs at each interface of the epoxy molding resin.
더욱이, 소우크 공정(85℃, 85%)에 의해 반도체 칩 패키지는 강제적으로 수분을 흡수하게 되며, 고온(약 240℃)의 적외선 리플로우 공정에서 반도체 칩 패키지 내에 존재하는 수분은 수증기압을 발생시킴으로써 전형적인 팝콘 크랙(Pop-corn Crack)을 유발시키게 된다.Further, the semiconductor chip package is forcibly absorbed by the soak process (85 ° C., 85%), and the moisture present in the semiconductor chip package in the high temperature (about 240 ° C.) infrared reflow process generates water vapor pressure. This will cause a typical pop-corn crack.
그러므로, 신뢰성 테스트의 진행에 따른 반도체 칩 패키지 내의 잔류 응력에 의한 크랙의 발생을 최소화하기 위한 여러 가지 방안들이 소개되었다.Therefore, various methods have been introduced to minimize the occurrence of cracks due to residual stress in the semiconductor chip package according to the progress of the reliability test.
그 중 한 방안이 가와하라 외 2명의 미합중국 특허 제4,788,583호에 개시되어 있는 바와 같이, 반도체 칩 패키지의 성형층을 이중 구조를 갖게 하는 것이다.One of them is to have a double structure of a molded layer of a semiconductor chip package, as disclosed in U.S. Patent No. 4,788,583 by Kawahara and two others.
이와 같이 구성되는 반도체 칩 패키지를 제1도를 참조하여 살펴보면 다음과 같다.The semiconductor chip package configured as described above will be described with reference to FIG. 1.
제1도를 참조하면, 반도체 칩(10)과 그 반도체 칩(10)이 실장된 리이드프레임(15)의 대부분과 그 반도체 칩(10)과 리이드프레임(15) 부분을 연결시키는 본딩와이어(도시 안됨)들은 에폭시계 성형 수지로 형성된 제1성형층(22)에 의해 봉지된다. 제1성형층(22)이 형성된 후 다시 재성형이 이루어져서 제2성형층(24)이 형성된다. 여기서 반도체 칩 패키지는 이중의 성형층(22, 24) 구조를 이루게 되며, 그 이중의 성형층 구조는 반도체 칩 패키지 내부로의 수분 침투를 방지한다.Referring to FIG. 1, a bonding wire connecting most of a semiconductor chip 10 and a lead frame 15 on which the semiconductor chip 10 is mounted, and a portion of the semiconductor chip 10 and the lead frame 15, is illustrated. Or the like) is encapsulated by the first molding layer 22 formed of an epoxy-based molding resin. After the first molding layer 22 is formed, the second molding layer 24 is formed by reforming again. In this case, the semiconductor chip package forms a double forming layer 22 and 24 structure, and the double forming layer structure prevents moisture penetration into the inside of the semiconductor chip package.
그러나, 이중 성형작업시 성형층간의 경계면에서는 보이드(void)가 발생되어 두 층간의 접착력은 약화되고 증가된 성형작업으로 인한 불완전한 충전은 성형불량을 발생시킬 수 있다.However, in the double molding operation, voids are generated at the interface between the molding layers, so that the adhesion between the two layers is weakened, and incomplete filling due to the increased molding operation may cause molding failure.
반도체 칩 패키지 내의 잔류 응력에 의한 크랙의 발생을 최소화하기 위한 또 다른 방안으로서, 플라스틱 패키지에 관통구멍을 갖게 하는 방안이다. 그 구조를 설명하면 다음과 같다.Another method for minimizing the occurrence of cracks due to residual stress in the semiconductor chip package is to provide a through hole in the plastic package. The structure is as follows.
다이패드 하부면에서 수증기압에 의해 발생하는 패키지 크랙을 없애기 위하여 다이패드 하부에 관통구멍을 두어 수분의 침투를 허용하는 구조이다. 그러나, 이 구조는 관통구멍의 직경을 정확하게 통제해야 하며 수분에 대응한 신뢰성을 확보해야 하는 문제점이 있다.In order to eliminate package cracks caused by water vapor pressure on the bottom of the die pad, a through hole is provided in the bottom of the die pad to allow the penetration of moisture. However, this structure has a problem in that the diameter of the through hole must be precisely controlled and the reliability corresponding to moisture is secured.
따라서 본 발명의 목적은 반도체 칩 패키지의 내부 소자간의 접착계면에 미치는 열응력을 완화시켜 줌과 동시에 잔류하는 수분을 분산시킴으로서 수증기압에 의한 기계적 응력을 부산시켜 반도체 칩 패키지의 신뢰성을 향상시킬 수 있는 반도체 칩 패키지를 제공하는데 있다.Accordingly, an object of the present invention is to reduce the thermal stress on the adhesion interface between the internal elements of the semiconductor chip package and to disperse the remaining moisture, thereby releasing the mechanical stress caused by water vapor pressure to improve the reliability of the semiconductor chip package. To provide a chip package.
상기 목적을 달성하기 위한 본 발명에 따른 반도체 칩 패키지는 복수의 본딩 패드를 갖는 반도체 칩과, 반도체 칩이 실장되는 다이패드와, 본딩패드들에 대응하여 전기적으로 연결된 내부리드들과, 내부리드들과 일체형으로 형성되어 외부 단자들과 접속을 하기 위한 외부리드들과 반도체 칩과 다이패드와 내부리드들을 봉지하는 패키지 몸체를 포함하는 반도체 칩 패키지에 있어서, 다이패드를 중심으로 상부와 하부 중 적어도 어느 하나의 패키지 몸체 영역에 다이패드와 이격되도록 하여 내부리드에 적어도 하나 이상의 홈이 형성된 금속판이 부착되어 있으며, 홈에 흡습성 폴리이미드 테이프가 부착된 것을 특징으로 한다.The semiconductor chip package according to the present invention for achieving the above object is a semiconductor chip having a plurality of bonding pads, a die pad on which the semiconductor chip is mounted, internal leads electrically connected to the bonding pads, and internal leads A semiconductor chip package including a package body formed integrally with an external lead for connecting to external terminals, and a package body encapsulating the semiconductor chip, the die pad, and the inner leads, wherein at least any one of an upper portion and a lower portion with respect to the die pad; A metal plate having at least one groove formed on the inner lead is attached to one package body area so as to be spaced apart from the die pad, and a hygroscopic polyimide tape is attached to the groove.
이하, 첨부된 도면을 참조하여 본 발명을 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도는 본 발명의 일 실시예에 따른 반도체 칩 패키지의 구조를 나타낸 단면도이다.2 is a cross-sectional view illustrating a structure of a semiconductor chip package according to an embodiment of the present invention.
제3도는 제2도의 반도체 칩 패키지 일부를 절개한 단면도이다.3 is a cross-sectional view of a portion of the semiconductor chip package of FIG. 2.
제2도를 참조하면, 사각형상의 다이패드(14) 상에 반도체 칩(10)이 접착제(12)로 실장되어 있으며, 다이패드(14)의 양측으로 소정의 간격으로 리이드(16)들이 배치되어 있고, 리이드(16)들의 일측이 반도체 칩(10)의 본딩패드(도시 안됨)들과 본딩와이어(18)로 연결되어 있다. 또한 반도체 칩(10)과 다이패드(14) 및 본딩와이어(18)와 내부리이드(16A) 등을 감싸 보호하는 에폭시계 성형 수지로 된 패키지 몸체(20)가 수지 봉지 방법으로 형성되어 있다. 이때, 다이패드(14) 하부의 에폭시계 성형 수지 영역에는 금속판(30)이 위치하고 있다. 그 금속판(30)은 가장자리 부분에서 둔각을 이루도록 굴곡되어져 있고 말단부가 내부리이드(16A)의 하부면에 비전도성 접착제(38)로 부착되어 있다.Referring to FIG. 2, the semiconductor chip 10 is mounted on the rectangular die pad 14 with the adhesive 12, and the leads 16 are disposed at predetermined intervals on both sides of the die pad 14. One side of the leads 16 is connected to the bonding pads (not shown) of the semiconductor chip 10 by the bonding wires 18. In addition, a package body 20 made of an epoxy-based molding resin that wraps and protects the semiconductor chip 10, the die pad 14, the bonding wire 18, the inner lead 16A, and the like is formed by a resin encapsulation method. At this time, the metal plate 30 is located in the epoxy-based molded resin region under the die pad 14. The metal plate 30 is bent at an obtuse angle at the edge portion, and the distal end is attached to the lower surface of the inner lead 16A with a nonconductive adhesive 38.
제3도를 참조하여 제2도의 금속판(30)에 대하여 좀 더 상세히 설명하면 다음과 같다. 다이패드(제2도의 14)를 하방향으로 수직 투영하여 금속판 하부면에 투영된 다이패드 면을 다이패드 하방향 수직투영면(도면의 이점쇄선 부분의 내측부분; 이하 생략)이라 할 때, 그 다이패드 하방향 수직투영면의 내측에는 4개의 홈(32)이 형성되어져 있으며, 그 다이패드 하방향 수직투영면의 외측에는 금속판(30)을 관통하여 6개의 관통구멍(36)이 형성되어 있다. 그리고, 관통구멍(36)은 다이패드 하방향 수직투영면을 중심으로 대칭성을 가지도록 형성되어 있고, 홈은 다이패드 하방향 수지투영면의 중심을 기준으로 대칭성을 가지도록 형성되어 있다. 또한 그 홈의 저면에 흡습성을 갖는 폴리이미드 테이프(34)가 부착되어 있다.The metal plate 30 of FIG. 2 will be described in more detail with reference to FIG. 3 as follows. When the die pad (14 in FIG. 2) is vertically projected downward and the die pad surface projected on the lower surface of the metal plate is referred to as the die pad downward vertical projection surface (inner portion of the double-dotted line portion of the drawing; hereinafter omitted), the die pad Four grooves 32 are formed inside the pad downward vertical projection surface, and six through holes 36 are formed outside the die pad downward vertical projection surface through the metal plate 30. The through hole 36 is formed to have symmetry around the die pad downward vertical projection surface, and the groove is formed to have symmetry with respect to the center of the die pad downward resin projection surface. Further, a polyimide tape 34 having hygroscopicity is attached to the bottom of the groove.
본 발명에 따른 반도체 칩 패키지의 작용을 설명하면 다음과 같다.Referring to the operation of the semiconductor chip package according to the present invention.
T/C 공정이 진행될 때 온도차에 의하여 각 재료간에는 열팽창계수의 차이가 발생하는데, 이때 에폭시계 성형수지와 패키지 내부와의 접착계면에 미치는 열응력을 금속판이 완화시켜 주어 계면박리 및 초기균열을 사전에 줄일 수 있다. 상세하게 설명하면 다음과 같다.During the T / C process, the difference in thermal expansion coefficient occurs between the materials due to the temperature difference.At this time, the metal sheet alleviates the thermal stress on the adhesion interface between the epoxy-based molding resin and the inside of the package to prevent interfacial peeling and initial cracking. Can be reduced. It will be described in detail as follows.
외부리이드와 에폭시계 성형수지의 틈 사이로 침투한 수분은 금속판을 따라 금속판의 하부면에 잔류하게 된다. 이렇게 잔류된 수분은 일정한 형태로 굴곡되어진 홈 부위로 집중되고, 그 홈에 부착된 흡수성의 폴리이미드 테이프가 그 수분을 흡수한다. 따라서, 패키지 내부의 계면 부위에 수분이 집중되지 않는다.Moisture penetrated between the outer lead and the gap of the epoxy-based molding resin remains on the lower surface of the metal plate along the metal plate. The remaining water is concentrated in the groove portion bent in a certain shape, and the absorbent polyimide tape attached to the groove absorbs the moisture. Therefore, moisture is not concentrated in the interface portion inside the package.
또한, 관통구멍은 성형공정에서 성형수지의 출입이 가능하여 균일한 성형층을 이룰 수 있으며, 성형이 끝난 후 금속판과 패키지 몸체와의 결합력을 증가시켜 준다. 더욱이 관통구멍이 이루는 대칭성 구조는 결합력의 고른 분포를 가져와 어느 한 쪽으로 힘이 집중되는 것을 막는다.In addition, the through-holes can be formed in the molding process in the molding process to form a uniform forming layer, and increases the bonding force between the metal plate and the package body after forming. Moreover, the symmetrical structure of the through-holes results in an even distribution of coupling forces, preventing the force from being concentrated on either side.
본 발명에 의한 반도체 칩 패키지는 제2도에서와 같이 금속판이 리이드프레임 하부에 형성된 것에 제한되지 않고 리이드 프레임 상부 또는 하부 중 적어도 어느 하나에 형성될 수 있다. 또한, 제2도 및 제3도에서와 같이 홈과 관통구멍이 각각 4개, 6개 형성되어 있는 것에 한정되지 않고 적어도 하나 이상인 것을 포함하며, 그 홈과 관통구멍의 형상과 크기가 일정한 크기의 원형 및 사각형으로 형성되어 있지만 그에 제한되지 않는다.The semiconductor chip package according to the present invention is not limited to the metal plate formed below the lead frame as shown in FIG. In addition, as shown in FIG. 2 and FIG. 3, the groove and the through hole are not limited to four or six, respectively, and include at least one or more, and the groove and the through hole have a constant size and size. It is formed in a circle and a square, but is not limited thereto.
한편, 금속판은 프레스 가공에 의하여 쉽게 굴곡을 만들 수 있으며, 금속판과 에폭시계 성형수지와의 접착력을 증대시킴으로써 열응력에 대한 저항을 향상시켜 주기 위하여 일정한 형태로 형성된 관통구멍은 프레스 절단 작업으로 쉽게 만들 수 있다.On the other hand, the metal plate can be easily bent by press working, and the through-hole formed in a certain shape can be easily made by press cutting operation to improve the resistance to thermal stress by increasing the adhesion between the metal plate and the epoxy-based molding resin. Can be.
이상과 같이 본 발명에 따른 반도체 칩 패키지 구조에 따르면, 에폭시계 성형수지와 반도체 칩 패키지 내부소자와의 접착계면에 미치는 열응력을 완화시켜 줌과 동시에 계면박리 및 초기 균열을 사전에 줄일 수 있으며 패키지 내부 특히 다이패드 밑면 부위로 수분이 침투하는 경로를 차단하여 패키지 크랙을 방지할 수 있는 이점(利點)이 있다.As described above, according to the semiconductor chip package structure according to the present invention, the thermal stress on the adhesion interface between the epoxy-based molding resin and the internal element of the semiconductor chip package can be alleviated, and at the same time, the interface peeling and the initial crack can be reduced in advance. There is an advantage that can prevent the package crack by blocking the passage of moisture to the inside, especially the bottom portion of the die pad.
Claims (14)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025678A KR0169821B1 (en) | 1995-08-21 | 1995-08-21 | Semiconductor chip package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025678A KR0169821B1 (en) | 1995-08-21 | 1995-08-21 | Semiconductor chip package |
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| Publication Number | Publication Date |
|---|---|
| KR970013281A KR970013281A (en) | 1997-03-29 |
| KR0169821B1 true KR0169821B1 (en) | 1999-01-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950025678A KR0169821B1 (en) | 1995-08-21 | 1995-08-21 | Semiconductor chip package |
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| KR (1) | KR0169821B1 (en) |
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1995
- 1995-08-21 KR KR1019950025678A patent/KR0169821B1/en not_active IP Right Cessation
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| KR970013281A (en) | 1997-03-29 |
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