KR100268922B1 - semiconductor package and method for fabricating the same - Google Patents

semiconductor package and method for fabricating the same Download PDF

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Publication number
KR100268922B1
KR100268922B1 KR1019970067041A KR19970067041A KR100268922B1 KR 100268922 B1 KR100268922 B1 KR 100268922B1 KR 1019970067041 A KR1019970067041 A KR 1019970067041A KR 19970067041 A KR19970067041 A KR 19970067041A KR 100268922 B1 KR100268922 B1 KR 100268922B1
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South Korea
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die pad
chip
lead
line
inner lead
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KR1019970067041A
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Korean (ko)
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KR19990048376A (en
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이현일
김진섭
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to designed for all chips having size less than that is defined by the line of inner leads and a line spaced from the line. CONSTITUTION: The semiconductor package includes a plurality of outer lead(1), an inner lead(2), a die pad(3), a chip(4), an adhesive(5), a plurality of conductive members(6) and a mold body(7). The inner lead(2) is formed on the pate same to that of the outer lead. The die pad is downset compared with the inner lead which is implemented in the inner lead. The chip is bonded to the surface of the die pad and has the size defined by the line of inner leads and an imaginary line spaced from the line. The adhesive member is applied on the surface of the die pad to couple the chip to the die pad. The conductive members electrically couple the bonding pads and the inner leads, respectively. The mold body packages the overall structure but the outer leads.

Description

반도체 패키지 및 그 제조 방법{semiconductor package and method for fabricating the same}Semiconductor package and method for fabricating the same

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 리드프레임의 다이패드(die pad) 사이즈와 무관하게 인너리드 선단이 이루는 선으로부터 일정거리 이격된 임의의 선이 이루는 면적 이하의 사이즈를 갖는 칩은 전부 적용 가능하도록 한 반도체 패키지를 제공하기 위한 것이다.The present invention relates to a semiconductor package, and more particularly, a chip having a size less than or equal to an area formed by an arbitrary line spaced a certain distance from a line formed by an inner lead end, regardless of a die pad size of a lead frame. It is to provide a semiconductor package that can be applied to all.

종래의 반도체 패키지는 도 1 내지 도 3에 나타낸 바와 같이, 리드프레임의 타이바 부분에 다운-셋(down-set)이 되어 있지 않으며, 리드프레임의 다이패드(3)를 칩(4)보다 작게 설계한다.In the conventional semiconductor package, as shown in FIGS. 1 to 3, the tie bar portion of the lead frame is not down-set, and the die pad 3 of the lead frame is smaller than the chip 4. Design.

또한, 상기 다이패드(3)의 표면에 요홈(8)을 형성하여 칩 본딩시 상기 요홈(8)에 다이 접착제(5)를 도포하여 칩 본딩을 행하게 된다.In addition, the groove 8 is formed on the surface of the die pad 3 so that the chip bonding is performed by applying the die adhesive 5 to the groove 8 during chip bonding.

따라서, 종래에는 리드프레임의 다이패드(3)가 칩(4) 사이즈 보다 작으므로 인해, 와이어 본딩시 사용되는 치공구인 히터블록(9)을 특수하게 제작하여 사용하게 된다.Therefore, in the related art, since the die pad 3 of the lead frame is smaller than the size of the chip 4, the heater block 9, which is a tool used for wire bonding, is specially manufactured and used.

한편, 상기에서 칩(4) 사이즈 보다 리드프레임 다이패드(3)를 작게 하는 이유는 패키지 내부로의 수분침투 후, 열을 받을 경우 수분 팽창에 따른 패키지 크랙이 일어나기 때문에 이를 방지하기 위함이다.Meanwhile, the reason why the lead frame die pad 3 is smaller than the size of the chip 4 is to prevent the package crack due to moisture expansion when the heat is received after moisture penetration into the package.

즉, 수분은 리드프레임의 다이패드(3) 아래로 응집되는데, 도 3에 나타낸 바와 같이 칩(4) 사이즈보다 다이패드(3)가 큰 경우에는 수분 침투량도 많아지게 되며, 실장시 솔더 리플로우에 의해서 열을 받아 수분 팽창이 일어날 경우 크랙(crack) 및 계면분리(delamination) 현상을 일으키기가 더욱 쉬우므로 다이패드(3)의 사이즈를 칩(4)보다 작게 설계하여야 한다.That is, moisture is agglomerated under the die pad 3 of the lead frame. As shown in FIG. 3, when the die pad 3 is larger than the size of the chip 4, the moisture penetration amount also increases, and solder reflow during mounting is performed. When the expansion of the water by the heat occurs, it is easier to cause cracks and delamination phenomenon, so the size of the die pad (3) should be designed smaller than the chip (4).

그러나, 상기한 종래의 반도체 패키지는 리드프레임의 다이패드(3) 보다 반드시 큰 칩(4)을 사용해야만 하므로 리드프레임의 범용성이 떨어지고, 리드프레임의 다이패드(3)의 두께가 인너리드(2) 등의 두께와 상이하므로 별도의 제작이 요구되며, 다이패드(3)의 표면에 요홈(8)을 형성해야 하므로 제작상에 어려움이 따르는 등 많은 문제점이 있었다.However, since the conventional semiconductor package described above must use a larger chip 4 than the die pad 3 of the lead frame, the general purpose of the lead frame is inferior, and the thickness of the lead pad die pad 3 is inner lead 2. Since it is different from the thickness, etc.), a separate production is required, and the groove 8 must be formed on the surface of the die pad 3, and thus there are many problems such as difficulty in manufacturing.

본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 리드프레임의 다이패드 사이즈와 무관하게 인너리드 선단이 이루는 선으로부터 일정거리 이격된 임의의 선이 이루는 면적 이하의 사이즈를 갖는 칩은 전부 적용 가능하도록 한 반도체 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and irrespective of the die pad size of the lead frame, all chips having a size less than or equal to an area formed by an arbitrary line spaced from a line formed by the inner lead end may be applicable. It is an object of the present invention to provide a semiconductor package and a method of manufacturing the same.

도 1은 종래의 반도체 패키지를 나타낸 종단면도1 is a vertical cross-sectional view showing a conventional semiconductor package

도 2는 도 1의 Ⅰ-Ⅰ선을 나타낸 요부 횡단면도2 is a cross-sectional view showing main parts of the line I-I of FIG.

도 3은 도 1의 반도체 패키지 제조를 위한 와이어 본딩 공정을 보여주는 종단면도3 is a longitudinal cross-sectional view illustrating a wire bonding process for manufacturing the semiconductor package of FIG. 1.

도 4는 리드 프레임의 패드가 칩 사이즈보다 큰 경우에 발생하는 문제점을 설명하기 위한 일반적인 패키지 종단면도Figure 4 is a general package longitudinal cross-sectional view for explaining the problem that occurs when the pad of the lead frame is larger than the chip size

도 5는 본 발명에 따른 반도체 패키지의 제1실시예를 나타낸 종단면도5 is a longitudinal sectional view showing a first embodiment of a semiconductor package according to the present invention;

도 6은 도 5의 Ⅱ-Ⅱ선을 나타낸 횡단면도FIG. 6 is a cross-sectional view showing line II-II of FIG. 5.

도 7은 본 발명에 따른 반도체 패키지의 제2실시예를 나타낸 종단면도7 is a longitudinal sectional view showing a second embodiment of a semiconductor package according to the present invention.

도 8은 도 7의 Ⅲ-Ⅲ선을 나타낸 횡단면도FIG. 8 is a cross-sectional view illustrating line III-III of FIG. 7.

도 9는 본 발명의 반도체 패키지의 제3실시예를 나타낸 종단면도9 is a longitudinal sectional view showing a third embodiment of the semiconductor package of the present invention;

도 10은 도 9의 Ⅳ-Ⅳ선을 나타낸 종단면도FIG. 10 is a longitudinal cross-sectional view taken along line IV-IV of FIG. 9;

도 11은 도 10의 Ⅴ-Ⅴ선을 나타낸 횡단면도FIG. 11 is a cross-sectional view illustrating the VV line of FIG. 10.

도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings

1.아웃터리드 2:인너리드1.Outstanding 2: Inner Lead

3:다이패드 4:칩3: diepad 4: chip

5:접착제 6:전도성부재5: adhesive 6: conductive member

7:몰드바디7: Molded body

상기한 목적을 달성하기 위해, 본 발명은 복수개의 아웃터리드와, 상기 아웃터리드와 동일 평면상에서 연장형성된 인너리드와, 상기 인너리드 내측에 위치하며 상기 인너리드에 비해 다운셋된 다이패드와, 상기 다이패드 상면에 본딩되며 인너리드의 선단을 잇는 선으로부터 일정거리 이격된 가상의 선이 이루는 면적 범위 내의 사이즈를 갖는 칩과, 상기 다이패드에 칩이 결합되도록 다이패드 상면에 도포되는 접착제와, 상기 칩의 본딩패드들과 인너리드들을 전기적으로 각각 연결하는 복수개의 전도성부재와, 상기 아웃터리드를 제외한 나머지 전체 구조를 봉지하는 몰드바디가 구비됨을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the above object, the present invention provides a plurality of outlets, an inner lead extending on the same plane as the outer lead, a die pad located inside the inner lead and downset compared to the inner lead, A chip having a size within an area range formed by a virtual line bonded to the upper surface of the die pad and spaced a predetermined distance from the line connecting the inner lead, an adhesive applied to the upper surface of the die pad to bond the chip to the die pad, A semiconductor package is provided comprising a plurality of conductive members electrically connecting the bonding pads and the inner leads of the chip to each other, and a mold body for encapsulating the entire structure except for the outer lead.

상기한 목적을 달성하기 위한 본 발명의 다른 형태에 따르면, 본 발명은 리드프레임의 인너리드 선단을 잇는 선으로부터 내측으로 일정거리 이격된 가상의 선을 설정하는 단계와, 상기 다이패드 상면에 접착제를 도포하는 단계와, 가상의 선이 이루는 면적 이하의 크기를 갖는 칩을 상기 리드프레임의 다이패드 상면에 본딩하는 단계와, 상기 칩의 본딩패드와 리드프레임의 인너리드가 각각 전기적으로 연결되도록 전도성부재를 연결하는 단계와, 상기 아웃터리드를 제외한 나머지 전체 구조를 에폭시 몰딩 콤파운드를 이용하여 봉지하는 단계를 순차적으로 수행하여서 됨을 특징으로 하는 반도체 패키지 제조방법이 제공된다.According to another aspect of the present invention for achieving the above object, the present invention comprises the steps of setting an imaginary line spaced a predetermined distance inward from the line connecting the inner lead end of the lead frame, and the adhesive on the upper surface of the die pad Applying, bonding a chip having a size less than or equal to an area formed by an imaginary line to the upper surface of the die pad of the lead frame, and electrically connecting the bonding pad of the chip to the inner lead of the lead frame, respectively. A method of manufacturing a semiconductor package is provided by sequentially connecting and encapsulating the entire structure other than the outer structure using an epoxy molding compound.

이하, 본 발명의 각 실시예들을 첨부도면 도 5 내지 도 11을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, each embodiment of the present invention will be described in detail with reference to FIGS. 5 to 11.

본 발명은 복수개의 아웃터리드(1)와, 상기 아웃터리드(1)와 동일 평면상에서 연장형성된 인너리드(2)와, 상기 인너리드(2) 내측에 위치하며 상기 인너리드(2)에 비해 다운셋된 다이패드(3)와, 상기 다이패드(3) 상면에 본딩되며 인너리드(2)의 선단을 잇는 선으로부터 일정거리 이격된 가상의 선이 이루는 면적 범위 내의 사이즈를 갖는 칩(4)과, 상기 다이패드(3)에 칩(4)이 결합되도록 하는 접착제(5)와, 상기 칩(4)의 본딩패드(4a)들과 인너리드(2)들을 전기적으로 각각 연결하는 복수개의 전도성부재(6)와, 상기 아웃터리드(1)를 제외한 나머지 전체 구조를 봉지하는 몰드바디(7)가 구비되어 구성된다.According to the present invention, a plurality of outer leads 1, an inner lead 2 extending in the same plane as the outer lead 1, and located inside the inner lead 2 are lower than the inner lead 2; A chip 4 having a size within an area range formed by a set die pad 3 and a virtual line bonded to an upper surface of the die pad 3 and spaced apart from a line connecting an end of the inner lead 2 by a predetermined distance; And a plurality of conductive members electrically connecting the adhesive 5 to bond the chip 4 to the die pad 3 and the bonding pads 4a and the inner lead 2 of the chip 4, respectively. (6) and the mold body 7 which seals the whole structure except the said outward 1 is provided.

이와 같이 구성된 본 발명의 반도체 패키지 제조를 위한 패키징 과정은 다음과 같이 수행된다.The packaging process for manufacturing the semiconductor package of the present invention configured as described above is performed as follows.

먼저, 웨이퍼에 집적회로를 형성하는 FAB공정을 완료한 후, 웨이퍼 상에 만들어진 각 칩(4)을 서로 분리시키는 다이싱(Dicing)이 끝나면, 분리된 각 칩(4)을 리드 프레임(Lead Frame)의 다이패드(3)에 본딩시키게 된다.First, after completing the FAB process of forming the integrated circuit on the wafer, and after dicing dividing each chip 4 formed on the wafer from each other, the separated chips 4 are placed in a lead frame. Is bonded to the die pad 3).

이때, 칩(4)의 크기는 최대로 크게 만들더라도 인너리드(2)의 선단을 잇는 선으로부터 일정거리(예; 5 MIL) 이상 떨어진 선이 이루는 면적 이하의 사이즈를 갖고 있어야 한다.At this time, even if the size of the chip 4 is maximized, the chip 4 should have a size less than or equal to an area formed by a line separated by a predetermined distance (for example, 5 MIL) or more from the line connecting the tip of the inner lead 2.

즉, 칩(4)의 크기는 가변될 수 있기는 하나, 오직 인너리드(2)의 선단을 잇는 선으로부터 일정거리(예; 5 MIL) 이상 떨어진 선 내측에 위치하도록 칩(4) 사이즈가 작아지는 방향으로만 가변이 가능하다.That is, the size of the chip 4 may vary, but the size of the chip 4 is small so that the chip 4 is located inside the line that is separated by a predetermined distance (for example, 5 MIL) from the line connecting the tip of the inner lead 2. It can only be changed in the losing direction.

한편, 칩 본딩이 완료된 후에는 칩(4)에 형성된 외부접속단자인 본딩 패드(Bonding pad)와 리드 프레임의 인너리드(2)(Inner Lead portion)를 전기적으로 접속시키는 와이어 본딩(Wire Bonding)을 순차적으로 수행한 후, 상기 칩(4) 및 본딩된 전도성부재인 와이어를 에폭시 몰딩 콤파운드로 감싸 보호하기 위한 봉지(encapsulation)공정을 수행하게 된다.On the other hand, after chip bonding is completed, wire bonding for electrically connecting a bonding pad, which is an external connection terminal formed on the chip 4, and an inner lead portion 2 of the lead frame, may be performed. After sequentially performing, the encapsulation process for encapsulating and protecting the chip 4 and the wire, which is a bonded conductive member, with an epoxy molding compound is performed.

또한, 봉지공정을 수행한 후에는 리드 프레임의 써포트 바(Support Bar) 및 댐 바(Dam Bar)를 자르는 트리밍(Trimming) 및, 아웃터리드(1)를 소정의 형상으로 성형하는 포밍(Forming)을 차례로 수행하게 된다.In addition, after the encapsulation process, trimming to cut the support bar and the dam bar of the lead frame, and forming the outer 1 to form a predetermined shape are performed. In turn.

트리밍 및 포밍 완료 후에는 최종적으로 솔더링(Soldering)을 실시하므로써 반도체소자 패키지 공정을 완료하게 된다.After trimming and forming, the soldering process is finally performed to complete the semiconductor device package process.

도 5는 본 발명에 따른 반도체 패키지의 제1실시예를 나타낸 종단면도이고, 도 6은 도 5의 Ⅱ-Ⅱ선을 나타낸 횡단면도로서, 도 5 및 도 6에 나타낸 반도체 패키지는 본 발명에 따른 반도체 패키지의 제1실시예를 나타낸 것으로서, 칩(4)의 사이즈가 다이패드보다 작은 경우이다.5 is a longitudinal cross-sectional view showing a first embodiment of a semiconductor package according to the present invention, Figure 6 is a cross-sectional view showing a line II-II of Figure 5, the semiconductor package shown in Figures 5 and 6 is a semiconductor according to the present invention As shown in the first embodiment of the package, the size of the chip 4 is smaller than the die pad.

그리고, 도 7은 본 발명에 따른 반도체 패키지의 제2실시예를 나타낸 종단면도이고, 도 8은 도 7의 Ⅲ-Ⅲ선을 나타낸 횡단면도로서, 이 경우는 칩(4)의 사이즈가 다이패드(3) 보다 큰 경우로서, 칩(4)의 가로 및 세로 사이즈는 다이패드(3)의 가로 및 세로방향 양쪽에 대해 모두 다이패드(3)보다 큰 사이즈를 갖게 된다.7 is a longitudinal cross-sectional view showing a second embodiment of the semiconductor package according to the present invention, and FIG. 8 is a cross-sectional view showing the III-III line of FIG. 7, in which case the size of the chip 4 is a die pad ( 3) As a larger case, the horizontal and vertical sizes of the chip 4 have a larger size than the die pad 3 for both the horizontal and vertical directions of the die pad 3.

도 9는 본 발명의 반도체 패키지의 제3실시예를 나타낸 종단면도이고, 도 10은 도 9의 Ⅳ-Ⅳ선을 나타낸 종단면도이며, 도 11은 도 10의 Ⅴ-Ⅴ선을 나타낸 횡단면도로서, 이 경우의 반도체 패키지는 칩(4)의 사이즈가 가로 및 세로방향 중 어느 한방향에 대해서만 다이패드(3)보다 사이즈가 큰 경우이다.9 is a longitudinal cross-sectional view illustrating a third embodiment of the semiconductor package of the present invention, FIG. 10 is a vertical cross-sectional view showing a line IV-IV of FIG. 9, and FIG. 11 is a cross-sectional view showing a V-V line of FIG. 10. The semiconductor package in this case is a case where the size of the chip 4 is larger than the die pad 3 only in one of the transverse and longitudinal directions.

상기한 세 가지 실시예의 반도체 패키지 모두 칩(4)의 사이즈가 인너리드(2)의 선단을 잇는 선으로부터 일정거리 이격된 선이 이루는 면적의 크기 이하인 구조이므로 패키징 작업이 가능하다.Since the semiconductor package of the above three embodiments has a structure in which the size of the chip 4 is smaller than the size of the area formed by the line spaced apart from the line connecting the tip of the inner lead 2 by a predetermined distance, packaging can be performed.

따라서, 본 발명의 반도체 패키지는 리드프레임의 다이패드(3) 사이즈와 무관하게 인너리드(2) 선단이 이루는 선으로부터 일정거리 이격된 임의의 선이 이루는 면적 이하의 사이즈를 갖는 칩(4)은 전부 적용 가능하게 된다.Therefore, in the semiconductor package of the present invention, regardless of the size of the die pad 3 of the lead frame, the chip 4 having a size less than or equal to an area formed by any line spaced apart from the line formed by the tip of the inner lead 2 may be formed. All of them become applicable.

이상에서와 같이, 본 발명의 반도체 패키지는 리드프레임의 다이패드(3) 사이즈와 무관하게 인너리드(2) 선단이 이루는 선으로부터 일정거리 이격된 임의의 선이 이루는 면적 이하의 사이즈를 갖는 칩(4)은 전부 적용 가능하도록 하므로써, 리드프레임의 범용성을 향상시켜 리드프레임 제조 비용을 절감할 수 있게 된다.As described above, the semiconductor package of the present invention is a chip having a size less than or equal to an area formed by an arbitrary line spaced a certain distance from the line formed by the tip of the inner lead 2 regardless of the size of the die pad 3 of the lead frame. 4) can be applied to all of them, thereby improving the versatility of the lead frame, thereby reducing the lead frame manufacturing cost.

또한, 리드프레임의 다이패드(3)의 두께를 인너리드(2) 등의 두께와 동일하게 할 수 있으므로 다이패드(3)를 별도의 제작하지 않아도 된다.In addition, since the thickness of the die pad 3 of the lead frame can be the same as the thickness of the inner lead 2 or the like, the die pad 3 does not need to be manufactured separately.

특히, 라지칩(4)일 경우, 리드프레임의 다이패드(3)보다 칩(4)이 더 크므로 수분흡수시 발생하는 크랙 및 계면분리 현상에 대한 저항력이 다이패드(3)가 칩(4)보다 더 큰 경우에 비해 훨씬 증가하게 된다.Particularly, in the case of the large chip 4, since the chip 4 is larger than the die pad 3 of the lead frame, the die pad 3 has a resistance against cracks and interfacial separation occurring when water is absorbed. Larger than).

Claims (2)

복수개의 아웃터리드와,A plurality of outliers, 상기 아웃터리드와 동일 평면상에 연장형성된 인너리드와,An inner lead extending on the same plane as the outer lead, 상기 인너리드 내측에 위치함 상기 인너리드에 비해 다운셋된 다이패드와,Located inside the inner lead die pad downset compared to the inner lead, 상기 다이패드 상면에 본딩되며 인너리드의 선단을 잇는 선으로부터 내측으로 일정거리 이격된 가상의 선이 이루는 면적 범위 내의 사이즈를 갖는 칩과,A chip bonded to an upper surface of the die pad and having a size within an area range formed by a virtual line spaced inward from a line connecting an end of an inner lead by a predetermined distance; 상기 다이패드에 칩이 결합되도록 다이패드 상면에 도포되는 접착제와,An adhesive applied to an upper surface of the die pad to bond the chip to the die pad; 상기 칩의 본딩패드들과 인너리드들을 전기적으로 각각 연결하는 복수개의 전도성부재와,A plurality of conductive members electrically connecting the bonding pads and the inner leads of the chip to each other; 상기 아웃터리드를 제외한 나머지 전체 구조를 봉지하는 몰드바디가 구비됨을 특징으로 하는 반도체 패키지.A semiconductor package comprising a mold body for encapsulating the entire structure except for the outer lead. 리드프레임의 인너리드 선단을 잇는 선으로부터 내측으로 일정거리 이격된가상의 선을 설정하는 단계와,Setting up a virtual line spaced inward from the line connecting the inner lead end of the lead frame; 상기 다이패드 상면에 접착제를 도포하는 단계와,Applying an adhesive to the upper surface of the die pad; 가상의 선이 이루는 면적 이하의 크기를 갖는 칩을 상기 리드프레임의 다이패드 상면에 본딩하는 단계와,Bonding a chip having a size less than or equal to an area formed by an imaginary line to an upper surface of the die pad of the lead frame; 상기 칩의 본딩패드와 리드프레임의 인너리드가 각각 전기적으로 연결되도록 전도성부재를 연결하는 단계와,Connecting a conductive member to electrically connect the bonding pad of the chip and the inner lead of the lead frame, respectively; 상기 아웃터리드를 제외한 나머지 전체 구조를 에폭시 몰딩 콤파운드를 이용하여 봉지하는 단계;를 순차적으로 수행하여서 됨을 특징으로 하는 반도체 패키지 제조방법.And encapsulating the entire structure other than the outer structure by using an epoxy molding compound.
KR1019970067041A 1997-12-09 1997-12-09 semiconductor package and method for fabricating the same KR100268922B1 (en)

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Citations (1)

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Publication number Priority date Publication date Assignee Title
JPH05211271A (en) * 1992-01-30 1993-08-20 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211271A (en) * 1992-01-30 1993-08-20 Nec Corp Semiconductor device

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