JPS57208162A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS57208162A
JPS57208162A JP56094247A JP9424781A JPS57208162A JP S57208162 A JPS57208162 A JP S57208162A JP 56094247 A JP56094247 A JP 56094247A JP 9424781 A JP9424781 A JP 9424781A JP S57208162 A JPS57208162 A JP S57208162A
Authority
JP
Japan
Prior art keywords
section
film
protective film
layer structure
active element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56094247A
Other languages
Japanese (ja)
Inventor
Masaharu Noyori
Shuji Kondo
Tsuyoshi Higasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP56094247A priority Critical patent/JPS57208162A/en
Publication of JPS57208162A publication Critical patent/JPS57208162A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To improve the reliability of a semiconductor integrated circuit by employing different number of layers of surface protective films, thickness or material different to each other in response to a circuit element section and a wiring section. CONSTITUTION:In a semiconductor chip 1 having a power source pad 3, a grounding pad 4, metal wiring patterns 5, 6, an active element section 7 made of n-channel MOSFET, the surface protective film of the active element section 7 is formed in a two-layer structure of an SiO2 film 8 containing phosphorus and an Si3N4 film 1, and the surface protective film of the other part is formed on an Si3N4 film 2. The influence of Na<+> ions to the active element is eliminated, and invasion of water content is prevented by the Si3N4 film. An n-channel MOSFET and a bipolar transistor are formed on the same chip, or a protective film of two layer structure is formed in the n-channel MOS section even in a C-MOSFET, and a protective film of one-layer structure may be formed at the other section.
JP56094247A 1981-06-17 1981-06-17 Semiconductor integrated circuit Pending JPS57208162A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56094247A JPS57208162A (en) 1981-06-17 1981-06-17 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56094247A JPS57208162A (en) 1981-06-17 1981-06-17 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS57208162A true JPS57208162A (en) 1982-12-21

Family

ID=14104969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56094247A Pending JPS57208162A (en) 1981-06-17 1981-06-17 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS57208162A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065222A (en) * 1987-11-11 1991-11-12 Seiko Instruments Inc. Semiconductor device having two-layered passivation film
US5070386A (en) * 1989-08-09 1991-12-03 Seiko Instruments Inc. Passivation layer structure with through-holes for semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5726456A (en) * 1980-07-23 1982-02-12 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5726456A (en) * 1980-07-23 1982-02-12 Hitachi Ltd Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5065222A (en) * 1987-11-11 1991-11-12 Seiko Instruments Inc. Semiconductor device having two-layered passivation film
US5070386A (en) * 1989-08-09 1991-12-03 Seiko Instruments Inc. Passivation layer structure with through-holes for semiconductor device

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