JP2001358169A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent upper layer pads from peeling off or a layer insulation film, which lies under the pads form cracks against stresses in probing or wire bonding for improving the reliability of a semiconductor device. SOLUTION: A lower layer conducive pad 2 is formed n a layer insulation film 1, an upper layer conductive pad 4 is formed via a layer insulation film 3 on the pad 2, the upper and lower layer conductive pads are connected via a plurality of conductive plugs 5. The plugs 5 are disposed alternately with minimum or near minimum spacing, according to the design standards so as not to array in line, in a direction perpendicular to the pressure-applying direction in probing/wire bonding. Consequently, such a constitution disperses stresses in probing or wire bonding to avoid cracks, without sacrificing the adhesion of the pads.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having conductive pads which are stacked so as to overlap with each other and connected to each other by a conductive plug.

[0002]

2. Description of the Related Art In a semiconductor device using a multi-layer wiring, a conductive plug formed by embedding a conductor such as a refractory metal in an opened via hole is used. In a semiconductor device using such a conductive plug, a pad having a multilayer structure in which conductive pads of two or more layers above and below are connected by a plurality of conductive plugs is used. Normally, the conductive plugs are arranged in a square lattice at or near the minimum interval of the design standard, and are arranged so that the number of plugs is maximized. By thus maximizing the number of plugs, the adhesive strength between the upper and lower conductive pads can be increased, and the upper conductive pads can be prevented from peeling off during wire bonding.

FIG. 3A is a plan view showing a conventional pad structure, and FIG. 3B is a cross-sectional view taken along the line AA of FIG. 3A. In this case, upper and lower conductive pads are connected by a conductive plug. Here, a plan view of FIG.
In FIG. 5, the conductive plug 5 is drawn so as not to be actually visible due to the conductive pad 4, but to be visible for convenience of explanation. A lower conductive pad 2 is formed on interlayer insulating film 1, and an upper conductive pad 4 is sandwiched between interlayer insulating films 3.
Are formed. A wiring 2a connected to an internal circuit is drawn from the lower conductive pad 2. The lower conductive pad 2 and the upper conductive pad 4 are connected by a plurality of conductive plugs 5. Here, the conductive plugs 5 are arranged over the entire surface of the conductive pad in a square lattice at a minimum spacing or a spacing close to the design standard.

The conductive pads 2 and 4 are formed of an alloy containing aluminum or copper as a main component. The conductive plug 5 is formed of a high melting point metal such as tungsten or an alloy mainly composed of aluminum, copper, or the like as the conductive pads 2 and 4. The interlayer insulating films 1 and 3 are formed from a silicon oxide film or the like by a plasma CVD method. The whole is covered with the passivation film 6, and only the upper part of the pad is opened. The illustration of the structure below the interlayer insulating film 1 is omitted. A technique of arranging conductive pads in multiple layers and connecting them with a conductive plug is known, for example, from JP-A-2000-114309.

After the completion of the manufacturing process in the wafer state, the pads are probed by a probe for testing. After being separated into individual chips and die-bonded on the islands, wires are bonded on the pads. In probing, ultrasonic vibration is applied to the tool during wire bonding performed obliquely from above the pad. Thus, in the pad structure of FIG. 3, due to stress at the time of probing or wire bonding,
Cracks tend to occur below the pad. FIG. 4 illustrates a state in which a crack 9 is formed below a stress-applied portion of the conductive pad 4 as a result of performing probing or wire bonding on the pad of FIG. In FIG. 4, the directions in which pressure is applied during probing and wire bonding are indicated by arrows. To solve this problem, pad structures as shown in FIGS. 5 and 6 have been proposed. 5 and 6 show a conventional pad structure devised to prevent the occurrence of cracks. The difference from the structure of FIG. 3 is that the lower conductive pad and the conductive plug do not exist below the stress applying portion of the upper conductive pad 4 and are located near the lead-out wiring 7a or the periphery of the upper conductive pad. Only the lower conductive pad 7 and the conductive plug 8 are arranged.

[0006]

The pad structure shown in FIG.
Although the upper layer pad has high resistance to peeling in the wire bonding step, cracks are likely to occur in the interlayer insulating film below the pad during probing or wire bonding. On the other hand, the pad structure shown in FIGS. 5 and 6 can prevent cracks at the time of probing or wire bonding, but has a low adhesive strength for connecting the upper and lower conductive pads. The conductive pad may peel off. In addition,
In a pad structure including only one conductive pad, the strength of the conductive pad against peeling is not sufficient.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and it is an object of the present invention to maintain high resistance to peeling of an upper layer pad in a wire bonding step and to perform probing and wire bonding. Sometimes, cracks are less likely to occur in the interlayer insulating film below the pad.

[0008]

According to the present invention, in order to attain the above object, the uppermost conductive pad and the lower conductive pad are laminated via an interlayer insulating film, and both conductive pads are stacked. A semiconductor device in which conductive pads are connected by a plurality of conductive plugs penetrating the interlayer insulating film, wherein the conductive plugs are linear in a direction perpendicular to a direction in which pressure applied to the pads is applied. A semiconductor device, wherein the semiconductor device is arranged so as not to be arranged in a shape.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG.
FIG. 1A is a plan view illustrating a pad structure according to a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line AA of FIG. 1A. In FIG. 1, the same parts as those of the conventional example shown in FIG. 3 are denoted by the same reference numerals, and duplicate description will be omitted. The difference between the present embodiment and the conventional example shown in FIG. 3 is that the conductive plugs 5 are not arranged in a regular square lattice array but are alternately arranged. That is, in this embodiment, the conductive plugs 5 are arranged so as not to be linearly aligned in the direction perpendicular to the pressure application direction during probing / wire bonding.

Next, a method of manufacturing the pad of the present invention will be described. After an interlayer insulating film 1 is formed on a semiconductor substrate (not shown), a metal film (aluminum alloy or copper alloy) serving as a lower conductive pad is formed to a thickness of 0.5 to 1.0 μm by a sputtering method or the like. Deposits on the entire surface. Next, the deposited metal film is processed by photolithography and etching to form the conductive pad 2 and the wiring 2a connected thereto. Next, an interlayer insulating film 3 (silicon oxide film) is deposited to a thickness of about 1.3 μm on the entire surface by a plasma CVD method or the like, and the surface is flattened by CMP to a thickness of about 1 μm on the pad. Thereafter, a via hole for forming a conductive plug is formed by photolithography and etching.

A high melting point metal (tungsten) or the like is buried in the via hole by a CVD method or the like to form a conductive plug 5 (about 0.5 × 0.5 μm ² ). Next, a metal film (such as an aluminum alloy or a copper alloy) serving as an upper conductive pad is deposited on the entire surface to a thickness of about 0.5 to 1 μm by sputtering or the like, and is processed by photolithography and etching. Pad 4
(About 100 × 100 μm ² ). Next, CV
A passivation film 6 made of a silicon oxide film, a silicon nitride film, polyimide, or the like is formed on the entire surface by a method D or the like, and only the upper portion of the conductive pad 4 is opened by photolithography and etching.

As described in the above-described conventional example, when pressure is applied to the upper conductive pad in the lateral direction due to probing in a wafer test or wire bonding in an assembling process, the interlayer insulating film 3 interposed therebetween. Is subjected to mechanical stress and cracks occur. This crack is generated so as to run in the direction perpendicular to the pressure application direction during probing / wire bonding. In some cases, a crack may reach the interlayer insulating film 1 below the conductive pad 2.

In the pad structure of the present invention, since the conductive plugs 5 are not aligned in a direction perpendicular to the pressure application direction,
Cracks running linearly are less likely to occur. In addition, since the upper and lower conductive pads are connected by laying conductive plugs on the entire surface of the pad, it has sufficient strength against peeling of the conductive pad during wire bonding. In this embodiment, the case where the conductive plug 5 is square is described, but the conductive plug 5 may be circular.

FIG. 2A is a plan view showing a pad structure according to a second embodiment of the present invention, and FIG. 2B is a sectional view taken on line AA of FIG. 2A.
It is sectional drawing along the line. In FIG. 2, parts that are the same as the parts of the first embodiment shown in FIG. 1 are given the same reference numerals, and duplicate descriptions will be omitted. The present embodiment differs from the embodiment shown in FIG. 1 in that the conductive plug is rectangular (or elliptical) instead of square (or circular). The gap between the conductive plugs in the pressure application direction is completely sandwiched between the conductive plugs in adjacent rows. By having such a structure, generation of cracks running perpendicular to the pressure application direction at the time of probing / wire bonding is further suppressed. The preferred embodiments have been described above. However, the present invention is not limited to these embodiments, and can be appropriately changed without departing from the gist of the present invention. For example, the shape of the conductive pad may be configured by a combination of a rectangle and a square, or another combination is also possible. Further, in the present invention, the case where the conductive pad has a two-layer structure has been described, but the present invention is also applicable to a three-layer structure.

[0015]

As described above, in the pad structure of the semiconductor device according to the present invention, since the conductive plugs connecting the conductive pads are arranged so as not to be aligned in a straight line, the wire structure can be reduced. It is possible to prevent cracks from occurring in the interlayer insulating film below the conductive pads during probing / wire bonding while maintaining resistance to peeling of the conductive pads during bonding.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view showing a first embodiment of the present invention.

FIG. 2 is a plan view and a sectional view showing a second embodiment of the present invention.

FIG. 3 is a plan view and a cross-sectional view of a first conventional example.

FIGS. 4A and 4B are a plan view and a cross-sectional view illustrating a state of occurrence of cracks in a first conventional example.

FIG. 5 is a plan view and a cross-sectional view of a second conventional example.

FIG. 6 is a plan view and a cross-sectional view of a third conventional example.

[Explanation of symbols]

 1, 3 interlayer insulating film 2, 4 conductive pad 2a wiring 5, 8 conductive plug 6 passivation film 7 lower conductive pad 7a lead-out wiring 9 crack

Claims (8)

[Claims] An uppermost conductive pad and a lower conductive pad are stacked with an interlayer insulating film interposed therebetween, and a plurality of conductive plugs penetrating the interlayer insulating film between both conductive pads. In the semiconductor device being connected, the conductive plugs are alternately arranged. 2. The semiconductor device according to claim 1, wherein the conductive plug is arranged so as not to be linearly aligned in a direction perpendicular to a direction in which a pressure applied to the pad is applied. 3. A conductive pad in the uppermost layer and a conductive pad under the uppermost layer are laminated via an interlayer insulating film, and a plurality of conductive plugs penetrating the interlayer insulating film between both conductive pads. In the semiconductor device being connected, the conductive plugs form gaps between the conductive plugs in rows of the conductive plugs adjacent to each other in a direction perpendicular to a direction in which a pressure applied to the uppermost conductive pad is applied. A semiconductor device, which is arranged so as to close a conductive plug in an adjacent row. 4. The semiconductor device according to claim 1, wherein the conductive plugs are arranged at a minimum interval of a design standard or an interval close thereto. 5. The semiconductor device according to claim 1, wherein the planar shape of the conductive plug is any one of a square, a rectangle, a circle, and an ellipse. 6. The semiconductor device according to claim 1, wherein said conductive plug is uniformly spread over substantially the entire surface of said conductive pad. 7. One or more conductive pads are formed below the lower conductive pad, and the conductive pads are connected by a plurality of conductive plugs. The semiconductor device according to claim 1. 8. The semiconductor device according to claim 1, wherein a surface is covered with a passivation film having an opening on the uppermost conductive pad.