JPH0583180B2 - - Google Patents
Info
- Publication number
- JPH0583180B2 JPH0583180B2 JP62087771A JP8777187A JPH0583180B2 JP H0583180 B2 JPH0583180 B2 JP H0583180B2 JP 62087771 A JP62087771 A JP 62087771A JP 8777187 A JP8777187 A JP 8777187A JP H0583180 B2 JPH0583180 B2 JP H0583180B2
- Authority
- JP
- Japan
- Prior art keywords
- pad electrode
- wiring
- insulating film
- conductive wire
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010410 layer Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 6
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板上に絶縁膜を介して積層
される複数層の配線を有し、その配線に設けられ
るパツド電極と端子導体とが導線によつて接続さ
れる半導体装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention has a plurality of layers of wiring laminated on a semiconductor substrate with an insulating film interposed therebetween, and a pad electrode and a terminal conductor provided on the wiring. The present invention relates to a method of manufacturing a semiconductor device connected by a conductive wire.
多層配線を有し、ワイヤ方式で絶縁基板上に実
装される半導体基板のワイヤボンデイングのため
のパツド電極は、従来最上層の配線の一部に形成
されていた。しかしこのようなパツド電極に導線
をボンデイングした場合、導線とボンデイング部
の下に存在する配線導体膜および酸化物のような
無機絶縁物あるいは有機絶縁物からなる層間絶縁
膜の積層体との弾性率、熱膨張係数の相違によ
り、接合面での剥離が生じやすく、断面の原因と
なるという問題点があつた。
Conventionally, a pad electrode for wire bonding of a semiconductor substrate having multilayer wiring and mounted on an insulating substrate using a wire method has been formed on a part of the uppermost layer wiring. However, when a conductive wire is bonded to such a pad electrode, the elastic modulus of the conductive wire, the wiring conductor film existing under the bonding part, and the laminate of the interlayer insulating film made of an inorganic insulator such as an oxide or an organic insulator is However, due to the difference in thermal expansion coefficients, peeling tends to occur at the joint surface, which causes a problem in cross section.
本発明は、上述の問題点を解決して、端子導体
と接続される導線と半導体基板上の配線に設けら
れたパツド電極と接合面における剥離などによる
断線のおそれのない、信頼性の高い半導体装置の
製造方法を提供することを目的とする。
The present invention solves the above-mentioned problems and provides a highly reliable semiconductor that is free from the risk of disconnection due to peeling or the like at the bonding surface between the conductive wire connected to the terminal conductor and the pad electrode provided on the wiring on the semiconductor substrate. The purpose is to provide a method for manufacturing the device.
この目的は本発明によれば、半導体基板上に絶
縁層を介して形成される第一層目の配線にパツド
電極を設け、次いでそのパツド電極を露出させて
層間絶縁膜を堆積し、上層の配線形成の際に該パ
ツド電極部上に上層の配線金属で積層することを
繰り返し、表面保護膜を積層した後パツド電極に
導線を接続することにより達成される。
According to the present invention, this purpose is achieved by providing a pad electrode on the first layer of wiring formed on the semiconductor substrate via an insulating layer, then exposing the pad electrode, depositing an interlayer insulating film, and depositing an interlayer insulating film on the upper layer. This is achieved by repeatedly laminating an upper layer of wiring metal on the pad electrode portion during wiring formation, and then connecting a conductive wire to the pad electrode after laminating a surface protective film.
本発明においては、半導体基板上に直接絶縁膜
を介して形成されたパツド電極に導線が形成さ
れ、その中間には積層体が介在せず、またパツド
電極は複数の金属層で積層形成される。
In the present invention, a conductive wire is formed on a pad electrode formed directly on a semiconductor substrate via an insulating film, and there is no laminate interposed between them, and the pad electrode is formed by laminating a plurality of metal layers. .
次に本発明の実施例を図面について説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
図は、本発明の一実施例の半導体装置を示す。
シリコン基板１の上面は薄い酸化膜２で覆われ、
この基板１にはバイポーラトランジスタあるいは
MOSFETなどの半導体素子が集積されていて、
その部分は厚い絶縁膜３で覆われている。次に酸
化膜２および絶縁膜３の上にAl膜を蒸着し、パ
ターニングして第一層配線４を形成する。同時に
絶縁膜３の上に延長された配線の端部にパツド電
極５を形成する。続いて酸化膜、塗布膜などの層
間絶縁膜６を被覆し、スルーホール部７およびパ
ツド電極５上の絶縁膜をエツチング除去した後、
第二層配線８を形成するとともに、パツド電極５
上に第二層配線金属で作られた電極９を重ね形成
する。第二層配線８とパツド電極５との接続は第
一層配線４に達するスルーホール部７を介して行
われる。さらに表面にパツシベーシヨン膜１０を
被着し、同様にパツド電極５およびその上に重ね
た電極９を覆う部分を除去する。 The figure shows a semiconductor device according to an embodiment of the present invention.
The upper surface of the silicon substrate 1 is covered with a thin oxide film 2,
This substrate 1 has a bipolar transistor or
Semiconductor elements such as MOSFETs are integrated,
That part is covered with a thick insulating film 3. Next, an Al film is deposited on the oxide film 2 and the insulating film 3 and patterned to form the first layer wiring 4. At the same time, a pad electrode 5 is formed at the end of the wiring extending on the insulating film 3. Subsequently, an interlayer insulating film 6 such as an oxide film or a coating film is coated, and the insulating film on the through hole portion 7 and pad electrode 5 is removed by etching.
While forming the second layer wiring 8, the pad electrode 5
An electrode 9 made of a second layer wiring metal is formed on top. The connection between the second layer wiring 8 and the pad electrode 5 is made through a through hole portion 7 that reaches the first layer wiring 4. Furthermore, a passivation film 10 is applied to the surface, and the portion covering the pad electrode 5 and the electrode 9 superimposed thereon is similarly removed.
図に示したような半導体装置の実装は、図に示
していない絶縁基板上にろう付けなどにより固着
したのち、パツド電極５と絶縁基板上の端子導体
とを導線でボンデイングすることによつて接続す
ることにより行う。 The semiconductor device shown in the figure is mounted by fixing it on an insulating substrate (not shown) by brazing or the like, and then connecting the pad electrode 5 and the terminal conductor on the insulating substrate by bonding with a conductive wire. Do by doing.
本発明によれば、ワイヤ方式で実装される多層
配線構造の半導体装置のパツド電極を第一層目の
配線に設けることにより、パツド電極にボンデイ
ングされる接続導線の下に弾性率、熱膨張係数の
異なる積層体がなくなるとともに、パツド電極が
複数層積層したもので形成されるため導線接合面
に生ずる応力が小さくなり、接合面における剥離
が阻止されるので、ICチツプなどを実装した半
導体装置の信頼性を向上させることができる。
According to the present invention, by providing a pad electrode in the first layer of wiring of a semiconductor device with a multilayer wiring structure mounted by a wire method, the elastic modulus and thermal expansion coefficient are In addition to eliminating the need for a laminate with different laminates, the stress generated at the conductor bonding surface is reduced because the pad electrode is formed by laminating multiple layers, and peeling at the bonding surface is prevented. Reliability can be improved.
図は、本発明の一実施例による半導体装置の要
部断面図である。
１……シリコン基板、２……酸化膜、３……絶
縁膜、４……第一層配線、５……パツド電極、６
……層間絶縁膜、７……スルーホール部、８……
第二層配線、９……電極、１０……パツシベーシ
ヨン膜。
The figure is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Oxide film, 3... Insulating film, 4... First layer wiring, 5... Pad electrode, 6
...Interlayer insulating film, 7...Through hole part, 8...
Second layer wiring, 9...electrode, 10...passivation film.
Claims (1)
数層の配線を有し、該配線に設けられるパツド電
極と端子導体とが導線によつて接続される半導体
装置の製造方法において、半導体基板上に絶縁膜
を介して形成される第一層目の配線にパツド電極
を設け、次いで該パツド電極を露出させて層間絶
縁膜を堆積し、上層の配線形成の際に該パツド電
極部上に、該上層の配線金属で積層することを繰
り返し、表面保護膜を積層した後、パツド電極に
導線を接続することを特徴とする半導体装置の製
造方法。1. In a method for manufacturing a semiconductor device having multiple layers of wiring stacked on a semiconductor substrate with an insulating film interposed therebetween, a pad electrode provided on the wiring and a terminal conductor are connected by a conductive wire. A pad electrode is provided on the first layer of wiring formed through an insulating film, and then an interlayer insulating film is deposited with the pad electrode exposed, and when forming the upper layer wiring, on the pad electrode part, A method of manufacturing a semiconductor device, which comprises repeating the process of laminating the upper layer of wiring metal, and after laminating a surface protective film, connecting a conductive wire to a pad electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8777187A JPS63252433A (en) | 1987-04-08 | 1987-04-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8777187A JPS63252433A (en) | 1987-04-08 | 1987-04-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63252433A JPS63252433A (en) | 1988-10-19 |
| JPH0583180B2 true JPH0583180B2 (en) | 1993-11-25 |
Family
ID=13924234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8777187A Granted JPS63252433A (en) | 1987-04-08 | 1987-04-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63252433A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6050949A (en) * | 1983-08-30 | 1985-03-22 | Seiko Epson Corp | Semiconductor device |
| JPS6091660A (en) * | 1983-10-25 | 1985-05-23 | Nec Corp | Manufacture of semiconductor device |
-
1987
- 1987-04-08 JP JP8777187A patent/JPS63252433A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6050949A (en) * | 1983-08-30 | 1985-03-22 | Seiko Epson Corp | Semiconductor device |
| JPS6091660A (en) * | 1983-10-25 | 1985-05-23 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63252433A (en) | 1988-10-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW511200B (en) | Semiconductor device and manufacturing method thereof | |
| JPS63283040A (en) | Semiconductor device | |
| JPH02272737A (en) | Projecting electrode structure of semiconductor and formation of projecting electrode | |
| JP2772157B2 (en) | Semiconductor device wiring method | |
| JP2001358169A (en) | Semiconductor device | |
| JP3106493B2 (en) | Semiconductor device | |
| JPH0714028B2 (en) | Method for manufacturing three-dimensional semiconductor device | |
| JPH01218042A (en) | Semiconductor device | |
| JPH0583180B2 (en) | ||
| KR100497193B1 (en) | Bonding pad for semiconductor device and formation method of the same | |
| US20060170087A1 (en) | Semiconductor device | |
| JPS62237748A (en) | Manufacture of semiconductor device | |
| JP5273920B2 (en) | Semiconductor device | |
| JPS6359535B2 (en) | ||
| JPH0456237A (en) | Semiconductor device | |
| JPS63308924A (en) | Semiconductor device | |
| JPH0666407B2 (en) | Method for manufacturing three-dimensional semiconductor device | |
| JPH0621061A (en) | Semiconductor device | |
| JPH03112135A (en) | Semiconductor device and manufacture thereof | |
| JPH05218036A (en) | Semiconductor device | |
| JPS63252445A (en) | Manufacture of semiconductor device | |
| JPH02183536A (en) | Semiconductor device | |
| JPH02161755A (en) | Semiconductor device | |
| JP3565872B2 (en) | Thin film multilayer wiring board | |
| JPS62234350A (en) | Manufacture of semiconductor device |