JP2772157B2 - Semiconductor device wiring method - Google Patents

Semiconductor device wiring method

Info

Publication number
JP2772157B2
JP2772157B2 JP12382391A JP12382391A JP2772157B2 JP 2772157 B2 JP2772157 B2 JP 2772157B2 JP 12382391 A JP12382391 A JP 12382391A JP 12382391 A JP12382391 A JP 12382391A JP 2772157 B2 JP2772157 B2 JP 2772157B2
Authority
JP
Japan
Prior art keywords
wiring
chip
substrate
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP12382391A
Other languages
Japanese (ja)
Other versions
JPH04350951A (en
Inventor
直樹 柴山
能克 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Heavy Industries Ltd
Original Assignee
Mitsubishi Heavy Industries Ltd
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Filing date
Publication date
Application filed by Mitsubishi Heavy Industries Ltd filed Critical Mitsubishi Heavy Industries Ltd
Priority to JP12382391A priority Critical patent/JP2772157B2/en
Publication of JPH04350951A publication Critical patent/JPH04350951A/en
Application granted granted Critical
Publication of JP2772157B2 publication Critical patent/JP2772157B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置の配線方法に
関し、特に圧力センサ，赤外線センサなどの各種センサ
への配線にも適用できるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring method for a semiconductor device, and more particularly to a wiring method for various sensors such as a pressure sensor and an infrared sensor.

【０００２】[0002]

【従来の技術】図６は、従来のワイヤボンディング法を
用いた半導体装置を示す。2. Description of the Related Art FIG. 6 shows a semiconductor device using a conventional wire bonding method.

【０００３】図中の１は、基板である。この基板１の所
定の位置には裸ＩＣチップ２が搭載され、前記チップ２
の上部周縁には複数の第１電極３が設けられている。前
記チップ２の周囲の基板１上には、先端部に第２電極４
が形成された複数の導体パタ−ン５が形成されている。
前記チップ２の第１電極３と導体パタ−ン４の第２電極
４は、ＡＩやＡｕなどからなるボンディングワイヤ６に
より電気的に接続されている。[0003] Reference numeral 1 in the figure denotes a substrate. A bare IC chip 2 is mounted on a predetermined position of the substrate 1, and the chip 2
Are provided with a plurality of first electrodes 3 on the upper periphery. On the substrate 1 around the chip 2, a second electrode 4
Are formed, and a plurality of conductor patterns 5 are formed.
The first electrode 3 of the chip 2 and the second electrode 4 of the conductor pattern 4 are electrically connected by a bonding wire 6 made of AI, Au or the like.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、従来技
術によれば、以下に述べる問題点を有する。However, according to the prior art, there are the following problems.

【０００５】(1) 作業性が悪い。即ち、配線必要箇所を
１箇所ずつボンディングワイヤ６で配線する必要があ
り、１ケの装置で複雑な裸ＩＣチップの同時配線を行う
のは困難である。 (2) 耐振性が悪い。即ち、配線したボンディングワイヤ
６は、高周波の振動に弱く、疲労破壊しやすい。(1) Poor workability. That is, it is necessary to wire the necessary wiring portions one by one with the bonding wires 6, and it is difficult to perform complicated simultaneous wiring of the naked IC chip with one device. (2) Poor vibration resistance. That is, the wired bonding wire 6 is vulnerable to high-frequency vibration and is easily broken by fatigue.

【０００６】(3) 信頼性が低い。即ち、１つの裸ＩＣチ
ップ２から例えば０．１ｃｍ2 あたり４０本以上のボン
ディングワイヤを配線する際、ワイヤ間の接触が起こり
易い。また、ワイヤボンディング作業中、裸ＩＣチップ
２を破損することがある。これらの原因からＩＣの機能
に不具合が生じ、ワイヤボンディング法はＩＣの信頼性
を低下させる可能性が高い。(3) Low reliability. That is, for example, 0.1 cm 2 from one bare IC chip 2 When wiring 40 or more bonding wires per wire, contact between the wires is likely to occur. Further, during the wire bonding operation, the bare IC chip 2 may be damaged. Due to these causes, a malfunction occurs in the function of the IC, and the wire bonding method has a high possibility of lowering the reliability of the IC.

【０００７】(4) 小型化が困難である。即ち、図６のよ
うに裸ＩＣチップ２と基板１上の第１電極３の間にワア
イヤボンディングのためのスペ−スが必要であり、小型
化が困難である。また、ワイヤボンディング法は裸ＩＣ
チップの第１電極３から一度上にボンディングワイヤ６
を引き上げるため、裸ＩＣチップ２の厚さの１．５〜５
倍程度の高さが必要であり、小型化が困難である。(4) It is difficult to reduce the size. That is, as shown in FIG. 6, a space for wire bonding is required between the bare IC chip 2 and the first electrode 3 on the substrate 1, and it is difficult to reduce the size. The wire bonding method uses bare IC
Bonding wire 6 once above first electrode 3 of the chip
1.5 to 5 times the thickness of the bare IC chip 2
About twice the height is required, and miniaturization is difficult.

【０００８】本発明は上記事情に鑑みてなされてもの
で、裸ＩＣチップ上の第１電極と基板上の第２電極との
配線形成をメタライズで行なうことにより、従来と比べ
作業性に優れ、耐震性に優れ、信頼性が高く、かつ小形
化が可能な半導体装置の配線方法を提供することを目的
とする。Since the present invention has been made in view of the above circumstances, by forming the wiring between the first electrode on the bare IC chip and the second electrode on the substrate by metallization, the workability is superior to that of the prior art. An object of the present invention is to provide a semiconductor device wiring method which is excellent in earthquake resistance, has high reliability, and can be downsized.

【０００９】[0009]

【課題を解決するための手段】本発明は、基板上に搭載
され，上部に複数の第１電極が形成されるとともに端部
に基板主面側に向って末広がりの傾斜部を有した裸ＩＣ
チップと、前記裸ＩＣチップの周辺に形成され先端部が
複数の第２電極になっている導体パターンと、前記第１
電極と第２電極とを電気的に接続する接続手段とを具備
する半導体装置の配線方法において、前記接続手段を前
記基板及びＩＣチップ上にメタライズを行なうことによ
り形成することを特徴とする半導体装置の配線方法であ
る。SUMMARY OF THE INVENTION The present invention relates to a bare IC mounted on a substrate, having a plurality of first electrodes formed on the upper portion, and having an inclined portion diverging toward the main surface of the substrate at the end.
A chip, a conductor pattern formed around the bare IC chip and having a plurality of second electrodes at a tip end thereof;
In a wiring method for a semiconductor device comprising a connection means for electrically connecting an electrode and a second electrode, the connection means is formed by metallizing the substrate and the IC chip. Wiring method.

【００１０】本発明において、前記傾斜部はＩＣチップ
をウェハからカットする際に斜めにカットすることによ
り形成してもよいし、図３のようにセラミックブロック
をＩＣチップの側面に接合させることにより形成しても
よい。In the present invention, the inclined portion may be formed by diagonally cutting the IC chip from the wafer, or by joining a ceramic block to the side surface of the IC chip as shown in FIG. It may be formed.

【００１１】本発明において、メタライズ（あるいはメ
タライジング：Ｍetallizing）とは非金属表面に金属層
を形成させ、非金属の外観を金属化させることを意味す
る。金属被膜を作る方法としては、溶射法，真空蒸着
法，無電界メッキ法等が挙げられる。In the present invention, the term “metallizing” means that a metal layer is formed on the surface of a nonmetal and the appearance of the nonmetal is metallized. Examples of a method for forming a metal film include a thermal spraying method, a vacuum evaporation method, and an electroless plating method.

【００１２】[0012]

【作用】本発明によれば、ＩＣチップ上の第１電極と基
板上の第２電極との配線をメタライズで行なうため、以
下に述べる効果を有する。According to the present invention, since the wiring between the first electrode on the IC chip and the second electrode on the substrate is performed by metallization , the following effects are obtained.

【００１３】(1) 作業性が良い。即ち、従来、配線必要
箇所を１箇所ずつワイヤボンディング（配線）していた
が、本発明の場合１枚の基板で必要な配線を一度に行な
うことができる。また、蒸着装置等のメタライズ装置が
大きければ、複数の基板を一度に配線することができ
る。 (2) 耐振性が良い。即ち、メタライズによる配線のパタ
−ンは基板やＩＣチップと密着しているため、振動に強
く、耐震性に優れている。(1) Good workability. That is, conventionally, wire bonding (wiring) is performed one by one at a required wiring position, but in the case of the present invention, necessary wiring can be performed at a time on one substrate. If a metallizing device such as a vapor deposition device is large, a plurality of substrates can be wired at a time. (2) Good vibration resistance. That is, since the wiring pattern formed by metallization is in close contact with the substrate or the IC chip, it is resistant to vibration and excellent in earthquake resistance.

【００１４】(3) 信頼性が高い。即ち、配線時におい
て、ＩＣチップに機械的ストレスが加わらないため、Ｉ
Ｃチップの破損の可能性が低い。また、ワイヤによる配
線がないため、配線間の接触がなく、信頼性は高い。(3) High reliability. That is, since no mechanical stress is applied to the IC chip during wiring,
The possibility of breakage of the C chip is low. Further, since there is no wiring by wires, there is no contact between the wirings, and the reliability is high.

【００１５】(4) 小型化が可能である。即ち、ワイヤに
よる配線がないため、配線後の高さはワイヤボンディン
グ法に比べ、２／３〜１／５程度となる。また、ＩＣチ
ップ周囲の配線スペ−スもワイヤボンディング法に比べ
て１／２〜１／10程度に縮小でき、小型化が可能であ
る。(4) Size reduction is possible. That is, since there is no wiring by wires, the height after the wiring is about 2/3 to 1/5 as compared with the wire bonding method. Also, the wiring space around the IC chip can be reduced to about 1/2 to 1/10 of that of the wire bonding method, and the size can be reduced.

【００１６】[0016]

【実施例】【Example】

（実施例１）図１は、本発明方法によって得られた半導
体装置の概略説明図を示す。(Embodiment 1) FIG. 1 is a schematic explanatory view of a semiconductor device obtained by the method of the present invention.

【００１７】図中の11は基板である。ここで、基板とし
ては、熱膨脹による断線を防止するためにＳｉに近い熱
膨脹係数を有するセラミック基板やメタルベ−ス基板を
用いる。この基板11の所定の位置には、裸ＩＣチップ12
が接着剤やＳｉとＡｕの共晶結合等の手法により接合さ
れている。前記基板11の側壁には、基板11との段差をな
くすためにＡＩ2 Ｏ3 （アルミナ）等の絶縁膜13で被覆
された傾斜部としてのスカ−ト部14が設けられている。
ここで、スカ−ト部14はＩＣチップ12をウェハからカッ
トする際斜めにカットすることにより、容易に準備でき
る。前記チップ12の上部周縁には、複数の第１電極15が
設けられている。前記チップ12の周囲の基板11上には、
先端部に第２電極16が形成された複数の導体パタ−ン17
が形成されている。前記チップ12の第１電極15と導体パ
タ−ン17の第２電極16は、Ｃｕ，Ｃｒ，ＡＩからなる配
線18により電気的に接続されている。次に、こうした構
成の半導体装置において、配線の形成方法について図２
（Ａ），（Ｂ）及び図７を参照して説明する。In the figure, reference numeral 11 denotes a substrate. Here, as a substrate, a ceramic substrate or a metal-based substrate having a thermal expansion coefficient close to that of Si is used to prevent disconnection due to thermal expansion. At a predetermined position on the substrate 11, a bare IC chip 12
Are joined by an adhesive or a technique such as eutectic bonding of Si and Au. On the side wall of the substrate 11, a skirt portion 14 as an inclined portion covered with an insulating film 13 such as AI 2 O 3 (alumina) is provided in order to eliminate a step with the substrate 11.
Here, the skirt portion 14 can be easily prepared by diagonally cutting the IC chip 12 from the wafer. A plurality of first electrodes 15 are provided on an upper peripheral edge of the chip 12. On the substrate 11 around the chip 12,
A plurality of conductor patterns 17 each having a second electrode 16 formed at the tip.
Are formed. The first electrode 15 of the chip 12 and the second electrode 16 of the conductor pattern 17 are electrically connected by a wiring 18 made of Cu, Cr and AI. Next, in a semiconductor device having such a configuration, a method of forming a wiring will be described with reference to FIG.
This will be described with reference to FIGS.

【００１８】(1) まず、斜めにカットした裸ＩＣチップ
12の傾斜面を絶縁するために、メタルスクリ−ンに窓を
開けたマスクを被せ、アルミナ等の絶縁膜13の蒸着を１
０〜５０μｍの厚さまで行う。なお、アルミナのかわり
に他の酸化物や窒化物を使用してもよい。図７は、蒸着
装置の一例を示すもので、基板11は該基板の裏面側を上
に向けて真空装置にセットする。(1) First, a bare IC chip cut diagonally
In order to insulate the 12 inclined surfaces, a metal screen is covered with a mask having an open window, and an insulating film 13 of alumina or the like is deposited.
This is performed to a thickness of 0 to 50 μm. Note that another oxide or nitride may be used instead of alumina. FIG. 7 shows an example of a vapor deposition apparatus. The substrate 11 is set in a vacuum apparatus with the back side of the substrate facing upward.

【００１９】(2) 次に、図２（Ａ）のように配線形成箇
所にメタライズするための窓19ａを開けたマスク（メタ
ルマスク）19を用いて、Ｃｕ，Ｃｒ，ＡＩ等の導体配線
材料を厚み１０〜５０μｍ蒸着し、基板11上の第２電極
15とチップ12の第１電極14とを接続する配線18を前記絶
縁膜13上等に形成した（図２（Ｂ）図示）。(2) Next, as shown in FIG. 2A, using a mask (metal mask) 19 in which a window 19a for metallizing a wiring formation location is opened, a conductor wiring material such as Cu, Cr, and AI is used. Is deposited to a thickness of 10 to 50 μm, and the second electrode
A wiring 18 connecting the 15 and the first electrode 14 of the chip 12 was formed on the insulating film 13 or the like (FIG. 2B).

【００２０】しかして、上記実施例によれば、裸ＩＣチ
ップ12上の第１電極14と基板11上の第２電極16を接続す
る配線の形成をメタライズにより行なうため、以下に述
べる効果を有する。According to the above embodiment, since the wiring for connecting the first electrode 14 on the bare IC chip 12 and the second electrode 16 on the substrate 11 is formed by metallization, the following effects are obtained. .

【００２１】(1) 作業性が良い。即ち、従来、配線必要
箇所を１箇所ずつワイヤボンディング（配線）していた
が、本発明の場合１枚の基板で必要な配線を一度に行な
うことができる。また、蒸着装置等のメタライズ装置が
大きければ、複数の基板を一度に配線することができ
る。 (2) 耐振性が良い。即ち、メタライズによる配線のパタ
−ンは基板11や裸ＩＣチップ12と密着しているため、振
動に強く、耐震性に優れている。(1) Good workability. In other words, conventionally, wire-bonding (wiring) is performed one by one for each wiring-required portion. However, in the case of the present invention, necessary wiring can be performed at a time on one substrate. If a metallizing device such as a vapor deposition device is large, a plurality of substrates can be wired at a time. (2) Good vibration resistance. That is, since the wiring pattern formed by metallization is in close contact with the substrate 11 and the bare IC chip 12, it is resistant to vibration and excellent in earthquake resistance.

【００２２】(3) 信頼性が高い。即ち、配線時におい
て、裸ＩＣチップ12に機械的ストレスが加わらないた
め、裸ＩＣチップ12の破損の可能性が低い。また、従来
のようにワイヤによる配線がないため、配線間の接触が
なく、信頼性は高い。(3) High reliability. That is, since no mechanical stress is applied to the bare IC chip 12 at the time of wiring, the possibility that the bare IC chip 12 is damaged is low. Further, since there is no wiring by wires as in the related art, there is no contact between the wirings and the reliability is high.

【００２３】(4) 小型化が可能である。即ち、従来のよ
うにワイヤによる配線がないため、配線後の高さはワイ
ヤボンディング法に比べ、２／３〜１／５程度となる。
また、裸ＩＣチップ12周囲の配線スペ−スもワイヤボン
ディング法に比べて１／２〜１／10程度に縮小でき、小
型化が可能である。 （実施例２）(4) Size reduction is possible. That is, since there is no wiring by wires as in the related art, the height after wiring is about 2/3 to 1/5 of that of the wire bonding method.
Also, the wiring space around the bare IC chip 12 can be reduced to about 1/2 to 1/10 of that of the wire bonding method, and the size can be reduced. (Example 2)

【００２４】まず、スカ−ト部21を有した裸ＩＣチップ
12を、基板11に接着剤やＳｉとＡｕの共晶結合等の手法
により接合させた。ここで、前記スカ−ト部21は、セラ
ミックブロックを略直方体形状のチップ12の側面に接着
させることにより形成する。次に、図３（Ａ）のように
配線必要箇所にメタライズするための窓22ａを開けたマ
スク（メタルマスク）22を被せ、導電性の塗料やペ−ス
トを塗布することにより基板11上の第２電極15とチップ
12の第１電極14とを接続する配線23を前記スカ−ト部21
等の上に形成した（図３（Ｂ）図示）。しかして、実施
例２においては、実施例１と比較して、スカ−ト部21が
セラミックブロックよりなるため、絶縁膜も形成が不要
である。First, a naked IC chip having a skirt 21
12 was bonded to the substrate 11 by an adhesive or a technique such as eutectic bonding of Si and Au. Here, the skirt portion 21 is formed by bonding a ceramic block to the side surface of the chip 12 having a substantially rectangular parallelepiped shape. Next, as shown in FIG. 3 (A), a mask (metal mask) 22 having a window 22a for metallizing is placed on a required portion of the wiring, and a conductive paint or paste is applied on the substrate 11 by applying a conductive paint or paste. Second electrode 15 and tip
The wiring 23 for connecting the first electrode 14 to the first electrode 14 is connected to the skirt portion 21.
(FIG. 3B). Thus, in the second embodiment, as compared with the first embodiment, since the skirt 21 is made of a ceramic block, it is not necessary to form an insulating film.

【００２５】[0025]

【発明の効果】以上詳述した如く本発明によれば、裸Ｉ
Ｃチップ上の第１電極と基板上の第２電極との配線形成
をメタライズで行なうことにより、従来と比べ作業性に
優れ、耐震性に優れ、信頼性が高く、かつ小形化が可能
な半導体装置の配線方法を提供できる。As described in detail above, according to the present invention, naked I
By forming metallization between the first electrode on the C chip and the second electrode on the substrate by metallization, a semiconductor that is superior in workability, superior in earthquake resistance, high in reliability and small in size as compared with the prior art A method of wiring the device can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施例に係る半導体装置の説明図。FIG. 1 is an explanatory diagram of a semiconductor device according to an embodiment of the present invention.

【図２】本発明の一実施例に係る半導体装置の配線方法
の説明図。FIG. 2 is an explanatory diagram of a wiring method of a semiconductor device according to one embodiment of the present invention.

【図３】本発明の他の実施例に係る半導体装置の配線方
法の説明図。FIG. 3 is an explanatory diagram of a wiring method of a semiconductor device according to another embodiment of the present invention.

【図４】図２（Ｂ）の要部の断面図。FIG. 4 is a sectional view of a main part of FIG. 2 (B).

【図５】図３（Ｂ）の要部の断面図。FIG. 5 is a sectional view of a main part of FIG. 3 (B).

【図６】ワイヤボンディング法の説明図。FIG. 6 is an explanatory diagram of a wire bonding method.

【図７】本発明に係るアルミナや配線材料を蒸着するた
めの装置の説明図。FIG. 7 is an explanatory view of an apparatus for depositing alumina and a wiring material according to the present invention.

【符号の説明】[Explanation of symbols]

11…基板、12…裸ＩＣチップ、13…絶縁膜、14…スカ−
ト部、15…第１電極、16…第２電極、17…導体パタ−
ン、18，23…配線、19…マスク（メタルマスク）、19
ａ，22ａ…窓。11 ... substrate, 12 ... bare IC chip, 13 ... insulating film, 14 ... scar
G, 15: first electrode, 16: second electrode, 17: conductor pattern
, 18, 23 ... wiring, 19 ... mask (metal mask), 19
a, 22a ... windows.

フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 321Continuation of the front page (58) Field surveyed (Int.Cl. 6 , DB name) H01L 21/60 321

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 基板上に搭載され，上部に複数の第１電
極が形成されるとともに端部に基板主面側に向って末広
がりの傾斜部を有した裸ＩＣチップと、前記裸ＩＣチッ
プの周辺に形成され先端部が複数の第２電極になってい
る導体パターンと、前記第１電極と第２電極とを電気的
に接続する接続手段とを具備する半導体装置の配線方法
において、前記接続手段を前記基板及びＩＣチップ上に
メタライズを行なうことにより形成することを特徴とす
る半導体装置の配線方法。A bare IC chip mounted on a substrate, having a plurality of first electrodes formed thereon, and having an inclined portion diverging toward the main surface of the substrate at an end; A wiring pattern for a semiconductor device, comprising: a conductor pattern formed in the periphery and having a plurality of second electrodes at a tip end; and connection means for electrically connecting the first electrode and the second electrode. means on said substrate and IC chip
A wiring method for a semiconductor device, wherein the wiring method is formed by performing metallization .
JP12382391A 1991-05-28 1991-05-28 Semiconductor device wiring method Expired - Lifetime JP2772157B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12382391A JP2772157B2 (en) 1991-05-28 1991-05-28 Semiconductor device wiring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12382391A JP2772157B2 (en) 1991-05-28 1991-05-28 Semiconductor device wiring method

Publications (2)

Publication Number Publication Date
JPH04350951A JPH04350951A (en) 1992-12-04
JP2772157B2 true JP2772157B2 (en) 1998-07-02

Family

ID=14870248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12382391A Expired - Lifetime JP2772157B2 (en) 1991-05-28 1991-05-28 Semiconductor device wiring method

Country Status (1)

Country Link
JP (1) JP2772157B2 (en)

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US8759148B2 (en) 2009-01-27 2014-06-24 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
US8901728B2 (en) 2009-01-27 2014-12-02 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same
US9070393B2 (en) 2009-01-27 2015-06-30 Panasonic Corporation Three-dimensional structure in which wiring is provided on its surface
US9795033B2 (en) 2009-01-27 2017-10-17 Panasonic Corporation Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

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