JPH0691126B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0691126B2 JPH0691126B2 JP62146593A JP14659387A JPH0691126B2 JP H0691126 B2 JPH0691126 B2 JP H0691126B2 JP 62146593 A JP62146593 A JP 62146593A JP 14659387 A JP14659387 A JP 14659387A JP H0691126 B2 JPH0691126 B2 JP H0691126B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- bonding pad
- film
- semiconductor device
- organic insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0504—14th Group
- H01L2924/05042—Si3N4
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に絶縁膜の構造に関す
る。The present invention relates to a semiconductor device, and more particularly to a structure of an insulating film.
〔従来の技術〕 多層配線層間絶縁膜やパッシベーション膜として有機絶
縁層を有する半導体装置は、有機絶縁層が吸湿すること
によってその絶縁抵抗が低下するのを防止するため更に
有機絶縁層の上を耐湿性の良い無機絶縁層で被覆する事
が行われていた。[Prior Art] A semiconductor device having an organic insulating layer as a multilayer wiring interlayer insulating film or a passivation film further has a moisture-proof property on the organic insulating layer in order to prevent the insulation resistance from lowering due to moisture absorption by the organic insulating layer. Coating with an inorganic insulating layer having good properties has been performed.
第２図は従来例の主要部を示す半導体チップの縦断面図
である。FIG. 2 is a vertical sectional view of a semiconductor chip showing a main part of a conventional example.
ボンディングパッド１の周辺部分にも有機絶縁層３と無
機絶縁層２の複合絶縁層が設けられている。The composite insulating layer of the organic insulating layer 3 and the inorganic insulating layer 2 is also provided in the peripheral portion of the bonding pad 1.
上述した従来の半導体装置では、電気的接続のためのパ
ッシベーション膜の開口部のボンディングパッド１の周
辺部分においても有機絶縁層３と無機絶縁層２が重なっ
た構造となっているため、ボンディング時に位置ずれ等
により機械的衝撃がこの周辺部分に加えられると容易に
無機絶縁層２が破損したり更には有機絶縁層３の下地
（例えば酸化シリコン膜４）との界面剥離が起きて、信
頼性とりわけ耐湿性が大幅に低下してしまうという欠点
がある。In the above-described conventional semiconductor device, the organic insulating layer 3 and the inorganic insulating layer 2 overlap each other even in the peripheral portion of the bonding pad 1 at the opening of the passivation film for electrical connection. When a mechanical shock is applied to this peripheral portion due to displacement or the like, the inorganic insulating layer 2 is easily damaged, and further, the interface peeling with the underlying layer (for example, the silicon oxide film 4) of the organic insulating layer 3 occurs, so that the reliability is particularly high. There is a drawback that the moisture resistance is significantly reduced.
本発明は、半導体基板上の所定の絶縁膜を選択的に被覆
するボンディングパッドと、前記ボンディングパッドの
表面部に開口を有して前記ボンディングパッドの設けら
れた前記絶縁膜を被覆するパッシベーション膜とを備え
た半導体装置において、前記パッシベーション膜が、前
記ボンディングパッドおよびその周辺を除き前記絶縁膜
を被覆する有機絶縁層と、前記ボンディングパッドおよ
び前記有機絶縁層の設けられた前記絶縁層を被覆する無
機絶縁層とからなるというものである。The present invention provides a bonding pad that selectively covers a predetermined insulating film on a semiconductor substrate, and a passivation film that covers the insulating film provided with the bonding pad and has an opening on the surface of the bonding pad. In the semiconductor device including, the passivation film is an organic insulating layer that covers the insulating film except the bonding pad and its periphery, and an inorganic layer that covers the insulating layer provided with the bonding pad and the organic insulating layer. It is composed of an insulating layer.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の主要部を示す半導体チップ
の縦断面図である。FIG. 1 is a vertical sectional view of a semiconductor chip showing a main part of an embodiment of the present invention.
この実施例はシリコンからなる半導体基板５の表面に設
けられた酸化シリコン膜４上の厚さ１〜２μｍのAlから
なるボンディングパッド１の表面部に開口６を有するパ
ッシベーション膜がボンディングパッド１の周囲に設け
られた厚さ１μｍのスパッタ法で被着した窒化シリコン
膜（２）からなる幅50μｍの無機絶縁層領域７、及び有
機絶縁層３（厚さ１〜２μｍのポリイミド）とその表面
に設けられた無機絶縁層２（窒化シリコン）とからなる
複合絶縁層領域８を有している。In this embodiment, a passivation film having an opening 6 on the surface portion of a bonding pad 1 made of Al and having a thickness of 1 to 2 μm on a silicon oxide film 4 provided on the surface of a semiconductor substrate 5 made of silicon has a periphery around the bonding pad 1. The inorganic insulating layer region 7 having a width of 50 μm, which is made of the silicon nitride film (2) deposited by the sputtering method and having a thickness of 1 μm, and the organic insulating layer 3 (polyimide having a thickness of 1 to 2 μm) and the surface thereof. It has a composite insulating layer region 8 composed of the formed inorganic insulating layer 2 (silicon nitride).
外部との電気的接続用導体部であるボンディングパッド
１はその周辺を窒化シリコン膜などの無機絶縁層２によ
って囲まれておりポリイミドなどから成る有機絶縁層３
とボンディングパッド１とは距離を設けている。A bonding pad 1 which is a conductor portion for electrical connection to the outside is surrounded by an inorganic insulating layer 2 such as a silicon nitride film, and an organic insulating layer 3 made of polyimide or the like.
And the bonding pad 1 are separated from each other.
つまり、ボンディングパッドの周辺には、下地との密着
性が悪い有機絶縁層が存在していないので、ボンディン
グ時にパッシベーション膜が破損される危険性は著しく
低減される。このボンディング時にパッシベーション膜
に生じるクラックやはがれを顕微鏡で観察すると、従来
例では数パーセントの割合で発見されたが、この実施例
では殆ど皆無であった。That is, since there is no organic insulating layer having poor adhesion to the base around the bonding pad, the risk of damaging the passivation film during bonding is significantly reduced. When a crack or peeling generated in the passivation film at the time of this bonding was observed with a microscope, it was found at a rate of several percent in the conventional example, but almost none in this example.
以上説明したように本発明ではボンディングパッドとそ
の周辺に有機絶縁層を有しない無機絶縁領域が配置され
ているので、ボンディング時のパッシベーション膜の破
損が防止され大幅に半導体装置の耐湿性を向上できると
いう効果がある。As described above, in the present invention, since the bonding pad and the inorganic insulating region having no organic insulating layer are arranged around the bonding pad, damage of the passivation film at the time of bonding is prevented and the moisture resistance of the semiconductor device can be significantly improved. There is an effect.
第１図は本発明の一実施例の主要部を示す半導体チップ
の縦断面図、第２図は従来例の主要部を示す半導体チッ
プの縦断面図である。 １……ボンディングパッド、２……無機絶縁層、３……
有機絶縁層、４……酸化シリコン膜、５……半導体基
板、６……開口、７……無機絶縁層領域、8,8′……複
合絶縁層領域。FIG. 1 is a vertical sectional view of a semiconductor chip showing a main part of an embodiment of the present invention, and FIG. 2 is a vertical sectional view of a semiconductor chip showing a main part of a conventional example. 1 ... Bonding pad, 2 ... Inorganic insulating layer, 3 ...
Organic insulating layer, 4 ... Silicon oxide film, 5 ... Semiconductor substrate, 6 ... Opening, 7 ... Inorganic insulating layer region, 8,8 '... Composite insulating layer region.
Claims (1)
覆するボンディングパッドと、前記ボンディングパッド
の表面部に開口を有して前記ボンディングパッドの設け
られた前記絶縁膜を被覆するパッシベーション膜とを備
えた半導体装置において、前記パッシベーション膜が、
前記ボンディングパッドおよびその周辺を除き前記絶縁
膜を被覆する有機絶縁層と、前記ボンディングパッドお
よび前記有機絶縁層の設けられた前記絶縁層を被覆する
無機絶縁層とからなることを特徴とする半導体装置。1. A bonding pad for selectively covering a predetermined insulating film on a semiconductor substrate, and a passivation film for covering the insulating film having an opening at the surface of the bonding pad and provided with the bonding pad. In a semiconductor device including and, the passivation film,
A semiconductor device comprising an organic insulating layer that covers the insulating film except the bonding pad and its periphery, and an inorganic insulating layer that covers the insulating layer provided with the bonding pad and the organic insulating layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62146593A JPH0691126B2 (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62146593A JPH0691126B2 (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63308924A JPS63308924A (en) | 1988-12-16 |
| JPH0691126B2 true JPH0691126B2 (en) | 1994-11-14 |
Family
ID=15411227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62146593A Expired - Lifetime JPH0691126B2 (en) | 1987-06-11 | 1987-06-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691126B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6143638A (en) * | 1997-12-31 | 2000-11-07 | Intel Corporation | Passivation structure and its method of fabrication |
| JP3121311B2 (en) * | 1998-05-26 | 2000-12-25 | 日本電気株式会社 | Multilayer wiring structure, semiconductor device having the same, and manufacturing method thereof |
| TW201432864A (en) * | 2013-02-01 | 2014-08-16 | Murata Manufacturing Co | Semiconductor device |
| DE112013007584T5 (en) | 2013-11-27 | 2016-08-18 | Hewlett-Packard Development Company, L.P. | Printhead with bondpad surrounded by a partition |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58135645A (en) * | 1982-02-08 | 1983-08-12 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS63192240A (en) * | 1987-02-03 | 1988-08-09 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-06-11 JP JP62146593A patent/JPH0691126B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63308924A (en) | 1988-12-16 |
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