JPS63192240A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63192240A
JPS63192240A JP2317187A JP2317187A JPS63192240A JP S63192240 A JPS63192240 A JP S63192240A JP 2317187 A JP2317187 A JP 2317187A JP 2317187 A JP2317187 A JP 2317187A JP S63192240 A JPS63192240 A JP S63192240A
Authority
JP
Japan
Prior art keywords
film
sin
interface
semiconductor device
intrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2317187A
Other languages
Japanese (ja)
Inventor
Goro Mitarai
御手洗 五郎
Kazumasa Satsuma
薩摩 和正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2317187A priority Critical patent/JPS63192240A/en
Publication of JPS63192240A publication Critical patent/JPS63192240A/en
Pending legal-status Critical Current

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  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To inhibit the generation of cracks at the end section of the interface of an SiN film and an SiO2 film, and to prevent the intrusion of water by applying an elastically deformed film just under the end section of an overcoat film consisting of SiN. CONSTITUTION:An elastically deformed film 10 is applied between an silicon nitride (SiN) film 7 and an SiO2 film 4. When a PCT test is conducted at that time, large stress is applied to the surface of a chip by the swelling of a molding resin surrounding the periphery of the semiconductor chip. Consequently, large stress is applied onto the interface of the SiN film 7 and the SiO2 film 4 having the large difference of thermal expansion coefficients, but stress is relaxed because the Al film 10 formed on the interface is deformed elastically, thus generating no crack. Accordingly, the intrusion of water from the interface section is also prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、オーバーコート膜を使用した半導体装置に関
し、特に耐湿性の良好な半導体装置に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device using an overcoat film, and particularly to a semiconductor device with good moisture resistance.

〔従来の技術〕[Conventional technology]

従来より半導体チップ表面保護膜(いわゆるオーバーコ
ート膜)として、グラスコート膜(Si02膜)やシリ
コンナイトライド膜(SiN膜)が使用されている。特
に素子の耐湿性向上には、以前から適用されているグラ
スコート1m(si。
BACKGROUND ART Glass coat films (Si02 films) and silicon nitride films (SiN films) have conventionally been used as semiconductor chip surface protective films (so-called overcoat films). In particular, glass coat 1m (si) has been used for a long time to improve the moisture resistance of devices.

2膜)よりも膜の組成が緻密で不純物に対するブロック
効果が強く又吸湿性もないSiN膜が有効であることか
ら、多くの半導体装置に通用され始めている。
Since the SiN film has a denser composition, has a stronger blocking effect against impurities, and is not hygroscopic than the SiN film (2), and is effective, it is beginning to be used in many semiconductor devices.

第2図はNPN)ランジスタにSiNオーバーコート膜
を被着した従来の半導体装置の例を示す断面図である。
FIG. 2 is a sectional view showing an example of a conventional semiconductor device in which an SiN overcoat film is applied to an NPN transistor.

この図において、1はNPN)ランジスタのコレクタ、
2はベース、3はエミッタ、4は酸化膜、5はベース電
極、6はエミッタ電極、7はシリコンナイトライド膜、
8はベースポンディングパッド、9はエミッタボンディ
ングバッドである。このように構成された半導体装置は
、緻密でかつ吸湿性のない5iNIQ7でエミッタ、ペ
ースポンディングパッド9.8及びスクライブストリー
ト以外の部分を覆うことにより、チップ表面を保護して
特に耐湿性に対して効果を得ようとしているものである
In this figure, 1 is the collector of the NPN) transistor,
2 is a base, 3 is an emitter, 4 is an oxide film, 5 is a base electrode, 6 is an emitter electrode, 7 is a silicon nitride film,
8 is a base bonding pad, and 9 is an emitter bonding pad. The semiconductor device configured in this way protects the chip surface by covering the parts other than the emitter, pace pounding pad 9.8 and scribe street with 5iNIQ7, which is dense and has no moisture absorption, and is particularly resistant to moisture. This is what we are trying to achieve.

ところが、このような従来の素子に対して耐湿性の評価
方法として一般的なプレンシャークンカーテスト(PC
Tテスト)を行なうと、半導体チップの周囲をかこんで
いるモールド樹脂が水分の樹脂への侵入のため及び高温
にさらされるためにふくれ上がり(膨潤)、チップ表面
に大きなストレスを与えるようになる。
However, as a method for evaluating the moisture resistance of such conventional elements, the general pre-shank car test (PC
When the molding resin surrounding the semiconductor chip (T test) is performed, the molding resin surrounding the semiconductor chip swells (swells) due to moisture intrusion into the resin and exposure to high temperatures, which places a large stress on the chip surface.

すると、SiN膜7は酸化膜(Sin2膜)4に比べ緻
密で硬く熱膨張係数が小さい、すなわちSiN膜7と5
i02膜4との熱膨張係数の差が大きいので、SiN膜
7と5in2膜4の界面に大きなストレスがかかり、第
3図に−示す如(SiNlli7と5iO2HIJ!4
の界面の端部かられずかにクランク11が発生する。こ
のクランク11へ水分が侵入し、この水分の侵入により
ますますクランク11が広がり、その後SiN膜7膜体
自体ラックが入り素子のリーク電流が増大する等の不良
が発生するという不都合を呈する。
Then, the SiN film 7 is denser and harder than the oxide film (Sin2 film) 4, and has a smaller thermal expansion coefficient.
Since the difference in thermal expansion coefficient with the i02 film 4 is large, a large stress is applied to the interface between the SiN film 7 and the 5in2 film 4, as shown in FIG.
A crank 11 is generated slightly from the edge of the interface. Moisture enters into the crank 11, and this intrusion of water causes the crank 11 to further expand, and then the SiN film 7 itself becomes racked, causing problems such as an increase in leakage current of the element.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の半導体装置は以上のように構成されているので、
本来5iNIQはPCTテストやその他の信頼性テスト
に対して強力なパッシベイション効果を有しているにも
かかわらず、SiN膜と5i02膜の界面端部にクラン
クが発生ずることにより、このSiN膜の持つ実力を十
分に利用することができないという問題点があった。
Conventional semiconductor devices are configured as described above, so
Although 5iNIQ originally has a strong passivation effect in PCT tests and other reliability tests, cranks occur at the edge of the interface between the SiN film and the 5i02 film, causing the SiN film to The problem was that it was not possible to fully utilize the abilities of the people.

この発明はかかる問題点を解決するためになされたもの
で、SiN膜と5iO2I15!の界面端部でのクラッ
ク発生を抑えると共に、水の侵入を防止することのでき
る半導体装置を得ることを目的とする。
This invention was made to solve this problem, and consists of a SiN film and 5iO2I15! An object of the present invention is to obtain a semiconductor device which can suppress the occurrence of cracks at the edge of the interface and can prevent water from entering.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る半導体装置は、SiNからなるオーバー
コート膜の端部の直下に塑性変形する被膜を被着したも
のである。
The semiconductor device according to the present invention has a plastically deformable film deposited directly under the edge of an overcoat film made of SiN.

〔作用〕[Effect]

この発明においては、5iNIQと5i02膜の間に塑
性変形する被膜が被着されていることにより、SiN膜
と5io2膜との熱膨張係数の差によるズレのストレス
が緩和され界面端部でのクランクの発生が防止され、又
水の侵入も防止される。
In this invention, since a plastically deformable film is attached between the 5iNIQ and 5i02 films, stress caused by misalignment due to the difference in thermal expansion coefficient between the SiN film and the 5io2 film is alleviated, and the crankshaft at the edge of the interface is The generation of water is prevented, and the intrusion of water is also prevented.

〔実施例〕〔Example〕

第1図は本発明の一実施例による半導体装置の断面図を
示すが、以下、この図を用いて本実施例を説明する。
FIG. 1 shows a cross-sectional view of a semiconductor device according to an embodiment of the present invention, and this embodiment will be explained below using this figure.

第1図において、素子は従来例と同じNPN トランジ
スタであり、■はコレクタ、2はベース、3はエミッタ
、4はSiO2膜、5はベース電極、6はエミッタ電橋
、7はSiN膜、8,9はポンディングパッド、10は
塑性変形するAI被被膜ある。
In Fig. 1, the element is the same NPN transistor as the conventional example, and ▪ is the collector, 2 is the base, 3 is the emitter, 4 is the SiO2 film, 5 is the base electrode, 6 is the emitter bridge, 7 is the SiN film, and 8 , 9 is a bonding pad, and 10 is an AI coating that is plastically deformed.

かかる構造の装置にPCTテストを行なうと、半導体チ
ップの周囲をかこんでいるモールド樹脂の膨潤によりチ
ップ表面に大きなストレスが加わる。このため、熱膨張
係数の差の大きいSiN膜7と5i02膜4との界面に
大きなストレスが加わるが、この界面に形成されたAI
被膜10が塑性変形するためにこのストレスが緩和され
、クランクは発生しない。従って、この部分からの水の
l凱 侵入も防止され、本来SiN膜の持つキ密で硬く、不純
物の侵入に対してブロック効果が大きいというパンシベ
イション膜としてのすぐれた特性を十分に生かすことが
できる。
When a PCT test is performed on a device having such a structure, a large stress is applied to the chip surface due to swelling of the molding resin surrounding the semiconductor chip. Therefore, a large stress is applied to the interface between the SiN film 7 and the 5i02 film 4, which have a large difference in coefficient of thermal expansion, but the AI formed at this interface
Since the coating 10 is plastically deformed, this stress is alleviated and no cranking occurs. Therefore, the intrusion of water from this part is also prevented, making full use of the excellent characteristics of the SiN film as a pansivation film, which is dense and hard and has a great blocking effect against the intrusion of impurities. Can be done.

なお、上記実施例では塑性変形する膜としてAI金屈膜
を被着する場合について説明したが、ポリイミド膜等の
有機物被膜を被着してもよく、上記実施例と同等の効果
が得られるのはもちろんである。
In addition, in the above example, a case was explained in which an AI gold film was applied as a plastically deformable film, but an organic film such as a polyimide film may also be applied, and the same effect as in the above example can be obtained. Of course.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る半導体装置によれば、S
iNからなるオーバーコート膜の端部の直下に塑性変形
する被膜を被着したので、SiN膜と5i02膜の界面
でのクラック発生及び水の侵入を防止でき、StN膜本
来のパンシベイション膜としてのすぐれた特性を十分に
生かすことができ、装置の耐湿性を大幅に向上すること
ができる。
As described above, according to the semiconductor device according to the present invention, S
Since a plastically deformable film is deposited directly under the edge of the overcoat film made of iN, it is possible to prevent the occurrence of cracks and water intrusion at the interface between the SiN film and the 5i02 film, and it can be used as a pansivation film originally intended for the StN film. This makes it possible to take full advantage of the excellent properties of this material and greatly improve the moisture resistance of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体装置を示す断
面図、第2図は従来の半導体装置を示す断面図、第3図
はSiN膜と5i02膜の界面に発生したクランクを説
明するための断面図である。 1はコレクタ、2はベース、3はエミッタ、4は酸化膜
、5はベース電極、6はエミッタ電極、7はシリコンナ
イトライド膜、10は塑性変形する被膜。 なお、図中同一符号は、同−又は相当部分を示す。
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a conventional semiconductor device, and FIG. 3 is for explaining a crank that occurs at the interface between the SiN film and the 5i02 film. FIG. 1 is a collector, 2 is a base, 3 is an emitter, 4 is an oxide film, 5 is a base electrode, 6 is an emitter electrode, 7 is a silicon nitride film, and 10 is a plastically deformable film. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体チップ表面にシリコンナイトライドからな
るオーバーコート膜を被着してなる半導体装置において
、 上記オーバーコート膜はその全ての端部の直下に塑性変
形する被膜を被着したものであることを特徴とする半導
体装置。
(1) In a semiconductor device in which an overcoat film made of silicon nitride is deposited on the surface of a semiconductor chip, the overcoat film shall have a plastically deformable film deposited directly under all edges thereof. A semiconductor device characterized by:
(2)上記塑性変形被膜は金属膜であることを特徴とす
る特許請求の範囲第1項記載の半導体装置。
(2) The semiconductor device according to claim 1, wherein the plastically deformed film is a metal film.
(3)上記塑性変形被膜は有機物被膜であることを特徴
とする特許請求の範囲第1項記載の半導体装置。
(3) The semiconductor device according to claim 1, wherein the plastically deformed film is an organic film.
JP2317187A 1987-02-03 1987-02-03 Semiconductor device Pending JPS63192240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2317187A JPS63192240A (en) 1987-02-03 1987-02-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2317187A JPS63192240A (en) 1987-02-03 1987-02-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63192240A true JPS63192240A (en) 1988-08-09

Family

ID=12103180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2317187A Pending JPS63192240A (en) 1987-02-03 1987-02-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63192240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308924A (en) * 1987-06-11 1988-12-16 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63308924A (en) * 1987-06-11 1988-12-16 Nec Corp Semiconductor device

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