JPS6255696B2 - - Google Patents
Info
- Publication number
- JPS6255696B2 JPS6255696B2 JP55069819A JP6981980A JPS6255696B2 JP S6255696 B2 JPS6255696 B2 JP S6255696B2 JP 55069819 A JP55069819 A JP 55069819A JP 6981980 A JP6981980 A JP 6981980A JP S6255696 B2 JPS6255696 B2 JP S6255696B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- protective film
- film
- polyimide
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229920001721 polyimide Polymers 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 23
- 230000001681 protective effect Effects 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 239000004642 Polyimide Substances 0.000 description 21
- 239000000758 substrate Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 7
- 125000004429 atom Chemical group 0.000 description 6
- 239000005360 phosphosilicate glass Substances 0.000 description 6
- 239000004952 Polyamide Substances 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 229920002647 polyamide Polymers 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の構造にかかり、特に半導
体チツプの表面保護構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a surface protection structure for a semiconductor chip.
従来の半導体装置に於ては素子形成及び配線層
の形成が終つた半導体チツプ表面が、そのボンデ
イング・パツド及びダイシング・ラインを除い
て、窒化シリコン（Si3N4）或るいは燐硅酸ガラス
（PSG）等の表面保護膜で覆われてなつていた。
In conventional semiconductor devices, the surface of the semiconductor chip after element formation and wiring layer formation, except for bonding pads and dicing lines, is made of silicon nitride (Si 3 N 4 ) or phosphosilicate glass. It was covered with a surface protective film such as (PSG) and faded.
然しこれら従来の表面保護膜には次のような問
題点があつた。
However, these conventional surface protective films have the following problems.
即ち(1)機械的な衝撃に対して脆弱な性質を有す
るために、チツプ・ボンデイングに際してコレツ
ト等による機械的衝撃により保護膜にクラツクを
生じ保護効果が失われるという問題、(2)保護膜と
該保護膜から露出しているボンデイング・パツド
とのコントラストが弱いために、ワイヤ・ボンデ
イングに際してテレビ・カメラ等によるボンデイ
ング・パツド部の認識が困難で作業能率が低下す
るという問題、(3)該保護膜がα線の遮蔽効果を有
しないために、半導体メモリ等に於てはα線によ
るソフト・エラーが防げないという問題等であ
る。 Namely, (1) the protective film is vulnerable to mechanical shock, so the mechanical shock caused by the collect etc. during chip bonding can cause cracks in the protective film and the protective effect is lost; and (2) the protective film and (3) The problem of low contrast with the bonding pad exposed from the protective film makes it difficult for televisions, cameras, etc. to recognize the bonding pad during wire bonding, reducing work efficiency; (3) protection of the bonding pad; Since the film does not have an effect of shielding alpha rays, there is a problem that soft errors caused by alpha rays cannot be prevented in semiconductor memories and the like.
本発明は上記問題点に鑑み、機械的衝撃により
クラツクが発生することがなく、そしてボンデイ
ング・パツドとの間の色調のコントラストが大き
く、且つα線の阻止効果を有する半導体チツプの
表面保護構造を提供する。 In view of the above problems, the present invention provides a surface protection structure for a semiconductor chip that does not cause cracks due to mechanical impact, has a large color contrast with the bonding pad, and has an α-ray blocking effect. provide.
上記の問題点は、分子構造中にシリコン原子を
含むポリイミド膜からなり半導体チツプ表面を覆
う第１の保護膜と、分子構造中にシリコン原子を
含まないポリイミド膜からなり該第１の保護膜上
に積層された第２の保護膜とを備え、該第２の保
護膜が該第１の保護膜より厚く形成され、半導体
チツプに形成されたボンデイング・パツド上の前
記第１及び第２の保護膜が選択的に除去されてい
ることを特徴とする半導体装置によつて達成され
る。
The above problem is that the first protective film is made of a polyimide film containing silicon atoms in its molecular structure and covers the surface of the semiconductor chip, and the first protective film is made of a polyimide film that does not contain silicon atoms in its molecular structure. a second protective film laminated on a bonding pad formed on a semiconductor chip, the second protective film being thicker than the first protective film; This is achieved by a semiconductor device characterized in that a film is selectively removed.
以下本発明を図に示す実施例の断面構造図、に
より詳細に説明する。
Hereinafter, the present invention will be explained in detail with reference to cross-sectional structural diagrams of embodiments shown in the drawings.
本発明の半導体装置に用いられる半導体チツプ
は、例えば図に示すようにメモリ或るいはロジツ
ク回路を構成する能動素子が形成されているシリ
コン（Si）基板１の表面に、例えば4000〜5000
〔Å〕程度の厚さの二酸化シリコン（SiO2）膜２
が形成されており、該SiO2膜２に形成された電
極窓部に於て、Si基板１面に形成されている前記
能動素子の不純物導入領域３に接続する金属配線
層例えば厚さ7000〜10000〔Å〕程度のアルミニ
ウム（Al）配線層４が前記SiO2膜２上に形成さ
れており、そして該Al配線層４が形成されたSi基
板１の表面が前記Al配線層４のボンデイング・
パツド領域５及びSi基板１のダイシング・ライン
領域６を除いて、例えば4000〜6000〔Å〕程度の
厚さの窒化シリコン（Si3N4）膜或るいは１〔μ
ｍ〕程度の厚さの燐硅酸ガラス（PSG）膜等から
なる絶縁膜７で覆われてなる従来構造のシリコ
ン・チツプ上に、前記ボンデイング・パツド領域
５及びダイシング・ライン領域６を除いて、下層
に2000〜3000〔Å〕程度の厚さのSi原子をその分
子構造中に含むポリ・イミドとSi原子を含まない
ポリ・イミドの混合物からなるポリ・イミド層８
が形成され、上層には10〜30〔μｍ〕程度の厚い
Si原子を含まないポリ・イミド層９からなる二層
構造のポリ・イミド層が形成された構造を有して
いる。 The semiconductor chip used in the semiconductor device of the present invention has, for example, 4000 to 5000 chips on the surface of a silicon (Si) substrate 1 on which active elements constituting a memory or logic circuit are formed, as shown in the figure.
Silicon dioxide (SiO 2 ) film 2 with a thickness of about [Å]
is formed, and in the electrode window portion formed in the SiO 2 film 2, a metal wiring layer, for example, with a thickness of 7,000 to 7,000 mm, is connected to the impurity-introduced region 3 of the active element formed on the surface of the Si substrate. An aluminum (Al) wiring layer 4 of about 10000 [Å] is formed on the SiO 2 film 2, and the surface of the Si substrate 1 on which the Al wiring layer 4 is formed is bonded to the Al wiring layer 4.
Except for the pad region 5 and the dicing line region 6 of the Si substrate 1, a silicon nitride (Si 3 N 4 ) film with a thickness of, for example, 4000 to 6000 [Å] or 1 [μ
m] on a silicon chip with a conventional structure covered with an insulating film 7 made of a phosphosilicate glass (PSG) film or the like with a thickness of about , a polyimide layer 8 consisting of a mixture of polyimide containing Si atoms in its molecular structure and polyimide containing no Si atoms with a thickness of about 2000 to 3000 [Å] in the lower layer.
is formed, and the upper layer is about 10 to 30 [μm] thick.
It has a structure in which a two-layered polyimide layer including a polyimide layer 9 that does not contain Si atoms is formed.
なお図に於て１はSi基板、２はSiO2膜、３は不
純物導入領域、７は絶縁膜を表わす。 In the figure, 1 represents a Si substrate, 2 represents an SiO 2 film, 3 represents an impurity introduced region, and 7 represents an insulating film.
上記本発明の構造を有するシリコン・チツプを
形成する方法について説明する。通常用いられる
方法により能動素子、Al配線層等の形成が完了
し、表面がAl配線層のボンデイング・パツド部
及びダイシング・ラインを除いてSi3N4或るいは
PSG等の絶縁膜で覆われているSi基板上に、先ず
2000〜3000〔Å〕程度の厚さのSi原子をその分子
中に含むポリ・アミドの混合されたSi原子を含ま
ないポリ・アミド層をスピン・コートして後、続
いてSi原子を含まない炭素Ｃと窒素Ｎと酸素Ｏと
水素Ｈとのみからなる通常のポリ・アミド層を10
〜30〔μｍ〕程度に昇温させて前記ポリ・アミド
層の第１次キユアーを行う。 A method for forming a silicon chip having the structure of the present invention will be described. Formation of active elements, Al wiring layer, etc. is completed by a commonly used method, and the surface is made of Si 3 N 4 or Al wiring layer except for bonding pads and dicing lines.
First, on a Si substrate covered with an insulating film such as PSG,
After spin-coating a Si atom-free polyamide layer mixed with polyamide containing Si atoms in its molecules to a thickness of about 2000 to 3000 Å, followed by Si atom-free polyamide layer. A normal polyamide layer consisting only of carbon C, nitrogen N, oxygen O, and hydrogen H is
The polyamide layer is first cured by raising the temperature to about 30 [μm].
次いで上記キユアーにより形成されたポリ・イ
ミド層上にネガ・レジスト層をスピン・コート
し、フオト・プロセスにより該ネガ・レジスト層
の前記Al配線のボンデイング・パツド領域及び
前記ダイシング・ライン領域を覆う領域にエツチ
ング窓を形成して後、該ネガ・レジスト層をマス
クとして、ヒドラジンを主成分とするエツチング
液等を用いて約55〔℃〕程度の温度でポリ・イミ
ド層のエツチングを行い、該ポリ・イミド層に形
成せしめた窓内にAl配線層のボンデイング・パ
ツド領域及びSi基板のダイシング・ライン領域を
表出させる。そして該基板面のネガ・レジスト層
を除去して後、該基板を約400〜450〔℃〕に昇温
せしめ、ポリ・イミド層を完全にキユアーさせ、
次いで前記ダイシング・ラインに於て該基板を切
断して、本発明の構造を有するシリコン・チツプ
を形成する。 Next, a negative resist layer is spin coated on the polyimide layer formed by the above curing process, and a region of the negative resist layer that covers the bonding pad region of the Al wiring and the dicing line region is formed by a photo process. After forming an etching window on the polyimide layer, using the negative resist layer as a mask, the polyimide layer is etched at a temperature of approximately 55 [°C] using an etching solution containing hydrazine as a main component. - Expose the bonding pad area of the Al wiring layer and the dicing line area of the Si substrate within the window formed in the imide layer. After removing the negative resist layer on the substrate surface, the substrate is heated to about 400 to 450 [°C] to completely cure the polyimide layer,
The substrate is then cut along the dicing line to form silicon chips having the structure of the present invention.
上記のような方法により形成した本発明の構造
を有する半導体チツプに於けるSi原子を含むポ
リ・イミド層は下層のSi3N4或るいはPSG等の絶
縁層に対して、極めて優れた接着性を有し、半導
体装置を組み立てる際に負荷される高温や半導体
装置の通電動作時に形成される高温状態により前
記ポリ・イミド層が下層の絶縁層から剥離するこ
とがなく、半導体チツプに形全されている能動素
子表面は外部雰囲気から充分に保護される。
The polyimide layer containing Si atoms in the semiconductor chip having the structure of the present invention formed by the method described above has extremely excellent adhesion to the underlying insulating layer such as Si 3 N 4 or PSG. The polyimide layer does not peel off from the underlying insulating layer due to the high temperatures that are applied when assembling a semiconductor device or the high temperature conditions that occur when the semiconductor device is energized, and the semiconductor chip can be fully formed. The exposed active element surfaces are well protected from the external atmosphere.
そしてポリ・イミド層は僅かな可塑性を有し、
機械的衝撃によりクラツクが発生することがな
い。よつて、チツプ・ボンデイング等に際して、
加えられる外圧に対して更に強い保護効果が実施
例に示すようにSi原子を含むポリ・イミド層上
に、該ポリ・イミド層と親和性を有する厚い通常
のポリ・イミド層を形成することにより得られ
る。 And the polyimide layer has slight plasticity,
Cracks do not occur due to mechanical impact. Therefore, when performing chip bonding, etc.
An even stronger protective effect against applied external pressure can be obtained by forming a thick regular polyimide layer that has affinity with the polyimide layer containing Si atoms, as shown in the example. can get.
又上記ポリ・イミド層は褐色を呈し、Al配線
層のボンデイング・パツドと強いコントラストを
有するので、ワイヤ・ボンデイングに際してのテ
レビ・カメラ等によるバツド位置の認識が容易且
つ正確になる。 Further, the polyimide layer has a brown color and has a strong contrast with the bonding pad of the Al wiring layer, so that the position of the pad can be easily and accurately recognized by a television camera or the like during wire bonding.
そして又上記ポリ・イミド層はα線を阻止する
能力も備えているので該ポリ・イミド層を厚く形
成すれば、能動素子面に到達するα線を大幅に減
少せしめることができる。 Furthermore, since the polyimide layer has the ability to block α rays, by forming the polyimide layer thickly, the α rays reaching the active element surface can be significantly reduced.
以上説明したように本発明によれば、半導体チ
ツプ表面の保護が完全になり、ワイヤ・ボンデイ
ングの際のボンデイング・パツトの検出が容易に
なり、且つ半導体能動素子領域に対するα線の遮
蔽もなされるので、半導体メモリや半導体ロジツ
ク等の半導体集積回路等の製造歩留まり、量産性
及び品質の向上等を図ることができる。 As explained above, according to the present invention, the surface of the semiconductor chip is completely protected, bonding pads can be easily detected during wire bonding, and alpha rays are shielded from the semiconductor active element region. Therefore, it is possible to improve the manufacturing yield, mass productivity, and quality of semiconductor integrated circuits such as semiconductor memories and semiconductor logic.
図は本発明の一実施例の断面構造図である。図
に於て１はシリコン基板、２はSiO2膜、３は不
純物導入領域、４はアルミニウム配線層、５はボ
ンデイング・パツド領域、６はダイシング・ライ
ン領域、７は絶縁膜、８はシリコン原子をその分
子構造中に含むポリ・イミドとシリコン原子を含
まないポリ・イミドの混合物からなるポリ・イミ
ド層、９はシリコン原子を含まないポリ・イミド
層を表わす。
The figure is a cross-sectional structural diagram of one embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a SiO 2 film, 3 is an impurity doped region, 4 is an aluminum wiring layer, 5 is a bonding pad region, 6 is a dicing line region, 7 is an insulating film, and 8 is a silicon atom. The polyimide layer 9 is made of a mixture of polyimide containing in its molecular structure and polyimide containing no silicon atoms. 9 represents a polyimide layer containing no silicon atoms.
Claims (1)
膜からなり半導体チツプ表面を覆う第１の保護膜
と、分子構造中にシリコン原子を含まないポリイ
ミド膜からなり該第１の保護膜上に積層された第
２の保護膜とを備え、該第２の保護膜が該第１の
保護膜より厚く形成され、半導体チツプに形成さ
れたボンデイング・パツド上の前記第１及び第２
の保護膜が選択的に除去されていることを特徴と
する半導体装置。1. A first protective film made of a polyimide film containing silicon atoms in its molecular structure and covering the surface of the semiconductor chip; and a first protective film laminated on the first protective film made of a polyimide film not containing silicon atoms in its molecular structure. 2 protective films, the second protective film is formed thicker than the first protective film, and the first and second protective films are formed on the bonding pads formed on the semiconductor chip.
A semiconductor device characterized in that a protective film is selectively removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6981980A JPS56167333A (en) | 1980-05-26 | 1980-05-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6981980A JPS56167333A (en) | 1980-05-26 | 1980-05-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56167333A JPS56167333A (en) | 1981-12-23 |
| JPS6255696B2 true JPS6255696B2 (en) | 1987-11-20 |
Family
ID=13413740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6981980A Granted JPS56167333A (en) | 1980-05-26 | 1980-05-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56167333A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0710599B2 (en) * | 1987-01-31 | 1995-02-08 | 株式会社東芝 | Thermal head |
| JPH0724275B2 (en) * | 1987-11-06 | 1995-03-15 | 三菱電機株式会社 | Semiconductor device |
| US5198685A (en) * | 1990-08-01 | 1993-03-30 | Canon Kabushiki Kaisha | Photoelectric conversion apparatus with shock-absorbing layer |
| JPH08162528A (en) * | 1994-10-03 | 1996-06-21 | Sony Corp | Interlayer insulating film structure of semiconductor device |
| JP5600698B2 (en) * | 2012-03-14 | 2014-10-01 | 株式会社 日立パワーデバイス | Power semiconductor module with SiC element |
-
1980
- 1980-05-26 JP JP6981980A patent/JPS56167333A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56167333A (en) | 1981-12-23 |
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