JPS6216022B2 - - Google Patents

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Publication number
JPS6216022B2
JPS6216022B2 JP57138340A JP13834082A JPS6216022B2 JP S6216022 B2 JPS6216022 B2 JP S6216022B2 JP 57138340 A JP57138340 A JP 57138340A JP 13834082 A JP13834082 A JP 13834082A JP S6216022 B2 JPS6216022 B2 JP S6216022B2
Authority
JP
Japan
Prior art keywords
insulating film
film
polyimide
wiring
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57138340A
Other languages
Japanese (ja)
Other versions
JPS58116755A (en
Inventor
Kiichiro Mukai
Atsushi Saiki
Yukyoshi Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57138340A priority Critical patent/JPS58116755A/en
Publication of JPS58116755A publication Critical patent/JPS58116755A/en
Publication of JPS6216022B2 publication Critical patent/JPS6216022B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554—External layer
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To prevent the erroneous operation of an integrated circuit due to alpha-ray by forming a coating film having a thickness thicker than 10mum made of polyimide resin or polyimide isoindole quinazolinedion (PII) on the region of an element. CONSTITUTION:An insulating film 21' is formed on the part of a man surface of a semiconductor substrate having a memory cell 21, and a bonding pad is formed on an insulating film 21'. Then, a coating film 23 which has a thickness thicker than 10mum made of polyimide resin or PII of less than several ppb of impurity content to become a source of generating alpha-ray is formed on the region of the memory cell 21 of an insulating substrate. Then, the semiconductor substrate is sealed with ceramic.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、詳しくは、極度に
高い信頼性を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having extremely high reliability.

〔従来の技術〕[Conventional technology]

周知のように半導体基板内に形成された半導体
装置は、表面上に形成された配線を、機械的にス
トレス、水分あるいはNaやＫイオンなど、有害
物による影響から保護するための保護膜を有して
いる。 As is well known, semiconductor devices formed within a semiconductor substrate have a protective film that protects the wiring formed on the surface from mechanical stress, moisture, and the effects of harmful substances such as Na and K ions. are doing.

これらの保護膜としては、従来、多くの材料が
提案されている。たとえば、米国特許第3953877
号には、保護膜として感光性ポリイミドを用いた
半導体装置が開示されており、アイ・イー・イ
ー・イー・ジヤーナル・オブ・ソリツド・ステー
ト・サーキツト（IEEE Journal of Solid−State
Circuit SG−13巻、No.４、第462−467頁、1984
年８月にはPIQ（日立化成株式会社登録商標、ポ
リイミド・イソインドロ・キナゾリンジオン）を
保護膜および層間絶縁膜として用いることが記さ
れている。 Many materials have been proposed for these protective films. For example, U.S. Patent No. 3953877
The issue discloses a semiconductor device using photosensitive polyimide as a protective film, and is published in the IEEE Journal of Solid-State Circuits.
Circuit SG-13, No. 4, pp. 462-467, 1984
In August 2007, it was stated that PIQ (registered trademark of Hitachi Chemical Co., Ltd., polyimide isoindolo quinazolinedione) was used as a protective film and an interlayer insulating film.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明者の検討によれば、樹脂材料からできた
保護膜は、水分によつて生ずる障害を防止する力
が低いことが見出された。また、樹脂材料中に
は、NaやＫなどアルカリイオンが少量含まれ、
半導体基板中に侵入して、半導体装置の特性を劣
化させることのあることが見出された。 According to studies conducted by the present inventors, it has been found that a protective film made of a resin material has a low ability to prevent damage caused by moisture. In addition, the resin material contains small amounts of alkali ions such as Na and K.
It has been found that these substances may penetrate into semiconductor substrates and deteriorate the characteristics of semiconductor devices.

従つて、高い信頼性を有する半導体装置を得る
ためには、保護膜の有する上記問題を解決するこ
とが必要である。 Therefore, in order to obtain a highly reliable semiconductor device, it is necessary to solve the above-mentioned problems of the protective film.

本発明の目的は、上記従来の問題を解決し、高
い信頼性を有する半導体装置を提供することであ
る。 An object of the present invention is to solve the above-mentioned conventional problems and provide a highly reliable semiconductor device.

本発明の他の目的は、機械的ストレス、水分あ
るいは樹脂中に含まれるアルカリイオンによる障
害発生のない保護膜を有する半導体装置を提供す
ることである。 Another object of the present invention is to provide a semiconductor device having a protective film that is free from damage caused by mechanical stress, moisture, or alkali ions contained in resin.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的を達成するため、本発明は、樹脂材
料、好ましくはPIQもしくはポリイミド樹脂、か
らなる第３の絶縁膜を、無機材料、好ましくは窒
化シリコンもしくはリンガラス
（phosphosilicateglass）、からなる第２の絶縁膜
上に形成するものである。 To achieve the above object, the present invention provides a third insulating film made of a resin material, preferably PIQ or polyimide resin, and a second insulating film made of an inorganic material, preferably silicon nitride or phosphosilicate glass. It is formed on a film.

〔作用〕[Effect]

窒化シリコンおよびリンガラスはアルカリイオ
ンをゲツタリングする力が大きいので、樹脂膜中
に含まれるアルカリイオンが半導体基板へ侵入す
るのを効果的に防止する。 Since silicon nitride and phosphorous glass have a strong ability to getter alkali ions, they effectively prevent alkali ions contained in the resin film from entering the semiconductor substrate.

水分についても同様であり、外気もしくは樹脂
材料中に含まれる水分は、窒化シリコンやリンガ
ラスの膜によつて通過が阻止される。 The same applies to moisture, and moisture contained in the outside air or the resin material is prevented from passing through by the silicon nitride or phosphorus glass film.

高分子樹脂膜は、外部からの機械的衝撃やスト
レスを緩和すのに有効であり、とくにPIQとポリ
イミドは弾性に富むので半導体装置の製造中にお
ける機械的衝撃やストレスを緩和し、障害発生の
防止に極めて有効である。 Polymer resin films are effective in alleviating external mechanical shocks and stress. In particular, PIQ and polyimide are highly elastic, so they can alleviate mechanical shocks and stress during the manufacturing of semiconductor devices, reducing the risk of failures. Extremely effective in prevention.

したがつて、窒化シリコンもしくはリンガラス
からなる第２の絶縁膜上にPIQもしくポリイミド
樹脂膜からなる第３の絶縁膜を形成して用いるこ
とによつて、非常に信頼性の高い半導体装置を得
ることができる。 Therefore, by forming and using a third insulating film made of PIQ or polyimide resin film on a second insulating film made of silicon nitride or phosphorous glass, a highly reliable semiconductor device can be obtained. Obtainable.

〔実施例〕〔Example〕

第１図を用いて本発明を詳細に説明する。 The present invention will be explained in detail using FIG.

ポリイミド樹脂には、少量（数ppm程度）の
アルカリイオンが不純物として含まれることがあ
る。 Polyimide resins may contain a small amount (about several ppm) of alkali ions as impurities.

この場合、とくにSiO2など無機絶縁物からな
る第１の絶縁膜１′にピンホールが存在したり、
第１の絶縁膜１′の開口部と配線１″の間の位置合
わせのずれによつて生じた部分６が、第１図に示
したように存在する場合には、第２の絶縁膜３を
設けることなしに、ポリイミドからなる第３の絶
縁膜４を第１の絶縁膜１″に形成して熱処理を行
なうと、不純物イオンが上記ピンホールや上記部
分６を通つて半導体基板１内に入り、半導体装置
の特性を低下させる。 In this case, pinholes may exist in the first insulating film 1' made of an inorganic insulator such as SiO2 , or
If a portion 6 caused by misalignment between the opening of the first insulating film 1' and the wiring 1'' exists as shown in FIG. If the third insulating film 4 made of polyimide is formed on the first insulating film 1'' without providing a heat treatment, impurity ions will pass through the pinholes and the portion 6 into the semiconductor substrate 1. and deteriorate the characteristics of semiconductor devices.

従つて、アルカリイオンをゲツタリングする力
の大きいリンガラスや窒化シリコンの膜を半導体
基板上に設け、半導体基板とポリイミド樹脂膜と
の間に介在させるのが、極めて有効である。 Therefore, it is extremely effective to provide a film of phosphorus glass or silicon nitride, which has a strong ability to getter alkali ions, on the semiconductor substrate and interpose it between the semiconductor substrate and the polyimide resin film.

すなわち、第１図に示したように、リンガラス
膜３をCVD法によつて半導体基板１上形成し、
その上にポリイミド樹脂膜４を形成する。 That is, as shown in FIG. 1, a phosphor glass film 3 is formed on a semiconductor substrate 1 by CVD method,
A polyimide resin film 4 is formed thereon.

リンガラス膜のリン濃度は３モル％〜12モル
％、膜厚は約0.3〜1.5μｍとするのが好ましい。 The phosphorus glass film preferably has a phosphorus concentration of 3 mol % to 12 mol % and a film thickness of about 0.3 to 1.5 μm.

すなわち、リンガラス膜がアルカリイオンをゲ
ツタリングする力は、リン濃度に依存し、３モル
％以上ならばアルカリイオンをゲツタリングでき
る。 That is, the power of the phosphorus glass film to getter alkali ions depends on the phosphorus concentration, and if the phosphorus concentration is 3 mol % or more, alkali ions can be gettered.

一方、リン濃度が高くなると吸湿性が高くな
り、リン濃度が12モル％以上になるとAl配線の
腐食が生じるようになる。 On the other hand, as the phosphorus concentration increases, the hygroscopicity increases, and when the phosphorus concentration exceeds 12 mol%, corrosion of the Al wiring begins to occur.

リンガラス膜の膜厚は、半導体基板を実質的に
完全に覆うために少なくとも0.3μｍは必要であ
る。さらにリンガラス膜自体の内部応力によるク
ラツクが発生しないようにするためには、膜厚が
1.5μｍ以下であることが好ましい。 The thickness of the phosphor glass film is required to be at least 0.3 μm in order to substantially completely cover the semiconductor substrate. Furthermore, in order to prevent cracks from occurring due to the internal stress of the phosphor glass film itself, the film thickness must be increased.
It is preferably 1.5 μm or less.

本実施例においては、16−kb・NMOSダイナ
ミツクRAMが用いられ、４モル％を含む厚さ1.2
μｍのリンガラス膜３が形成れた。次に、上記リ
ンガラス膜３のボンデイングパツド部分に、通常
のホトエツチングによつて開口部を形成した。そ
の後で、開口部を有する厚さ４μｍのポリイミド
膜４を形成した。 In this example, a 16-kb NMOS dynamic RAM is used, with a thickness of 1.2 mm containing 4 mol%.
A phosphor glass film 3 with a thickness of μm was formed. Next, an opening was formed in the bonding pad portion of the phosphor glass film 3 by ordinary photoetching. Thereafter, a 4 μm thick polyimide film 4 having an opening was formed.

すなわち、周知のスピンオン法によつてポリイ
ミド樹脂を半導体基板表面に塗布し、200℃、１
時間の熱処理を行なつて半硬化し、ヒドラジン・
ハイドレイトを用いたホトエツチングによつてボ
ンデイングパツドの部分に開口部を形成した。そ
の後、350℃、１時間および450℃、10分の熱処理
を行なつて樹脂を硬化させた。この熱処理は、窒
素または不活性ガス中で行なうことが好ましい。 That is, polyimide resin is applied to the surface of a semiconductor substrate by the well-known spin-on method, and heated at 200°C for 1 hour.
Semi-hardened by heat treatment for hours, hydrazine
An opening was formed in the bonding pad area by photoetching using hydrate. Thereafter, heat treatment was performed at 350°C for 1 hour and at 450°C for 10 minutes to harden the resin. This heat treatment is preferably performed in nitrogen or an inert gas.

リンガラス膜３を形成せず、第１の絶縁膜１′
のピンホールおよび先に説明した位置合わせのず
れによつて生じた部分６が存在した場合、ポリイ
ミド樹脂膜４を形成して400℃以上の熱処理を行
なうと、0.5〜40％の歩留まり低下が認められ
た。 The first insulating film 1' is formed without forming the phosphor glass film 3.
If there are pinholes and the portion 6 caused by the misalignment described above, when the polyimide resin film 4 is formed and heat treated at 400°C or higher, a yield drop of 0.5 to 40% is observed. It was done.

しかし、本実施例では、ポリイミド膜形成によ
る歩留まり低下は生じなかつた。 However, in this example, there was no decrease in yield due to the formation of the polyimide film.

リンガラス膜３のかわりに窒化シリコン膜を用
いても、同様の結果が確認された。 Similar results were confirmed when a silicon nitride film was used instead of the phosphorus glass film 3.

窒化シリコン膜は、たとえばスパツタリングや
プラズマCVDなど既知の方法によつて形成でき
るが、プラズマCVDによつて形成するのが好ま
しい。 The silicon nitride film can be formed by a known method such as sputtering or plasma CVD, but it is preferably formed by plasma CVD.

窒化シリコン膜の膜厚は0.2〜３μｍの範囲と
するのが好ましい。半導体基板をほぼ完全に覆う
ためには、窒化シリコン膜の膜厚は最低0.2μｍ
は必要である。 The thickness of the silicon nitride film is preferably in the range of 0.2 to 3 μm. In order to almost completely cover the semiconductor substrate, the thickness of the silicon nitride film must be at least 0.2 μm.
is necessary.

膜厚の上限は、下記のプラズマエツチングを実
施できる範囲として、約３μｍとするのが好まし
い。 The upper limit of the film thickness is preferably about 3 .mu.m, which is a range in which the following plasma etching can be carried out.

窒化シリコン膜の開口部は、たとえばCF4を用
いたプラズマ形成することができる。 The opening in the silicon nitride film can be formed by plasma using, for example, CF 4 .

第１図において記号５はボンデイングワイヤを
示す。 In FIG. 1, symbol 5 indicates a bonding wire.

上記と同じ効果は、ポリイミド樹脂のかわりに
PIQ樹脂を用いても、また、樹脂膜をポツテイン
グによつて形成しても、同様に認められる。 The same effect as above can be obtained by using polyimide resin instead of polyimide resin.
The same effect can be observed even if PIQ resin is used or the resin film is formed by potting.

さらに、第１図に示したように、配線１″が第
１の絶縁膜１′上に形成され、上記配線１″の所定
の部分は半導体基板１の所定領域と電気的に接続
されている。 Further, as shown in FIG. 1, a wiring 1'' is formed on the first insulating film 1', and a predetermined portion of the wiring 1'' is electrically connected to a predetermined region of the semiconductor substrate 1. .

第２の絶縁膜３と第３の絶縁膜４の積層膜は開
口部２を有している。配線１″の表面の所定の部
分は上記開口部２を介して露出されるが、配線の
他の部分は、上記第２の絶縁膜３および第３の絶
縁膜４の積層膜によつて覆われる。 The laminated film of the second insulating film 3 and the third insulating film 4 has an opening 2 . A predetermined part of the surface of the wiring 1'' is exposed through the opening 2, but other parts of the wiring are covered with the laminated film of the second insulating film 3 and the third insulating film 4. be exposed.

ボンデイングワイヤ５は窓２内で配線１″の上
記露出された部分と接続されている。 The bonding wire 5 is connected to the exposed portion of the wiring 1'' within the window 2.

〔発明の効果〕〔Effect of the invention〕

配線１″はボンデイング部分以外は、窒化シリ
コンもしくはリンガラスからなる第２の絶縁膜３
およびPIQもしくはポリイミドからなる第３の絶
縁膜４によつて覆われているので、半導体装置の
製造中において、配線は効果的に保護される。 The wiring 1'' is covered with a second insulating film 3 made of silicon nitride or phosphorus glass, except for the bonding part.
Since the wiring is covered with the third insulating film 4 made of PIQ or polyimide, the wiring is effectively protected during the manufacture of the semiconductor device.

すなわち、PIQとポリイミドは弾性に富んでい
るため、PIQもしくはポリイミドからなる第３の
絶縁膜は、機械的衝撃やストレスを効果的に吸収
できる。 That is, since PIQ and polyimide are highly elastic, the third insulating film made of PIQ or polyimide can effectively absorb mechanical shock and stress.

また、窒化シリコンやリンガラスからなる第２
の絶縁膜はアルカリイオンのみではなく、水分の
透過阻止にも有効である。 In addition, a second layer made of silicon nitride or phosphorus glass is also used.
The insulating film is effective in blocking not only alkali ions but also moisture.

従つて、本発明によれば、機械的な衝撃やスト
レスあるいは水分およびアルカリイオンによる障
害は効果的に防止され、非常にすぐれた信頼性を
持つた半導体装置が得られる。 Therefore, according to the present invention, damage caused by mechanical shock and stress or moisture and alkali ions can be effectively prevented, and a semiconductor device with extremely high reliability can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示す断面図であ
る。 １……半導体基板、１′……第１の絶縁膜、
１″……配線、２……開口部、３……第２の絶縁
膜、４……第３の絶縁膜、５……ポンデイングワ
イヤ、６……位置合わせのずれによつて生じた部
分。 FIG. 1 is a sectional view showing one embodiment of the present invention. 1... Semiconductor substrate, 1'... First insulating film,
1''... Wiring, 2... Opening, 3... Second insulating film, 4... Third insulating film, 5... Ponding wire, 6... Portion caused by misalignment. .

Claims (1)

【特許請求の範囲】[Claims] １ 半導体基板の主表面上に形成された開口部を
有する無機絶縁膜である第１の絶縁膜と、上記第
１の絶縁膜上に形成され、上記開口部を介して上
記半導体基板の主表面と電気的に接続された配線
と、上記第１の絶縁膜および上記配線の所望部分
上に、上記配線の一部が露出されるように形成さ
れたリンガラスおよび窒化シリコンからなる群か
ら選択された材料からなる第２の絶縁膜と、上記
配線の露出された部分に電気的に接続されたボン
デイングワイヤと、上記第２の絶縁膜上に形成さ
れたポリイミド・イソインドロ・キナゾリンジオ
ン樹脂およびポリイミド樹脂からなる群から選択
された材料からなる第３の絶縁膜を有することを
特徴とする半導体装置。1. A first insulating film that is an inorganic insulating film having an opening formed on the main surface of the semiconductor substrate; and a wiring selected from the group consisting of phosphor glass and silicon nitride formed on the first insulating film and a desired portion of the wiring so that a portion of the wiring is exposed. a bonding wire electrically connected to the exposed portion of the wiring; a polyimide/isoindolo/quinazolinedione resin and a polyimide resin formed on the second insulating film; A semiconductor device comprising a third insulating film made of a material selected from the group consisting of:
JP57138340A 1982-08-09 1982-08-09 Semiconductor device and manufacture thereof Granted JPS58116755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57138340A JPS58116755A (en) 1982-08-09 1982-08-09 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57138340A JPS58116755A (en) 1982-08-09 1982-08-09 Semiconductor device and manufacture thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP14237578A Division JPS5568659A (en) 1978-11-20 1978-11-20 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS58116755A JPS58116755A (en) 1983-07-12
JPS6216022B2 true JPS6216022B2 (en) 1987-04-10

Family

ID=15219623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57138340A Granted JPS58116755A (en) 1982-08-09 1982-08-09 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS58116755A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103656A (en) * 2005-10-04 2007-04-19 Denso Corp Semiconductor device and its manufacturing method

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0230131A (en) * 1988-07-19 1990-01-31 Seiko Epson Corp Semiconductor device
JP4596011B2 (en) * 2008-01-09 2010-12-08 トヨタ自動車株式会社 Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643614A (en) * 1979-09-17 1981-04-22 Nippon Telegr & Teleph Corp <Ntt> Production of plug for optical fiber connector

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5643614A (en) * 1979-09-17 1981-04-22 Nippon Telegr & Teleph Corp <Ntt> Production of plug for optical fiber connector

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103656A (en) * 2005-10-04 2007-04-19 Denso Corp Semiconductor device and its manufacturing method
JP4645398B2 (en) * 2005-10-04 2011-03-09 株式会社デンソー Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
JPS58116755A (en) 1983-07-12

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