JPS628035B2 - - Google Patents

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Publication number
JPS628035B2
JPS628035B2 JP56075291A JP7529181A JPS628035B2 JP S628035 B2 JPS628035 B2 JP S628035B2 JP 56075291 A JP56075291 A JP 56075291A JP 7529181 A JP7529181 A JP 7529181A JP S628035 B2 JPS628035 B2 JP S628035B2
Authority
JP
Japan
Prior art keywords
film
resin
polyimide
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56075291A
Other languages
Japanese (ja)
Other versions
JPS57188853A (en
Inventor
Koji Fujisaki
Shunichi Numata
Akio Nishikawa
Hiroshi Suzuki
Takeshi Komaru
Daisuke Makino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Hitachi Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP56075291A priority Critical patent/JPS57188853A/en
Priority to GB8120607A priority patent/GB2098800B/en
Priority to DE3126361A priority patent/DE3126361C2/en
Publication of JPS57188853A publication Critical patent/JPS57188853A/en
Publication of JPS628035B2 publication Critical patent/JPS628035B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556—Protection against radiation, e.g. light or electromagnetic waves against alpha rays
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
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  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
  • Paints Or Removers (AREA)
  • Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An organic polymer film, e.g. aromatic polyimide resin 6, having a moisture permeability of 1 x 10<-7>g.cm/cm<2>.hr or less is formed between the encapsulating resin 8 of a semiconductor device, and a moisture absorption member 2, 3, 4 such as phosphosilicate glass or SiO2 film, a hygroscopic polyimide film or a corrodible aluminium wiring conductor. The low moisture permeability film is formed on the surface of the semiconductor device either directly or through the medium of other material, and may serve as a protective or possivation film, an alpha -ray shield or an inter- layer insulating film. Methods for the production of the low moisture permeability film are described, and the use of fillers such as silica or alumina is disclosed. <IMAGE>

Description

【発明の詳細な説明】[Detailed description of the invention]

本発明は、樹脂封止型半導体装置に係り、特に
パシベーシヨン用、PSG膜保護用、α線遮蔽用ま
たは多層配線絶縁用材料として低透湿率の有機高
分子膜例えばポリイミド樹脂を有する半導体素子
を封止用樹脂でモールドしてなる半導体装置の改
良に関する。 半導体基板に形成されたpn接合露出表面は、
雰囲気の影響を敏感に受け易いため、各種安定化
材をコーテイングして安定化される。無機パシベ
ーシヨン材の二酸化けい素、窒化けい素、アルミ
ナ、ガラスなどに代えて、低温で安定化処理が行
える利点のあるポリイミド樹脂によるパシベーシ
ヨン技術が、日本特開昭50−8469号公報に開示さ
れている。この公報に開示されているポリイミド
樹脂は、ピロメリツト酸二無水物、ベンゾフエノ
ンテトラカルボン酸二無水物、ジアミノジフエニ
ルエーテル及びジアミノジフエニルエーテルモノ
カルボンアミドから得られたもの（ポリイミドイ
ソインドロキナゾリンジオン樹脂）が記載されて
いる。そして、このポリイミド樹脂と半導体基板
等との接着性をよくするため、アミノシランカツ
プリング材で半導体基板等を前処理することが記
載されている。 日本特開昭50−6279号公報及び同50−6280号公
報には、レジン封止型半導体装置において、封止
樹脂とリードフレーム、半導体集積回路チツプ、
リード線との間をポリイミド樹脂で覆い外界から
の水分の浸入による集積回路装置の故障を減少す
る技術が開示されている。また、USPNo.4079511
にも水分が集積回路チツプに到達しないように封
入材で被覆した半導体装置が示されている。 更に、USPNo.4001870、USPNo.4017886、USPNo.
4040083、USPNo.4060828には、多層配線における
絶縁膜の材料としてポリイミド樹脂を用いた技術
が開示されている。そして、USPNo.4040083に
は、ポリイミド樹脂とSiO2膜との接着性を改善
し、半導体装置の耐湿性を改善するために、アル
ミニウムキレート化合物で半導体チツプを前処理
している。 また、半導体装置の耐湿性を向上させる方法と
して、ナトリウムイオン等を阻止する働きを有す
るリンガラス（Phosphosilicate glass、以下PSG
と略称する。）を保護膜に用いる方法が一般に賞
用されている。 このPSGは、CVD（Chemical Vapour
Deposition）法により、シラン及びホスフイン等
のSi源及びＰ源となるガスを混合し、酸化して素
子上に堆積させるものであり、この際リン濃度を
高くすることにより、イオン阻止能を高め、かつ
堆積した膜に後処理で温度をかけてフロー（流
動）させることが可能な膜となる。このようにフ
ローさせると、膜のかどが丸まり、また配線上等
の段差がゆるやかになる等により、配線が断線し
難くなり、また、素子の活性部におけるワイヤボ
ンデイングが可能になる等の有利性が得られる。 しかしながら、リン濃度を高くするとPSGは水
に溶出する傾向が強くなり、リン濃度が10数モル
％になると潮解性を示すに至る。したがつて、リ
ン濃度の高いPSGになるほど耐湿性がいつそう重
要となり、特にガラスフローが可能なリン濃度10
モル％以上の場合には重大な問題となる。 一方、高集積度の半導体メモリー装置における
封止材料中の放射性元素、ウラン及びトリウムか
ら放出されるα線により生じるソフトエラーを防
ぐため、半導体メモリー素子の回路側に、α線遮
蔽層を形成する技術があり、特にこの遮蔽材とし
て、ウラン及びトリウムの含有率を非常に少なく
したポリイミド樹脂を用いた樹脂封止型半導体メ
モリー装置も提案されている。 これら従来技術によれば、樹脂封止型半導体装
置における最大の問題点（セラミツク封止やガラ
ス封止に比較して）は、樹脂自体が水分を通す性
質があること及び樹脂と半導体基板、樹脂と金属
線の間にgapができ、水分を通す原因となるた
め、耐湿性に劣ることであると認識されている。
そのため、例えばアンダーコート樹脂と半導体チ
ツプ、及びPSG保護膜や金属線との間をカツプリ
ング材などによつて処理することが行われる。 一般的な傾向として、半導体装置の分野で用い
られる樹脂材料の耐湿性が良いことが要求される
ことは知られている。例えばパシベーシヨン材と
してそれ自身耐湿性又は撥水性のシリコーン樹脂
が広く用いられていることはその一例である。し
かしシリコーン樹脂は、水分の透過率が大きいた
め、半導体素子上に形成したSiO2膜、PSG膜及
び／又はポリイミド系の高分子膜などの高吸湿率
材料に外界から水分が浸入して到達するのを抑制
できないことが問題である。 各種ポリイミド樹脂、ことに前記ポリイミドイ
ソインドロキナゾリンジオン樹脂は、その耐熱
性、絶縁性、塗膜形成性、作業性などの優れた特
徴のほか、半導体チツプや金属膜に対する接着力
もあつて、集積回路の分野で広く用いられるよう
になつた。 しかし、本発明者らは、上記ポリイミドイソイ
ンドロキナゾリンジオン樹脂をはじめ、多くのポ
リイミド樹脂を用いた半導体装置について検討し
た結果、長期間の過酷な耐湿性テストで故障を示
すものがあることが分かつた。その原因を探るた
め本発明者は、封止樹脂の耐湿性、封止樹脂とア
ンダーコート又は安定化膜としてのポリイミド樹
脂膜との接着性、ポリイミド樹脂膜と半導体チツ
プ及びPSG保護膜や金属線などとの接着力などに
ついて検討したが、故障の最大の原因は、ポリイ
ミド樹脂自体の透湿性であることを発見した。従
来の考えでは、半導体チツプや金属線とポリイミ
ド樹脂膜が強固に密着していれば、水分が透過で
きないとされていた。しかしいくらカツプリング
材で半導体チツプを前処理しても、水分による故
障が生じることは、単に半導体素子とポリイミド
樹脂との接着力を改善しただけでは解決できない
という結論に到つた。即ちこの故障はポリイミド
樹脂が水分を透過させるために起ると考えられ
る。 本発明の目的は、耐湿性特に透湿性が著しく改
善された安定化膜、多層配線用絶縁膜又はα線遮
蔽層をそなえた樹脂封止型半導体装置を提供する
ことである。本発明は特に吸湿率の大きいSiO2
膜、PSG保護膜、ポリイミドイソインドロキナゾ
リンジオンなどの有機高分子膜を、半導体素子の
pn接合面又はアルミニウム配線上に形成した半
導体装置において、それら高吸湿率材料に外界か
ら水分が到達しないように、又は水分の到達を抑
制するように、低透湿率の高分子膜をオーバーコ
ートした樹脂封止型半導体装置を提供するもので
ある。 本発明の一例によれば、半導体基板と、その基
板上に形成された絶縁膜と、その絶縁膜上に形成
された金属導体及びその導体と接して形成された
PSG保護層及びポリイミド樹脂膜を有する機能素
子と、その機能素子を機械的に保護し、パツケー
ジする封止樹脂、及びその封止樹脂から延びてい
る少なくとも１つの外部リードとを有するものに
おいて、上記ポリイミド樹脂は１×10-7ｇ・cm／
cm2・ｈ以下の透湿率を有する芳香族ポリイミド樹
脂である半導体装置が提供される。 以下本発明を図面を参照しつつ詳細に説明す
る。 第１図において、１はシリコン等の半導体基板
を示し、その表面層には例えばpnp型のトランジ
スタが形成されている。この半導体基板１の表面
にはエミツタ、ベース、コレクタ間の絶縁及び保
護用の二酸化けい素膜２が形成され、さらにベー
ス電極３、エミツタ電極４がアルミニウム蒸着膜
により形成されている。このプレーナ型トランジ
スタをパツケージングする場合、基板１をタブリ
ード７の先端に固定し、素子の他の電極とリード
線間を金あるいはアルミニウムのワイヤ５により
ボンデイングを行ない、アンダーコート用樹脂６
で被覆保護した後、機械的強度を持たせるため
と、外気から保護するためにタブリード７の先端
部を含む半導体基板１を樹脂８によりモールドし
ている。 第２図は集積回路を樹脂封止してなる半導体装
置で、半導体集積回路１１はセラミツクなどから
なるパツケージ１５の上に固定され、集積回路片
１１の周囲に設けられたボンデイングパツド１４
と、パツケージの外部接続リード端子１２とは、
細い金属線１３で接続されている。この集積回路
片１１、細い金属線１３、金属線１３と接続した
リード端子１２ならびにボンデイングパツド１４
を全体的に覆うように、耐湿性ポリイミド樹脂か
らなるアンダーコート膜９を設け、さらにその外
側を成形樹脂１０により封止されている。本発明
は、厚膜回路にも適用できる。 第３図は、半導体基板表面に２層の配線構造を
有してなる樹脂封止型半導体装置の一実施例を示
す。 表面に二酸化ケイ素膜４２を有する半導体基板
４１上に金属被膜を形成し、これに周知のエツチ
ング法を用いて不要部分の金属を除去して、所望
の配線パターンを有する第１の導体層４３を設け
る。この導体層４３は二酸化ケイ素膜４２の所定
の場所に設けたスルーホール４８を介して半導体
素子と電気的に接続される。次に二酸化ケイ素膜
４７を化学気相成長法あるいは高周波スパツタリ
ング法などの公知の方法によつて、層４３、層４
２の上に被膜したのち、導体の接続に必要な部分
の二酸化ケイ素膜にスルーホールを形成した。 次にアミノシラン化合物の膜４４を形成した。
更に、ポリイミド樹脂膜４５を形成した。このポ
リイミド膜の所定の部分をエツチングして第１導
体層４３の一部を露出させた。この上に第２導体
層４６を形成した。この例では、絶縁層が二酸化
けい素４７及びポリイミド樹脂４５との二層構造
となつている。 第４図は半導体メモリー素子とそのレジンパツ
ケージの間にα線遮蔽層を有するデユアル−イン
−ライン型レジンパツケージ半導体メモリー装置
の断面図である。第４図において、７１は半導体
メモリー素子でシリコンチツプからなり、７２の
シリコンチツプ支持体に固定されている。７３は
リードで、メモリー素子７１の電極パツドとの間
をボンデイングワイヤ７４で接続している。７５
は封止樹脂、７６はα線遮蔽層である。この実施
例において、α線遮蔽層７６は、メモリー素子の
表面に塗布され、乾燥硬化されている。そしてそ
の遮蔽層の上に低透湿率のオーバーコート７７を
形成して水分の浸入を阻止する。封止樹脂７５は
エポキシ樹脂などの熱硬化性樹脂で形成される。 半導体の耐湿性としては、80℃／90％RHで
1000時間の試験に耐えなければならないが、この
試験に合格するポリイミド樹脂は、いずれも25
℃／75％RHにおける透湿率は１×10-7ｇ・cm／
cm2・ｈ以下であつた。そのような半導体装置とし
ては、一般式が （式（）中、Ｒは脂肪族、または芳香族基、−
R′−は The present invention relates to a resin-sealed semiconductor device, and particularly to a semiconductor element having an organic polymer film with a low moisture permeability, such as a polyimide resin, as a material for passivation, PSG film protection, α-ray shielding, or multilayer wiring insulation. This invention relates to improvements in semiconductor devices molded with sealing resin. The exposed surface of a pn junction formed on a semiconductor substrate is
Since it is sensitive to the influence of the atmosphere, it is stabilized by coating it with various stabilizing materials. In place of inorganic passivation materials such as silicon dioxide, silicon nitride, alumina, and glass, a passivation technology using polyimide resin, which has the advantage of being able to be stabilized at low temperatures, was disclosed in Japanese Patent Application Laid-Open No. 8469/1983. There is. The polyimide resin disclosed in this publication is one obtained from pyromellitic dianhydride, benzophenonetetracarboxylic dianhydride, diaminodiphenyl ether, and diaminodiphenyl ether monocarbonamide (polyimide isoindoquinazoline dione resin). It is also described that in order to improve the adhesion between this polyimide resin and a semiconductor substrate, etc., the semiconductor substrate, etc. is pretreated with an aminosilane coupling material. Japanese Unexamined Patent Application Publication No. 50-6279 and No. 50-6280 disclose a resin-encapsulated semiconductor device that includes a sealing resin, a lead frame, a semiconductor integrated circuit chip,
A technique has been disclosed in which the lead wires are covered with a polyimide resin to reduce failures of the integrated circuit device due to moisture infiltration from the outside world. Also, USP No.4079511
Also shown is a semiconductor device coated with an encapsulant to prevent moisture from reaching the integrated circuit chip. Furthermore, USP No. 4001870, USP No. 4017886, USP No.
No. 4040083 and USP No. 4060828 disclose a technology using polyimide resin as a material for an insulating film in multilayer wiring. In USP No. 4040083, semiconductor chips are pretreated with an aluminum chelate compound in order to improve the adhesion between polyimide resin and SiO 2 film and improve the moisture resistance of semiconductor devices. In addition, as a method to improve the moisture resistance of semiconductor devices, phosphosilicate glass (hereinafter referred to as PSG), which has the function of blocking sodium ions, etc.
It is abbreviated as. ) is generally used as a protective film. This PSG is a CVD (Chemical Vapor
By using the deposition method, gases such as silane and phosphine, which serve as a Si source and a P source, are mixed, oxidized, and deposited on the device. In addition, the deposited film becomes a film that can be caused to flow by applying temperature in post-treatment. Flowing in this way has advantages such as rounding the edges of the film and making the steps on the wiring more gentle, making it difficult for the wiring to break, and making wire bonding possible in the active area of the device. is obtained. However, as the phosphorus concentration increases, PSG tends to dissolve into water, and when the phosphorus concentration reaches 10-odd mol%, it becomes deliquescent. Therefore, the higher the phosphorus concentration of PSG, the more important moisture resistance becomes, especially for PSG with a phosphorus concentration of 10, which allows glass flow.
If it exceeds mol%, it becomes a serious problem. On the other hand, in order to prevent soft errors caused by alpha rays emitted from radioactive elements, uranium, and thorium in the sealing material in highly integrated semiconductor memory devices, an alpha ray shielding layer is formed on the circuit side of the semiconductor memory element. In particular, a resin-sealed semiconductor memory device using a polyimide resin containing extremely low uranium and thorium content has been proposed as a shielding material. According to these conventional technologies, the biggest problem with resin-sealed semiconductor devices (compared to ceramic encapsulation or glass encapsulation) is that the resin itself has a property of allowing moisture to pass through, and that the resin and semiconductor substrate It is recognized that moisture resistance is poor because a gap is formed between the wire and the metal wire, causing moisture to pass through.
Therefore, for example, processing is performed between the undercoat resin and the semiconductor chip, the PSG protective film, or the metal wire using a coupling material or the like. It is known that as a general trend, resin materials used in the field of semiconductor devices are required to have good moisture resistance. For example, silicone resins, which are themselves moisture resistant or water repellent, are widely used as passivation materials. However, silicone resin has a high moisture permeability, so moisture from the outside world can enter and reach high moisture absorption materials such as SiO 2 films, PSG films, and/or polyimide polymer films formed on semiconductor devices. The problem is that it cannot be suppressed. Various polyimide resins, especially the above-mentioned polyimide isoindoquinazolinedione resins, have excellent properties such as heat resistance, insulation, film forming properties, and workability, as well as adhesion to semiconductor chips and metal films, making them a popular choice for integration. It has come to be widely used in the field of circuits. However, as a result of studying semiconductor devices using many polyimide resins, including the above-mentioned polyimide isoindoquinazolinedione resin, the present inventors found that some semiconductor devices failed during long-term, severe moisture resistance tests. I understand. In order to investigate the cause, the present inventor investigated the moisture resistance of the sealing resin, the adhesion between the sealing resin and the polyimide resin film as an undercoat or stabilizing film, the relationship between the polyimide resin film and the semiconductor chip, the PSG protective film, and the metal wire. We investigated the adhesive strength of polyimide resin, etc., and discovered that the biggest cause of failure was the moisture permeability of the polyimide resin itself. The conventional thinking was that if a semiconductor chip or metal wire and a polyimide resin film were tightly adhered to each other, moisture would not be able to pass through them. However, no matter how much the semiconductor chip is pretreated with a coupling material, it was concluded that failure due to moisture cannot be solved simply by improving the adhesive strength between the semiconductor element and the polyimide resin. That is, it is thought that this failure occurs because the polyimide resin allows moisture to permeate through it. An object of the present invention is to provide a resin-sealed semiconductor device equipped with a stabilizing film, an insulating film for multilayer wiring, or an α-ray shielding layer, which has significantly improved moisture resistance, particularly moisture permeability. The present invention is particularly suitable for SiO 2 which has a high moisture absorption rate.
film, PSG protective film, polyimide isoindoquinazoline dione, and other organic polymer films for semiconductor devices.
In semiconductor devices formed on p-n junction surfaces or aluminum wiring, a polymer film with low moisture permeability is overcoated to prevent or suppress moisture from reaching these high moisture absorption materials from the outside world. The present invention provides a resin-sealed semiconductor device. According to an example of the present invention, a semiconductor substrate, an insulating film formed on the substrate, a metal conductor formed on the insulating film, and a metal conductor formed in contact with the conductor
The device comprising a functional element having a PSG protective layer and a polyimide resin film, a sealing resin that mechanically protects and packages the functional element, and at least one external lead extending from the sealing resin. Polyimide resin is 1×10 -7 g・cm/
A semiconductor device made of aromatic polyimide resin having a moisture permeability of cm 2 ·h or less is provided. The present invention will be described in detail below with reference to the drawings. In FIG. 1, reference numeral 1 indicates a semiconductor substrate made of silicon or the like, and a pnp type transistor, for example, is formed on its surface layer. A silicon dioxide film 2 for insulation and protection between the emitter, base, and collector is formed on the surface of the semiconductor substrate 1, and furthermore, a base electrode 3 and an emitter electrode 4 are formed of an aluminum vapor-deposited film. When packaging this planar transistor, the substrate 1 is fixed to the tip of the tab lead 7, and bonding is performed between the other electrodes of the element and the lead wires using gold or aluminum wires 5.
After covering and protecting the semiconductor substrate 1 with a resin 8, the semiconductor substrate 1 including the tip of the tab lead 7 is molded with a resin 8 in order to provide mechanical strength and protect it from the outside air. FIG. 2 shows a semiconductor device in which an integrated circuit is sealed with resin, in which a semiconductor integrated circuit 11 is fixed on a package 15 made of ceramic or the like, and a bonding pad 14 provided around the integrated circuit piece 11 is used.
and the external connection lead terminal 12 of the package.
They are connected by a thin metal wire 13. This integrated circuit piece 11, a thin metal wire 13, a lead terminal 12 connected to the metal wire 13, and a bonding pad 14
An undercoat film 9 made of moisture-resistant polyimide resin is provided to cover the entire surface, and the outside of the undercoat film 9 is sealed with a molded resin 10. The present invention can also be applied to thick film circuits. FIG. 3 shows an embodiment of a resin-sealed semiconductor device having a two-layer wiring structure on the surface of a semiconductor substrate. A metal film is formed on a semiconductor substrate 41 having a silicon dioxide film 42 on its surface, and unnecessary portions of the metal are removed using a well-known etching method to form a first conductor layer 43 having a desired wiring pattern. establish. This conductor layer 43 is electrically connected to the semiconductor element through a through hole 48 provided at a predetermined location in the silicon dioxide film 42. Next, the silicon dioxide film 47 is deposited on the layers 43 and 4 by a known method such as chemical vapor deposition or high frequency sputtering.
After coating on the silicon dioxide film, through holes were formed in the silicon dioxide film in the areas necessary for connecting the conductor. Next, a film 44 of an aminosilane compound was formed.
Furthermore, a polyimide resin film 45 was formed. A predetermined portion of this polyimide film was etched to expose a portion of the first conductor layer 43. A second conductor layer 46 was formed on this. In this example, the insulating layer has a two-layer structure of silicon dioxide 47 and polyimide resin 45. FIG. 4 is a cross-sectional view of a dual-in-line resin package semiconductor memory device having an α-ray shielding layer between a semiconductor memory element and its resin package. In FIG. 4, a semiconductor memory element 71 is made of a silicon chip and is fixed to a silicon chip support 72. A lead 73 is connected to an electrode pad of the memory element 71 by a bonding wire 74. 75
76 is a sealing resin, and 76 is an α-ray shielding layer. In this embodiment, the alpha-ray shielding layer 76 is applied to the surface of the memory element and dried and cured. Then, an overcoat 77 having a low moisture permeability is formed on the shielding layer to prevent moisture from entering. The sealing resin 75 is made of thermosetting resin such as epoxy resin. The humidity resistance of semiconductors is 80℃/90%RH.
Polyimide resins that pass this test must withstand a 1000-hour test.
Moisture permeability at ℃/75%RH is 1×10 -7 g・cm/
It was less than cm2・h. For such a semiconductor device, the general formula is (In formula (), R is an aliphatic or aromatic group, -
R′− is

【式】およびま たは ｎは整数を表わす）で示される有機高分子膜を、
直接または他の絶縁材料を介して設けた樹脂封止
型半導体装置がある。 尚、[expression] and or n represents an integer),
There are resin-sealed semiconductor devices that are provided directly or through other insulating materials. still,

【式】としては、通常[Formula] is usually

【式】およ びまたは[Formula] and Bi or

【式】が選ばれる。 本発明によれば、水に対して腐食性物質のアル
ミ配線導体や水に対して溶出性を有するPSG保護
層などの上に、上記一般式（）で示される特定
のポリイミド樹脂膜を設けてアルミ配線層やPSG
保護層などの耐湿性を向上させ、良好な特性（経
時故障率の少ない）を有する樹脂封止型半導体装
置を提供することができる。またpn接合を有す
る半導体素子において、pn接合の露呈する半導
体表面を上記ポリイミド樹脂膜で覆うことによ
り、外気の水分による特性劣化が生じない優れた
素子を提供することができる。 本発明による上記コート膜の厚さは、１〜300
μｍに選ばれ、その後、成形材料でモールドされ
る。成形材料樹脂の厚さは、一般に0.5〜５mm程
度に選ばれる。 高集積度を有する半導体メモリー素子にα線が
入射すると誤動作（ソフトエラー）を起す問題が
ある。このα線は、封止材料であるセラミツク、
金属あるいはモールド樹脂などに含まれる微量の
ウラン及びトリウムな主な線源である。したがつ
て、この封止材料からウラン及びトリウムを除去
してやれば上述の問題は解決するわけである。そ
して、封止材料を精製することによつて、ウラン
及びトリウムの含量を極度に少なくすることが試
みられている。 一方、保護コート膜によりα線を遮蔽する方法
は種々試みられており、半導体装置がメモリーの
場合には、本発明のポリイミド膜の厚さを35μｍ
以上に選べば、α線によるソフトエラーを防止す
ることが可能である。この際、保護コート膜の場
合も、封止材料と同様にウラン、トリウムの含有
量が0.1ppb以下になるよう精製すれば、ポリイ
ミド樹脂自身からのα線の発生は実際上問題にな
らない。精製は、モノマや溶媒を蒸留、昇華、再
結晶、抽出などによつて行うことが便利である。
また、耐湿試験時の腐食、リークなどを少なくす
るため、ナトリウムの含有量は1ppm以下になる
よう精製するが、上記の精製と同じ工程で行うこ
とが可能である。 本発明における前記一般式（）で表わされる
ポリイミド樹脂あるいはその前駆体であるポリア
ミド酸樹脂は、芳香族ジアミンと芳香族テトラカ
ルボン酸二無水物とを等モルの割合で反応させる
方法で得られる。例えば溶液重縮合法などによつ
て達成することができる。 溶液重合法においては反応溶媒が用いられる
が、この溶媒としては芳香族ジアミンまたは芳香
族テトラカルボン酸二無水物の両方を溶解しうる
ものでなければならない。本発明において使用す
る反応溶媒を例示すると、Ｎ・Ｎ−ジメチルホル
ムアミド、Ｎ・Ｎ−ジエチルホルムアミド、ジメ
チルスルホキシド、Ｎ・Ｎ−ジメチルアセトアミ
ド、Ｎ・Ｎ−ジエチルアセトアミド、Ｎ−メチル
−２−ピロリドンなどがあげられる。反応溶媒は
溶解操作を容易にするなど必要に応じて２種以上
混合して用いることもできる。 本発明における芳香族テトラカルボン酸二無水
物の具体例を挙げると、例えばピロメリツト酸二
無水物（PMDA）、ベンゾフエノンテトラカルボ
ン酸二無水物（BTDA）、１・４・５・８−ナフ
タレンテトラカルボン酸二無水物、２・３・６・
７−ナフタレンテトラカルボン酸二無水物、１・
２・５・６−ナフタレンテトラカルボン酸二無水
物、３・3′・４・4′−ジフエニルテトラカルボン
酸二無水物、２・２・３・3′−ジフエニルテトラ
カルボン酸二無水物、２・３・3′・4′−ジフエニ
ルテトラカルボン酸二無水物、２・２−ビス
（３・４−ジカルボキシフエニル）プロパン二無
水物、２・２−ビス〔４−（３・４−ジカルボキ
シフエノキシ）フエニル〕プロパン二無水物、
２・２−ビス〔４−（２・３−ジカルボキシフエ
ノキシ）フエニル〕プロパン二無水物、ビス
（３・４−ジカルボキシフエニル）スルホン二無
水物、ビス（３・４−ジカルボキシフエニル）エ
ーテル二無水物、ビス（３・４−ジカルボキシフ
エニル）メタン二無水物及びペリレン−３・４・
９・10−テトラカルボン酸二無水物等があり、ま
たそれらの混合物を使用することもできる。 本発明における芳香族ジアミンとしては、４・
4″−ジアミノ−ｐ−ターフエニル及び４・４−
ジアミノクオーターフエニルが、本発明の効果を
達成する上で有用である。 また、透湿率が１×10-7ｇ・cm／cm2・ｈより大
きくならず、本発明の効果を損なわない範囲内に
おいて、上記以外の一般的に知られている次のよ
うなジアミンを用いて前記各種酸二無水物と共縮
重合させて合成したポリイミド樹脂を適用するこ
ともできる。例えばｐ−フエニレンジアミン、ｍ
−フエニレンジアミ、４・4′−ジアミノジフエニ
ルエーテル、４・4′−ジアミノジフエニルメタ
ン、４・4′−ジアミノジフエニルスルホン、４・
4′−ジアミノジフエニルプロパン、２・２・４・
4′−ジアミノジフエニルスルフイド、１・５−ジ
アミノナフタリン、４・4′−ジアミノジフエニル
エタン、ｍ−トルイレンジアミン、ｐ−トルイレ
ンジアミン、３・4′−ジアミノベンズアニリド、
１・４−ジアミノナフタリン、３・3′−ジクロロ
−４・4′−ジアミノジフエニル、ベンジジン、
４・4′−ジアミノジフエニルアミン、４・4′−ジ
アミノジフエニル−Ｎ−メチルアミン、４・4′−
ジアミノジフエニル−Ｎ−フエニルアミン、３・
3′−ジアミノジフエニルスルホンなどがある。 なお、本発明者らは、透湿率が１×10-7ｇ・
cm／cm2・ｈより小さい他のポリマーを、本発明の
目的及び効果を損なわない範囲内の量で本発明の
ポリイミド樹脂に混合させて本発明の目的を達成
できることを見い出した。それらのポリマーは例
えばフツ素樹脂の４フツ化エチレン重合体、４フ
ツ化エチレン−６フツ化プロピレン共重合体やポ
リビニリデンフロライドなどがある。 さらに、透湿率が１×10-7ｇ・cm／cm3・ｈより
も大きい一般のポリイミド樹脂に、シリカ、アル
ミナ等微粉末のフイラーを添加すると、透湿率が
かなり低下し、この手法でも半導体の故障率が低
下することを発見した。 これらのフイラーは、天然の鉱石を精製するこ
となく粉砕しただけでは、不純物の点で半導体メ
モリー素子には使用できない。 従つて、半導体メモリー素子のコート材として
使用するには、次のような方法で精製することに
より、ソフトエラーの原因であるα線が実用上問
題となるほどには、発生しないフイラーが得られ
る。 すなわち、例えばケイ素又はアルミニウムに結
合した加水分解しうる基を有するケイ素化合物又
はアルミニウム化合物を蒸留精製し、加水分解及
び共加水分解後、加熱酸化することによつて得ら
れる。 なお、上記フイラーを添加したコート材では、
フイラーの粒子径や添加量の増加とともに塗膜性
が損なわれる問題があり、半導体素子に適用する
際には、適正な範囲の組成を選ぶ必要がある。 本発明の上記ポリイミドは、前記反応溶媒中で
合成されたポリアミド酸ワニスの状態で素子の表
面上に塗布され、100〜450℃程度の温度で数時間
加熱されてポリイミド膜となる。その後、エポキ
シ樹脂、フエノール樹脂、ジアリルフタレート樹
脂、不飽和ポリエステル樹脂、シリコーン樹脂等
の成形材料で注型、トランスフア成形、射出成形
などにより0.5〜５mm程度の厚さにモールドされ
る。 上記のようにして得られたポリイミド樹脂膜
は、腐食性物質のアルミ配線導体、PSG保護層及
びpn接合部の半導体表面の保護膜あるいは層間
絶縁膜として効果を発揮する。 以上により、一般のポリイミドで保護コートし
た場合に比べ、耐湿性の優れた半導体装置が得ら
れる。 次に、本発明を実施例により説明するが、本発
明はこれらにより何ら限定されるものではない。 なお、以下で述べる実施例では、ポリイミドを
コートする前に、すべてアミノシラン化合物で前
処理を施し行なつた。 実施例 １ ４・4″−ジアミノｐ−ターフエニル0.1モルと
ピロメリツト酸二無水物（以下PMDAと略称す
る。）0.1モルをＮ−メチル−２−ピロリドン（以
下NMPと略称する。）中で約10℃で反応させて、
不揮発分約15％、ウラン、トリウムの含量
0.1ppb以下のワニスを得た。 このワニスをMOS型16KビツトRAM素子に塗
布し、100℃で１時間、200℃で２時間、250℃で
３時間加熱して厚さ約50μｍのポリイミド膜を素
子表面に形成した。その後、エポキシ樹脂成形材
料でトランスフア成形し半導体装置を得た。 この半導体装置の80℃／90％RH、1000時間後
の故障率は、０／120と優れていた。 また、このメモリーのソフトエラー率は、100
フイツト（１フイツトは１ケの素子、109時間当
り１回のエラーが起ることを示す単位）以下であ
つた。 同様の加熱条件で得たポリイミドフイルムの25
℃／75％RHにおける透湿率は1.8×10-8ｇ・cm／
cm2・ｈであつた。 比較例 １ ４・4′−ビス（ｐ−アミノフエノキシ）ビフエ
ニル0.1モルとPMDA0.1モルをNMP中で約10℃で
反応させて、不揮発分15％、ウラン、トリウムの
含量0.1ppb以下のワニスを得た。 このワニスを用い、実施例１と同様にして素子
表面にコートしたのち樹脂封止した半導体装置の
同条件下の故障率は12／56であつた。このメモリ
ーのソフトエラー率は、実施例１と同様100フイ
ツト以下であつた。また、このポリイミドの25
℃／75％RHでの透湿率は4.5×10-7ｇ・cm／cm2・
ｈであつた。 実施例 ２ ４・４−ジアミノクオーターフエニル0.05モ
ルと４・4′−ジアミノジフエニルエーテル0.05モ
ル、ベンゾフエノンテトラカルボン酸二無水物
（以下BTDAと略称する）0.1モルをNMP中で約10
℃で反応させ、不揮発分約15％のワニスを得た。
このワニスをレジン封止ダイオードに適用した場
合について述べる。 半導体素子側面にpn接合に沿つて上記ワニス
を塗布後100℃で１時間、200℃で２時間、250℃
で３時間加熱乾燥させポリイミド樹脂膜を形成し
た。これをエポキシ樹脂でモールドし半導体装置
を得、これを80℃／90％RH中に1000時間放置後
の故障率は０／80であつた。このポリイミドフイ
ルムの25℃／75％RHにおける透湿率は3.5×10-8
ｇ・cm／cm2・ｈであつた。 比較例 ２ ４・4′−ジアミノジフエニルエーテル0.1モル
とBTDA0.1モルをNMP中で約10℃で反応させ、
不揮発分約15％のワニスを得た。このワニスを用
いた以外は実施例２と同様にしてレジン封止ダイ
オードを得て実施例２と同じ条件で試験したとこ
ろ、故障率は84／240であつた。このポリイミド
フイルムの25℃／75％RHでの透湿率は2.5×10-7
ｇ・cm／cm2・ｈであつた。 実施例 ３ ４・4″−ジアミノ−ｐ−ターフエニル0.1モル
とPMPD0.05モル、BTDA0.05モルをNMP中で約
10℃で反応させ、不揮発分約15％のワニスを得
た。 シリコン基板の表面上に膜厚5500Åの熱酸化膜
（SiO2）を形成したのち、この表面上に膜厚１μ
ｍのアルミニウムを真空蒸着後、従来の工程に従
つて第１配線導体層を形成した。この上に上記ワ
ニスを回転塗布し、100℃で１時間、200℃で１時
間、250℃で２時間加熱して厚さ約２μｍのポリ
イミド樹脂層間絶縁膜を形成した。次いでスルー
ホール形成後、２層目のアルミニウム配線を行な
い、その上にリン濃度12モル％のCVD法PSG
（厚さ5500Å）の保護層を形成した。ボンデイン
グ後、上記ワニスを塗布、焼付して厚さ35μｍの
ポリイミド保護膜を形成した。これをエポキシ樹
脂でトランスフア成形し半導体装置を得た。 この半導体装置を80℃／90％RHの雰囲気中に
放置したところ、1000時間経過後においても異状
はなかつた。 このポリイミドフイルムの25℃／75％RHにお
ける透湿率は、1.6×10-8ｇ・cm／cm2・ｈであつ
た。 比較例 ３ ４・4′−ジアミノジフエニルメタン0.1モルと
PMDA0.05モル、BTDA0.05モルをNMP中で約10
℃で反応させ、不揮発分約15％のワニスを得た。 これを用いた以外は実施例３と同様にして試験
を行つたところ、800時間経過後に異常が認めら
れたので、不良品を解体してみると、素子のアル
ミ配線は１層目及び２層目共いたるところ腐食し
ていた。 このポリイミドフイルムの25℃／75％RHにお
ける透湿率は４×10-7ｇ・cm／cm・ｈであつた。 実施例 ４ ４・4″−ジアミノｐ−ターフエニル0.1モル、
PMDA0.08モル及びBTDA0.02モルをNMP中で約
10℃で反応させて、不揮発分約15％のワニスを得
た。 このワニスを、リン濃度10モル％のCVD法
PSGを保護層として有するLSIに塗布し、100℃
で１時間、200℃で１時間、次いで300℃で１時間
加熱し、厚さ約50μｍの保護膜を形成した。 その後、エポキシ樹脂成形材料でモールドして
半導体装置を得た。 これを80℃／90％RHの雰囲気中に1000時間放
置したところ、故障率は０／150であつた。 このポリイミドフイルムの25℃／75％RHにお
ける透湿率は1.5×10-8ｇ・cm／cm2・ｈであつ
た。 比較例 ４ ４・4′−ジアミノジフエニルメタン0.1モル、
PMDA0.08モル及びBTDA0.02モルをNMP中で約
10℃で反応させて、不揮発分約15％のワニスを得
た。 これを用い実施例４と同様にして半導体装置を
得、実施例４と同条件で耐湿試験を行なつたとこ
ろ、故障率は42／56であつた。このポリイミドフ
イルムの25℃／75％RHでの透湿率は3.6×10-7
ｇ・cm／cm2・ｈであつた。 実施例 ５〜８ 実施例１で得たポリアミド酸ワニスと、比較例
１で得たポリアミド酸ワニスとを、下表に示す割
合で混合し、４種の混合ポリアミド酸ワニスを得
た。このワニスを用いて、実施例１と同様にレジ
ンモールドしたRAMを作成し、耐湿試験を行な
つた。[Formula] is selected. According to the present invention, a specific polyimide resin film represented by the above general formula () is provided on the aluminum wiring conductor, which is a corrosive substance to water, and the PSG protective layer, which is leached to water. Aluminum wiring layer or PSG
It is possible to provide a resin-sealed semiconductor device having improved moisture resistance of a protective layer and the like and having good characteristics (low failure rate over time). Furthermore, in a semiconductor element having a pn junction, by covering the exposed semiconductor surface of the pn junction with the polyimide resin film, it is possible to provide an excellent element whose characteristics do not deteriorate due to moisture in the outside air. The thickness of the above coating film according to the present invention is 1 to 300 mm.
μm and then molded with molding material. The thickness of the molding material resin is generally selected to be about 0.5 to 5 mm. When α rays are incident on semiconductor memory devices with a high degree of integration, there is a problem in that malfunctions (soft errors) occur. This alpha ray is transmitted through the sealing material ceramic,
The main sources are trace amounts of uranium and thorium contained in metals or mold resins. Therefore, the above-mentioned problem can be solved by removing uranium and thorium from this sealing material. Attempts are being made to extremely reduce the content of uranium and thorium by refining the sealing material. On the other hand, various methods of shielding alpha rays with a protective coating film have been attempted, and when the semiconductor device is a memory, the thickness of the polyimide film of the present invention is reduced to 35 μm.
If the above selection is made, it is possible to prevent soft errors caused by α rays. At this time, in the case of the protective coating film as well, if the uranium and thorium content is refined to 0.1 ppb or less, as with the sealing material, the generation of alpha rays from the polyimide resin itself will not actually be a problem. Purification is conveniently carried out by distillation, sublimation, recrystallization, extraction, etc. of the monomer or solvent.
In addition, in order to reduce corrosion and leakage during moisture resistance tests, the material is purified to a sodium content of 1 ppm or less, but this can be done using the same process as the above purification. In the present invention, the polyimide resin represented by the general formula () or the polyamic acid resin which is its precursor is obtained by a method of reacting an aromatic diamine and an aromatic tetracarboxylic dianhydride in equimolar ratios. For example, this can be achieved by a solution polycondensation method. In the solution polymerization method, a reaction solvent is used, and this solvent must be capable of dissolving both the aromatic diamine and the aromatic tetracarboxylic dianhydride. Examples of reaction solvents used in the present invention include N·N-dimethylformamide, N·N-diethylformamide, dimethyl sulfoxide, N·N-dimethylacetamide, N·N-diethylacetamide, N-methyl-2-pyrrolidone, etc. can be given. Two or more reaction solvents may be used in combination, if necessary, to facilitate the dissolution operation. Specific examples of the aromatic tetracarboxylic dianhydride in the present invention include pyromellitic dianhydride (PMDA), benzophenone tetracarboxylic dianhydride (BTDA), and 1,4,5,8-naphthalene. Tetracarboxylic dianhydride, 2, 3, 6,
7-Naphthalenetetracarboxylic dianhydride, 1.
2,5,6-naphthalenetetracarboxylic dianhydride, 3,3',4,4'-diphenyltetracarboxylic dianhydride, 2,2,3,3'-diphenyltetracarboxylic dianhydride , 2,3,3',4'-diphenyltetracarboxylic dianhydride, 2,2-bis(3,4-dicarboxyphenyl)propane dianhydride, 2,2-bis[4-(3・4-dicarboxyphenoxy)phenyl]propane dianhydride,
2,2-bis[4-(2,3-dicarboxyphenoxy)phenyl]propane dianhydride, bis(3,4-dicarboxyphenyl)sulfone dianhydride, bis(3,4-dicarboxy phenyl)ether dianhydride, bis(3,4-dicarboxyphenyl)methane dianhydride, and perylene-3,4.
Examples include 9,10-tetracarboxylic dianhydride, and mixtures thereof can also be used. The aromatic diamine in the present invention includes 4.
4″-diamino-p-terphenyl and 4,4-
Diaminoquarterphenyl is useful in achieving the effects of the present invention. In addition, the following generally known diamines other than those mentioned above may be used as long as the moisture permeability does not exceed 1×10 -7 g・cm/cm 2・h and does not impair the effects of the present invention. It is also possible to apply a polyimide resin synthesized by cocondensation polymerization with the various acid dianhydrides using the above-mentioned various acid dianhydrides. For example, p-phenylenediamine, m
-phenylene diamide, 4,4'-diaminodiphenyl ether, 4,4'-diaminodiphenylmethane, 4,4'-diaminodiphenyl sulfone, 4,
4'-diaminodiphenylpropane, 2.2.4.
4'-diaminodiphenyl sulfide, 1,5-diaminonaphthalene, 4,4'-diaminodiphenylethane, m-tolylenediamine, p-tolylenediamine, 3,4'-diaminobenzanilide,
1,4-diaminonaphthalene, 3,3'-dichloro-4,4'-diaminodiphenyl, benzidine,
4,4'-diaminodiphenylamine, 4,4'-diaminodiphenyl-N-methylamine, 4,4'-
Diaminodiphenyl-N-phenylamine, 3.
Examples include 3'-diaminodiphenyl sulfone. In addition, the present inventors have determined that the moisture permeability is 1×10 -7 g・
It has been found that the objects of the present invention can be achieved by mixing other polymers smaller than cm/cm 2 ·h with the polyimide resin of the present invention in an amount within a range that does not impair the objects and effects of the present invention. Examples of such polymers include fluorocarbon resins such as tetrafluoroethylene polymer, tetrafluoroethylene-hexafluoropropylene copolymer, and polyvinylidene fluoride. Furthermore, when a filler of fine powder such as silica or alumina is added to a general polyimide resin with a moisture permeability higher than 1×10 -7 g・cm/cm 3・h, the moisture permeability decreases considerably. However, they discovered that the failure rate of semiconductors decreased. These fillers cannot be used in semiconductor memory devices because of impurities if the natural ores are simply ground without being refined. Therefore, for use as a coating material for semiconductor memory devices, a filler that does not generate alpha rays, which cause soft errors, to the extent that it becomes a practical problem can be obtained by purifying the filler using the following method. That is, it can be obtained, for example, by distilling and purifying a silicon compound or aluminum compound having a hydrolyzable group bonded to silicon or aluminum, hydrolyzing and cohydrolyzing it, and then heating and oxidizing it. In addition, in the coating material added with the above filler,
There is a problem that coating properties are impaired as the particle size and amount added of the filler increases, so when applying it to semiconductor devices, it is necessary to select a composition within an appropriate range. The polyimide of the present invention is applied to the surface of the device in the form of a polyamic acid varnish synthesized in the reaction solvent, and heated at a temperature of about 100 to 450° C. for several hours to form a polyimide film. Thereafter, it is molded to a thickness of about 0.5 to 5 mm using a molding material such as epoxy resin, phenol resin, diallyl phthalate resin, unsaturated polyester resin, or silicone resin by casting, transfer molding, injection molding, or the like. The polyimide resin film obtained as described above is effective as a protective film or an interlayer insulating film on the surface of a corrosive aluminum wiring conductor, a PSG protective layer, and a semiconductor at a pn junction. As a result of the above, a semiconductor device with superior moisture resistance can be obtained compared to a case where a protective coating is made of general polyimide. Next, the present invention will be explained with reference to Examples, but the present invention is not limited to these in any way. In the Examples described below, all samples were pretreated with an aminosilane compound before coating with polyimide. Example 1 0.1 mole of 4,4''-diamino p-terphenyl and 0.1 mole of pyromellitic dianhydride (hereinafter abbreviated as PMDA) were mixed in N-methyl-2-pyrrolidone (hereinafter abbreviated as NMP) for about 10 React at ℃,
Non-volatile content approximately 15%, uranium and thorium content
A varnish with less than 0.1 ppb was obtained. This varnish was applied to a MOS-type 16K-bit RAM element and heated at 100°C for 1 hour, 200°C for 2 hours, and 250°C for 3 hours to form a polyimide film about 50 μm thick on the element surface. Thereafter, a semiconductor device was obtained by transfer molding using an epoxy resin molding material. The failure rate of this semiconductor device after 1000 hours at 80°C/90%RH was excellent at 0/120. Also, the soft error rate of this memory is 100
It was less than the fit (one fit is one element, which means one error occurs every 109 hours). 25 of polyimide film obtained under similar heating conditions.
Moisture permeability at ℃/75%RH is 1.8×10 -8 g・cm/
It was hot at cm2・h. Comparative Example 1 0.1 mol of 4,4'-bis(p-aminophenoxy)biphenyl and 0.1 mol of PMDA were reacted in NMP at about 10°C to produce a varnish with a non-volatile content of 15% and a uranium and thorium content of 0.1 ppb or less. Obtained. The failure rate of a semiconductor device in which the element surface was coated with this varnish in the same manner as in Example 1 and then resin-sealed was 12/56 under the same conditions. The soft error rate of this memory was 100 fits or less, as in Example 1. Also, 25 of this polyimide
Moisture permeability at ℃/75%RH is 4.5×10 -7 g・cm/cm 2・
It was h. Example 2 0.05 mol of 4,4-diaminoquarterphenyl, 0.05 mol of 4,4'-diaminodiphenyl ether, and 0.1 mol of benzophenone tetracarboxylic dianhydride (hereinafter abbreviated as BTDA) were mixed in NMP at about 10 mol.
The reaction was carried out at ℃ to obtain a varnish with a non-volatile content of about 15%.
A case will be described in which this varnish is applied to a resin-sealed diode. After applying the above varnish to the side surface of the semiconductor device along the pn junction, it was heated to 100℃ for 1 hour, 200℃ for 2 hours, and 250℃.
The film was dried by heating for 3 hours to form a polyimide resin film. This was molded with epoxy resin to obtain a semiconductor device, and after being left at 80° C./90% RH for 1000 hours, the failure rate was 0/80. The moisture permeability of this polyimide film at 25℃/75%RH is 3.5×10 -8
It was g・cm/cm 2・h. Comparative Example 2 0.1 mol of 4,4'-diaminodiphenyl ether and 0.1 mol of BTDA were reacted at about 10°C in NMP,
A varnish with a non-volatile content of approximately 15% was obtained. A resin-sealed diode was obtained in the same manner as in Example 2 except that this varnish was used and tested under the same conditions as in Example 2, and the failure rate was 84/240. The moisture permeability of this polyimide film at 25℃/75%RH is 2.5×10 -7
It was g・cm/cm 2・h. Example 3 0.1 mol of 4.4″-diamino-p-terphenyl, 0.05 mol of PMPD, 0.05 mol of BTDA in NMP
The reaction was carried out at 10°C to obtain a varnish with a non-volatile content of approximately 15%. After forming a thermal oxide film (SiO 2 ) with a thickness of 5500 Å on the surface of a silicon substrate, a film with a thickness of 1 μ
After vacuum-depositing aluminum of m, a first wiring conductor layer was formed according to a conventional process. The above varnish was spin-coated on top of this, and heated at 100°C for 1 hour, 200°C for 1 hour, and 250°C for 2 hours to form a polyimide resin interlayer insulating film with a thickness of about 2 μm. Next, after forming through holes, a second layer of aluminum wiring is formed, and on top of that, CVD method PSG with a phosphorus concentration of 12 mol% is formed.
A protective layer (thickness: 5500 Å) was formed. After bonding, the above varnish was applied and baked to form a polyimide protective film with a thickness of 35 μm. This was transfer molded with epoxy resin to obtain a semiconductor device. When this semiconductor device was left in an atmosphere of 80° C./90% RH, no abnormality was observed even after 1000 hours had passed. The moisture permeability of this polyimide film at 25° C./75% RH was 1.6×10 -8 g·cm/cm 2 ·h. Comparative example 3 0.1 mol of 4,4'-diaminodiphenylmethane
PMDA 0.05 mol, BTDA 0.05 mol in NMP about 10
The reaction was carried out at ℃ to obtain a varnish with a non-volatile content of about 15%. A test was conducted in the same manner as in Example 3 except that this was used, and an abnormality was observed after 800 hours had passed. When the defective product was dismantled, it was found that the aluminum wiring of the element was in the first and second layers. The eyes were corroded everywhere. The moisture permeability of this polyimide film at 25° C./75% RH was 4×10 −7 g·cm/cm·h. Example 4 4.4″-diamino p-terphenyl 0.1 mol,
Approximately 0.08 mol PMDA and 0.02 mol BTDA in NMP
The reaction was carried out at 10°C to obtain a varnish with a non-volatile content of approximately 15%. This varnish was processed using the CVD method with a phosphorus concentration of 10 mol%.
Coated on LSI with PSG as a protective layer and heated to 100℃
The film was heated for 1 hour at 200°C, and then at 300°C for 1 hour to form a protective film with a thickness of about 50 μm. Thereafter, it was molded with an epoxy resin molding material to obtain a semiconductor device. When this was left in an atmosphere of 80°C/90% RH for 1000 hours, the failure rate was 0/150. The moisture permeability of this polyimide film at 25° C./75% RH was 1.5×10 -8 g·cm/cm 2 ·h. Comparative example 4 0.1 mol of 4,4'-diaminodiphenylmethane,
Approximately 0.08 mol PMDA and 0.02 mol BTDA in NMP
The reaction was carried out at 10°C to obtain a varnish with a non-volatile content of approximately 15%. Using this, a semiconductor device was obtained in the same manner as in Example 4, and a moisture resistance test was conducted under the same conditions as in Example 4, and the failure rate was 42/56. The moisture permeability of this polyimide film at 25℃/75%RH is 3.6×10 -7
It was g・cm/cm 2・h. Examples 5 to 8 The polyamic acid varnish obtained in Example 1 and the polyamic acid varnish obtained in Comparative Example 1 were mixed in the proportions shown in the table below to obtain four types of mixed polyamic acid varnishes. Using this varnish, a resin-molded RAM was prepared in the same manner as in Example 1, and a moisture resistance test was conducted.

【表】 実施例 ９ ４・4″−ジアミノ−ｐ−ターフエニル0.1モル
とBTDA0.1モルをNMP中で約10℃で反応させて
不揮発分約15％のワニスを得た。このポリアミド
酸ワニスにフツ素樹脂として４フツ化エチレン樹
脂を平均粒径0.1〜50μｍの微粉末としたものを
10重量％添加したワニスを作製した。このワニス
をリン濃度10モル％のCVD法PSGを保護層とし
て有するLSIに塗布し、100℃で１時間、200℃で
２時間、400℃で２時間加熱し、厚さ約50μｍの
保護膜を形成した。その後、エポキシ樹脂成形材
料でモールドして半導体装置を得た。 これを80℃／90％RHの雰囲気中に放置したと
ころ、1000時間経過後でも異常はなかつた。 さらに、この半導体装置を、120℃、２気圧の
飽和水蒸気中に放置するプレツシヤークツカーテ
ストを行なつたところ、120時間経過後でも異常
は認められなかつた。 このフツ素樹脂を含むコート材のフイルムの25
℃／75％RHにおける透湿率は1.3×10-8ｇ・cm／
cm2・ｈであつた。 実施例 10 ４・4′−ジアミノジフエニルエーテル0.1モル
とピロメリツト酸二無水物0.1モルをNMP中で約
10℃で反応させて得た不揮発分15％のワニスに、
精製された高純度のシリカ粉末をフイラーを添加
して、透湿率を測定した。その結果、第５図に示
したように、フイラーの添加量が増加するに従い
透湿率は低下し、フイラー添加量が35容量％以上
になると本発明の透湿率が１×10-7ｇ・cm／cm2・
ｈ以下となることがわかつた。また、フイラーの
添加量が70容量％以上では、塗膜性が著しく劣
り、半導体素子に塗布した場合、均一に塗布でき
なかつた。 そして、フイラーを50容量％添加した上記ワニ
スLSI素子に塗布し、100℃で１時間、200℃で５
時間加熱して厚さ70μｍの保護膜を形成した。 その後、エポキシ樹脂でトランスフア成形して
半導体装置を得た。 これを80℃／90％RH中に1000時間放置したと
ころ、故障率は０／180であつた。 実施例 11 実施例１で得たワニスを、LSIの多層配線用の
層間絶縁膜に用いた場合について述べる。 SiO2の熱酸化膜を有したシリコン基板表面上
に、膜厚２μｍのアルミニウムを真空蒸着後、従
来の工程に従つて第１層の配線導体層を形成し
た。この上に、実施例１で得たポリアミド酸ワニ
スを回転塗布し、加熱硬化してポリイミド膜（厚
さ４μｍ）を形成した。次いでスルホールを形成
後、第２層のアルミニウム配線導体層を形成す
る。さらに、この上に上記ワニスを塗布し加熱硬
化してポリイミド膜（厚さ４μｍ）を形成後、フ
オトレジストを用いてポリイミド膜を選択的にエ
ツチングし、スルホールを形成した。その後、第
３層のアルミニウム配線導体層を形成した。ボン
デイング後この上に配線保護膜として上記ワニス
を塗布、加熱硬化して厚さ45μｍのポリイミド膜
を形成した。 これをエポキシ樹脂で封止した後、80℃／90％
RHの雰囲気中に放置する試験を行つたところ、
1000時間経過後における故障率は０／40であつ
た。 以上説明したように、本発明によれば、アルミ
ニウム配線導体及びpn接合の露呈する半導体表
面あるいはCVD法PSG保護層上に、特定のポリ
イミド膜からなる有機高分子膜を設けることによ
り耐湿性の優れた半導体装置を提供することがで
きる。[Table] Example 9 A varnish with a nonvolatile content of about 15% was obtained by reacting 0.1 mol of 4,4″-diamino-p-terphenyl and 0.1 mol of BTDA in NMP at about 10°C. As the fluororesin, tetrafluoroethylene resin is made into fine powder with an average particle size of 0.1 to 50 μm.
A varnish containing 10% by weight was prepared. This varnish was applied to an LSI having CVD PSG with a phosphorus concentration of 10 mol% as a protective layer, and heated at 100°C for 1 hour, 200°C for 2 hours, and 400°C for 2 hours to form a protective film with a thickness of approximately 50 μm. Formed. Thereafter, it was molded with an epoxy resin molding material to obtain a semiconductor device. When this was left in an atmosphere of 80°C/90% RH, no abnormalities were observed even after 1000 hours had passed. Further, when this semiconductor device was subjected to a pressure vacuum test in which it was left in saturated steam at 120° C. and 2 atm, no abnormality was observed even after 120 hours. 25 of the coating material film containing this fluororesin
Moisture permeability at ℃/75%RH is 1.3×10 -8 g・cm/
It was hot at cm2・h. Example 10 0.1 mole of 4,4'-diaminodiphenyl ether and 0.1 mole of pyromellitic dianhydride are dissolved in NMP to approx.
A varnish with a non-volatile content of 15% obtained by reacting at 10℃,
A filler was added to purified high-purity silica powder, and the moisture permeability was measured. As a result, as shown in FIG. 5, as the amount of filler added increases, the moisture permeability decreases, and when the amount of filler added exceeds 35% by volume, the moisture permeability of the present invention decreases to 1×10 -7 g.・cm/ cm2・
It was found that it was less than h. Furthermore, when the amount of filler added was 70% by volume or more, the coating properties were extremely poor, and when it was applied to a semiconductor element, it could not be applied uniformly. Then, the above varnish containing 50% filler by volume was applied to the LSI device, heated at 100℃ for 1 hour, and heated to 200℃ for 5 hours.
A protective film with a thickness of 70 μm was formed by heating for a period of time. Thereafter, a semiconductor device was obtained by transfer molding with epoxy resin. When this was left at 80°C/90%RH for 1000 hours, the failure rate was 0/180. Example 11 A case will be described in which the varnish obtained in Example 1 is used as an interlayer insulating film for multilayer wiring of LSI. After aluminum was vacuum-deposited to a thickness of 2 μm on the surface of a silicon substrate having a thermally oxidized film of SiO 2 , a first wiring conductor layer was formed according to a conventional process. On top of this, the polyamic acid varnish obtained in Example 1 was spin-coated and cured by heating to form a polyimide film (thickness: 4 μm). Next, after forming through holes, a second aluminum wiring conductor layer is formed. Further, the varnish described above was applied and cured by heating to form a polyimide film (thickness: 4 μm), and then the polyimide film was selectively etched using a photoresist to form through holes. Thereafter, a third layer of aluminum wiring conductor layer was formed. After bonding, the above-mentioned varnish was applied thereon as a wiring protection film and cured by heating to form a polyimide film with a thickness of 45 μm. After sealing this with epoxy resin, 80℃/90%
When we conducted a test where we left it in an RH atmosphere, we found that
The failure rate after 1000 hours was 0/40. As explained above, according to the present invention, excellent moisture resistance is achieved by providing an organic polymer film made of a specific polyimide film on the exposed semiconductor surface of the aluminum wiring conductor and pn junction or on the CVD PSG protective layer. Accordingly, a semiconductor device can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明による樹脂封止型半導体装置
の構造を示す断面図；第２図は、本発明を適用し
た他の樹脂封止型半導体装置の構造を示す断面
図；第３図は、本発明を適用した多層配線を有す
る樹脂封止型半導体装置の構造を示す断面図、及
び第４図は、本発明による樹脂封止型メモリーの
構造を示す断面斜視図、第５図は、本発明の一実
施例をよりよく理解するための説明図である。 １，１１，４１，７１……半導体チツプ、８，
１０，７５……封止樹脂、６，９，４５，７６…
…ポリイミド膜。 FIG. 1 is a cross-sectional view showing the structure of a resin-sealed semiconductor device according to the present invention; FIG. 2 is a cross-sectional view showing the structure of another resin-sealed semiconductor device to which the present invention is applied; FIG. , FIG. 4 is a cross-sectional perspective view showing the structure of a resin-encapsulated memory according to the present invention, and FIG. FIG. 2 is an explanatory diagram for better understanding one embodiment of the present invention. 1, 11, 41, 71... semiconductor chip, 8,
10,75...Sealing resin, 6,9,45,76...
...Polyimide membrane.

Claims (1)

【特許請求の範囲】 １ 半導体素子の周囲を封止樹脂で封止した半導
体装置において、前記半導体素子の表面に透湿率
が１×10-7ｇ・cm／cm2・ｈ以下であり、一般式が 【式】 （式（）中、Ｒは脂肪族、または芳香族基、−
R′−は【式】およびま たは ｎは整数を表わす）で示される有機高分子膜を、
直接または他の絶縁材料を介して設けたことを特
徴とする樹脂封止型半導体装置。 ２ 【式】が【式】およびまたは 【式】であることを特徴とする特 許請求の範囲第２項記載の樹脂封止型半導体装
置。[Claims] 1. A semiconductor device in which the periphery of a semiconductor element is sealed with a sealing resin, wherein the surface of the semiconductor element has a moisture permeability of 1×10 -7 g·cm/cm 2 ·h or less, The general formula is [Formula] (In formula (), R is an aliphatic or aromatic group, -
R′− is [formula] and or n represents an integer),
A resin-sealed semiconductor device characterized in that it is provided directly or via another insulating material. 2. The resin-sealed semiconductor device according to claim 2, wherein [Formula] is [Formula] and or [Formula].
JP56075291A 1981-05-18 1981-05-18 Plastic molded type semiconductor device Granted JPS57188853A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP56075291A JPS57188853A (en) 1981-05-18 1981-05-18 Plastic molded type semiconductor device
GB8120607A GB2098800B (en) 1981-05-18 1981-07-03 Resin encapsulated semiconductor devices
DE3126361A DE3126361C2 (en) 1981-05-18 1981-07-03 Protective layer for semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56075291A JPS57188853A (en) 1981-05-18 1981-05-18 Plastic molded type semiconductor device

Publications (2)

Publication Number Publication Date
JPS57188853A JPS57188853A (en) 1982-11-19
JPS628035B2 true JPS628035B2 (en) 1987-02-20

Family

ID=13571981

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56075291A Granted JPS57188853A (en) 1981-05-18 1981-05-18 Plastic molded type semiconductor device

Country Status (3)

Country Link
JP (1) JPS57188853A (en)
DE (1) DE3126361C2 (en)
GB (1) GB2098800B (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6012744A (en) * 1983-07-01 1985-01-23 Hitachi Ltd Semiconductor device
JPS60208358A (en) * 1984-04-02 1985-10-19 Hitachi Ltd Composite
JPS60221426A (en) * 1984-04-17 1985-11-06 Hitachi Chem Co Ltd Production of polyimide composite
JPS60238817A (en) * 1984-05-12 1985-11-27 Citizen Watch Co Ltd Liquid crystal display device
JPS60243120A (en) * 1984-05-18 1985-12-03 Hitachi Ltd Flexible printed base board and production thereof
JPS60245150A (en) * 1984-05-21 1985-12-04 Hitachi Ltd Semiconductor device
JPH01110559A (en) * 1987-10-23 1989-04-27 Hitachi Chem Co Ltd Composition of protective film for semiconductor element
JPH0682649B2 (en) * 1988-01-08 1994-10-19 日産化学工業株式会社 Insulation film for electric / electronic devices
US5272247A (en) * 1990-10-19 1993-12-21 Hitachi, Ltd. Polyimide precursor, cured product thereof, and processes for producing them
US5276414A (en) * 1991-12-10 1994-01-04 Mitsubishi Denki Kabushiki Kaisha Moistureproof structure for module circuits
JPH05198786A (en) * 1992-01-22 1993-08-06 Sharp Corp Clear-mold ccd solid-state image pickup element
US5536584A (en) * 1992-01-31 1996-07-16 Hitachi, Ltd. Polyimide precursor, polyimide and metalization structure using said polyimide
DE19741437A1 (en) * 1997-09-19 1999-04-01 Siemens Ag Electronic component with improved housing molding compound
US7893435B2 (en) 2000-04-18 2011-02-22 E Ink Corporation Flexible electronic circuits and displays including a backplane comprising a patterned metal foil having a plurality of apertures extending therethrough
AU2001253575A1 (en) * 2000-04-18 2001-10-30 E-Ink Corporation Process for fabricating thin film transistors
JP5732884B2 (en) * 2011-02-09 2015-06-10 富士通株式会社 Semiconductor device, manufacturing method thereof, and power supply device
CN105254886A (en) * 2015-11-02 2016-01-20 株洲时代新材料科技股份有限公司 Polyamide acid resin composition and thermoplastic polyimide thin film as well as preparation methods thereof
JP6790756B2 (en) * 2016-11-18 2020-11-25 宇部興産株式会社 Polyimide, polyimide precursor, and polyimide film
CN116478400B (en) * 2023-02-06 2024-10-18 中山大学 Polyimide and diamine monomer containing tetrabiphenyl derivative structure and preparation method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506279A (en) * 1973-05-18 1975-01-22

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5176078A (en) * 1974-12-23 1976-07-01 Hitachi Ltd Handaboshokumakuo hodokoshita handotaisochi
JPS5568659A (en) * 1978-11-20 1980-05-23 Hitachi Ltd Semiconductor device and manufacturing method thereof
JPS55156343A (en) * 1979-05-25 1980-12-05 Hitachi Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS506279A (en) * 1973-05-18 1975-01-22

Also Published As

Publication number Publication date
GB2098800B (en) 1986-03-26
GB2098800A (en) 1982-11-24
JPS57188853A (en) 1982-11-19
DE3126361C2 (en) 1986-12-04
DE3126361A1 (en) 1982-11-25

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