JPS6148266B2 - - Google Patents
Info
- Publication number
- JPS6148266B2 JPS6148266B2 JP54074680A JP7468079A JPS6148266B2 JP S6148266 B2 JPS6148266 B2 JP S6148266B2 JP 54074680 A JP54074680 A JP 54074680A JP 7468079 A JP7468079 A JP 7468079A JP S6148266 B2 JPS6148266 B2 JP S6148266B2
- Authority
- JP
- Japan
- Prior art keywords
- polyimide
- coating
- film
- semiconductor
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 229920001721 polyimide Polymers 0.000 claims description 20
- 239000004642 Polyimide Substances 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 13
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 238000000034 method Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229920006026 co-polymeric resin Polymers 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- NWZSZGALRFJKBT-KNIFDHDWSA-N (2s)-2,6-diaminohexanoic acid;(2s)-2-hydroxybutanedioic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O.NCCCC[C@H](N)C(O)=O NWZSZGALRFJKBT-KNIFDHDWSA-N 0.000 description 1
- PEVRKKOYEFPFMN-UHFFFAOYSA-N 1,1,2,3,3,3-hexafluoroprop-1-ene;1,1,2,2-tetrafluoroethene Chemical group FC(F)=C(F)F.FC(F)=C(F)C(F)(F)F PEVRKKOYEFPFMN-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229920000840 ethylene tetrafluoroethylene copolymer Polymers 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- IKDUDTNKRLTJSI-UHFFFAOYSA-N hydrazine monohydrate Substances O.NN IKDUDTNKRLTJSI-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- HNJBEVLQSNELDL-UHFFFAOYSA-N pyrrolidin-2-one Chemical compound O=C1CCCN1 HNJBEVLQSNELDL-UHFFFAOYSA-N 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】
この発明は、半導体装置、特に電気的、機械
的、及び又は化学的な保護のための被膜を有する
半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a coating for electrical, mechanical, and/or chemical protection.
半導体素子の表面上に外部との電気的接続を行
なつた後シリコン系レジンで保護し、耐湿信頼性
を向上させる方法は一般的に知られている。この
場合、シリコン系レジンは、SiO2やPSG（フオス
フオシリケートガラス）膜上に塗布される。この
方法によりプラスチツク封止型の半導体装置の耐
湿信頼性が向上することが期待されるが、ポリイ
ミド系有機被膜を表面に有する半導体装置の場
合、シリコン系レジンはポリイミド系有機被膜と
の接着性が高く、プラスチツク封止工程で半導体
表面から剥離し、十分な耐湿信頼性が得られな
い。 A generally known method is to make electrical connections to the outside on the surface of a semiconductor element and then protect the semiconductor element with a silicon resin to improve moisture resistance reliability. In this case, the silicon-based resin is applied onto the SiO 2 or PSG (phosphorus phosphosilicate glass) film. This method is expected to improve the moisture resistance reliability of plastic-sealed semiconductor devices, but in the case of semiconductor devices that have a polyimide-based organic film on the surface, silicon-based resin has poor adhesion with the polyimide-based organic film. It is expensive and peels off from the semiconductor surface during the plastic sealing process, making it impossible to obtain sufficient moisture resistance reliability.
ポリイミド系有機被膜をその表面に有する半導
体装置の保護のためには、
(1) ポリイミド系有機被膜との接着性が良好なこ
と
(2) 水分の吸湿率及び透過率が小さいこと
(3) 塗布被膜がポリイミド系有機被膜に損傷を与
えるほどのストレスを生じさせないこと
が必要である。 In order to protect a semiconductor device that has a polyimide-based organic film on its surface, (1) good adhesion with the polyimide-based organic film (2) low moisture absorption and permeability (3) coating It is necessary that the coating does not generate enough stress to damage the polyimide organic coating.
本発明は信頼性のすぐれた半導体装置を提供す
ることを目的としてなされたものであり、更に具
体的にはポリイミド系有機被膜をその構成要素と
して有する半導体素子上に、ポリイミド系有機被
膜と接着性が良好で、かつ水分の吸湿率が小さい
フツ素系樹脂被膜を形成し、半導体装置の外部あ
るいは封止材料からの水分の浸入、ストレス、α
線等高速粒子によるダメージから半導体素子を保
護し、信頼性を向上させることを目的とする。 The present invention has been made for the purpose of providing a semiconductor device with excellent reliability, and more specifically, a polyimide-based organic film and an adhesive bonding layer are formed on a semiconductor element having a polyimide-based organic film as a component thereof. It forms a fluorine-based resin film that has good moisture absorption and low moisture absorption, and prevents moisture from entering the semiconductor device or from the sealing material, stress, α
The purpose is to protect semiconductor devices from damage caused by high-velocity particles such as linear particles and improve reliability.
フツ素系樹脂は一般に無機物との接着性は悪
く、従つてSiO2膜、PSG膜をその表面保護膜とし
て有する半導体装置への適用はむずかしいが、他
方ポリイミド系樹脂被膜との接着性は一般に良好
である。 Fluorine-based resins generally have poor adhesion to inorganic substances, and therefore are difficult to apply to semiconductor devices that have SiO 2 films or PSG films as surface protective films, but on the other hand, their adhesion to polyimide resin films is generally good. It is.
またフツ素樹脂は、水分の吸湿率が小さく、か
つ塗布、ベーク後もストレスが小さくポリイミド
系樹脂被膜に損傷を与えることはない。 In addition, fluororesin has a low moisture absorption rate, and even after application and baking, the stress is low and does not damage the polyimide resin coating.
これらの特徴を有するフツ素系樹脂とポリイミ
ド系有機被膜とを適切に組合せることにより、上
記目的を達成することが可能である。 The above object can be achieved by appropriately combining a fluororesin having these characteristics and a polyimide organic coating.
以下、実施例にもとづいて本発明を詳細に説明
する。 Hereinafter, the present invention will be explained in detail based on Examples.
まず、第１図に示すように通常のプロセにより
シリコンからなる半導体基板１の主表面に半導体
素子領域（図示せず）を形成し、SiO2膜等の絶
縁膜を介して素子領域間の電気的接続用Al配線
３及び外部との電気的接続のためのAl電極パツ
ド２を形成する。このようにして形成された半導
体素子表面に、ピロリドン溶媒の15％濃度のポリ
イミドワニスをスピンナで塗布し、100℃ 30
分、200℃ 30分、350℃ 30分窒素雰囲気中でベ
ークし、重合反応させ、約２μｍの厚さのポリイ
ミド被膜４を形成する。この後、外部との電気的
接続用パツド部２及びスクライブライン部１０の
ポリイミド被膜４をホトエツチング技術により除
去する。エツチングはヒドラジンヒドラートを用
い、30℃で約15分である。この工程によりパツド
部２及びスクライブライン部１０以外はポリイミ
ド被膜４で覆われた構造を得る。このように形成
された半導体装置を上記スクライブライン部に沿
つてスクライブし個々のペレツト（小片）に分割
し、第２図に示すようにリードフレームのタブ６
上に金（Au）箔５を用い金−Si共晶にて固定
し、その後外部との電気的接続のため通常のワイ
ヤボンデイング法によりパツド２とフレームのリ
ード端子７間をAu線等のコネクタワイヤ８で接
続する。 First, as shown in FIG. 1, a semiconductor element region (not shown) is formed on the main surface of a semiconductor substrate 1 made of silicon by a normal process, and electricity is established between the element regions via an insulating film such as a SiO 2 film. Al wiring 3 for physical connection and Al electrode pad 2 for electrical connection with the outside are formed. A polyimide varnish with a concentration of 15% pyrrolidone solvent was applied to the surface of the semiconductor element thus formed using a spinner, and heated at 100°C 30°C.
Bake in a nitrogen atmosphere for 30 minutes at 200° C. and 30 minutes at 350° C. to cause a polymerization reaction and form a polyimide film 4 with a thickness of about 2 μm. Thereafter, the polyimide coating 4 on the external electrical connection pad portion 2 and the scribe line portion 10 is removed by photoetching. Etching is performed using hydrazine hydrate at 30°C for about 15 minutes. Through this process, a structure is obtained in which the parts other than the pad portion 2 and the scribe line portion 10 are covered with the polyimide film 4. The semiconductor device thus formed is scribed along the scribe line portion to be divided into individual pellets (small pieces), and the tabs 6 of the lead frame are separated as shown in FIG.
A gold (Au) foil 5 is used on top and fixed with gold-Si eutectic, and then a connector such as an Au wire is connected between the pad 2 and the lead terminal 7 of the frame using the usual wire bonding method for electrical connection with the outside. Connect with wire 8.
こののち、水性デイスパージヨンタイプの４フ
ツ化エチレン−６フツ化プロピレン共重合樹脂
を、上記のように組立てられた半導体装置上に塗
布し、100℃ 30分，300℃ 30分窒素雰囲気中で
ベークし、被膜９を形成する。本被膜厚さは前記
ポリイミド被膜４の厚さの10倍以上とすることが
望ましく、具体的には10μｍ以上とするのが望ま
しい。 After this, aqueous dispersion type tetrafluoroethylene-hexafluoropropylene copolymer resin is applied onto the semiconductor device assembled as described above, and baked at 100° C. for 30 minutes and 300° C. for 30 minutes in a nitrogen atmosphere to form a coating 9. The thickness of this coating is desirably at least 10 times the thickness of the polyimide coating 4, specifically desirably at least 10 μm.
その後は通常の方法により点線１３で示すよう
にモールド樹脂体によりリードフレームのリード
先端部、タブ部、ワイヤ及び半導体素子部を一体
にプラスチツク封止し、本発明による半導体装置
が形成される。 Thereafter, the lead tips, tab portions, wires, and semiconductor element portion of the lead frame are integrally sealed with plastic using a molded resin body as shown by dotted lines 13 by a conventional method, thereby forming a semiconductor device according to the present invention.
ポリイミド上に塗布することにより同様の効果
が得られるフツ素系樹脂として、４フツ化エチレ
ン樹脂、４フツ化エチレン−エチレン共重合樹
脂、４フツ化エチレン−パ−フロロアルキルビニ
ルエーテル共重合樹脂などがある。これらはいず
れもポリマー分子の構成要素としてフツ素を含有
するポリマーである。 Examples of fluorine-based resins that can obtain similar effects by coating on polyimide include tetrafluoroethylene resins, tetrafluoroethylene-ethylene copolymer resins, and tetrafluoroethylene-perfluoroalkyl vinyl ether copolymer resins. be. All of these are polymers containing fluorine as a component of the polymer molecule.
本発明によりフツ素系樹脂のもつ非吸湿性及び
ポリイミドとの接着性が良好のため、各被膜間の
はがれの問題をなくし、外部から、半導体基板上
の金属配線への水分の浸入速度を遅らせ、半導体
装置の耐湿信頼性を向上させることができる。 The present invention eliminates the problem of peeling between each film due to the non-hygroscopicity of the fluororesin and its good adhesion to polyimide, thereby slowing down the rate of moisture intrusion from the outside into the metal wiring on the semiconductor substrate. , the moisture resistance reliability of the semiconductor device can be improved.
本発明の耐湿信頼性に対する効果を第３図に示
す。同図よりプレツシヤクツキング（H2O ガス
圧2.2気圧、温度120℃）による強制劣化試験によ
る不良発生は従来技術により作成したもの（曲線
１１）より本発明適用品（曲線１２）の方が明ら
かにすぐれていることがわかる。 The effect of the present invention on moisture resistance reliability is shown in FIG. From the same figure, the occurrence of defects in the forced deterioration test by pressure pumping (H 2 O gas pressure 2.2 atm, temperature 120°C) is higher in the product applied with the present invention (curve 12) than in the product created using the conventional technology (curve 11). is clearly superior.
なお、本願発明の効果は特に耐湿性を問題とす
るプラスチツク封止型の半導体装置に適用してそ
の効果が大きいが、その他例えばキヤン封止、セ
ラミツク封止型の半導体装置にも適用できる。 The present invention is particularly effective when applied to plastic-sealed semiconductor devices where moisture resistance is an issue, but it can also be applied to other types of semiconductor devices, such as can-sealed and ceramic-sealed.
第１図、半導体素子の保護膜としてポリイミド
被膜を有する半導体素子要部の断面図である。第
２図は、本発明に係る半導体装置を説明するため
の要部断面図である。第３図は、従来品及び本発
明適用品とのプレツシヤクツキング耐湿試験の結
果を示す特性図である。
１……半導体基板、２……電極、３……配線、
４……ポリイミド被膜、５……金−Si共晶、６…
…タブ部、７……リード部、８……コネクテイン
グワイヤ、９……フツ素系樹脂被膜、１３……モ
ールド樹脂体。
FIG. 1 is a sectional view of a main part of a semiconductor element having a polyimide film as a protective film of the semiconductor element. FIG. 2 is a sectional view of essential parts for explaining the semiconductor device according to the present invention. FIG. 3 is a characteristic diagram showing the results of a pressure-sucking moisture resistance test for a conventional product and a product to which the present invention is applied. 1... Semiconductor substrate, 2... Electrode, 3... Wiring,
4... Polyimide coating, 5... Gold-Si eutectic, 6...
...Tab portion, 7... Lead portion, 8... Connecting wire, 9... Fluorine resin coating, 13... Molded resin body.
Claims (1)
子表面の一部または全てをフツ素系樹脂で被覆し
た構造を有する半導体装置。1. A semiconductor device having a structure in which a part or all of the surface of a semiconductor element having a polyimide-based organic resin coating is coated with a fluorine-based resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7468079A JPS55166942A (en) | 1979-06-15 | 1979-06-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7468079A JPS55166942A (en) | 1979-06-15 | 1979-06-15 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61082001A Division JPS621236A (en) | 1986-04-11 | 1986-04-11 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55166942A JPS55166942A (en) | 1980-12-26 |
| JPS6148266B2 true JPS6148266B2 (en) | 1986-10-23 |
Family
ID=13554173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7468079A Granted JPS55166942A (en) | 1979-06-15 | 1979-06-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55166942A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57138165A (en) * | 1981-02-20 | 1982-08-26 | Nec Corp | Manufacture of semiconductor device |
| JPS62185341A (en) * | 1986-02-08 | 1987-08-13 | Mitsubishi Electric Corp | Resin sealed type semiconductor device |
| JPS63108641U (en) * | 1986-12-27 | 1988-07-13 |
-
1979
- 1979-06-15 JP JP7468079A patent/JPS55166942A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55166942A (en) | 1980-12-26 |
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