JPS62256457A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62256457A JPS62256457A JP61100096A JP10009686A JPS62256457A JP S62256457 A JPS62256457 A JP S62256457A JP 61100096 A JP61100096 A JP 61100096A JP 10009686 A JP10009686 A JP 10009686A JP S62256457 A JPS62256457 A JP S62256457A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resin film
- low temperature
- inorganic insulating
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 239000011248 coating agent Substances 0.000 claims abstract description 16
- 238000000576 coating method Methods 0.000 claims abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000000465 moulding Methods 0.000 claims abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 6
- 238000002161 passivation Methods 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract description 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 229910052682 stishovite Inorganic materials 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910052905 tridymite Inorganic materials 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000008602 contraction Effects 0.000 abstract 1
- 238000005336 cracking Methods 0.000 abstract 1
- 230000006866 deterioration Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- 230000001681 protective effect Effects 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 230000006378 damage Effects 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910007277 Si3 N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
［概要コ
塗布したコーティング樹脂膜とモールド樹脂との間に、
低温プラズマ成長させた無機絶縁膜、例えば、酸化シリ
コン膜、または、窒化シリコン膜を介在させる。そうす
ると、その介在させた絶縁膜がストレスの緩衝層となり
、半導体素子を被覆した保護膜の破壊が減少して、半導
体装置が高信頼化される。[Detailed Description of the Invention] [Summary] Between the applied coating resin film and the mold resin,
An inorganic insulating film grown by low-temperature plasma, such as a silicon oxide film or a silicon nitride film, is interposed. In this case, the interposed insulating film becomes a stress buffer layer, reducing damage to the protective film covering the semiconductor element, and making the semiconductor device highly reliable.
［産業上の利用分野］
本発明は半導体装置、特にモールド樹脂封止型半導体装
置の保護構造に関する。[Industrial Field of Application] The present invention relates to a protection structure for a semiconductor device, particularly a molded resin-encapsulated semiconductor device.
従前より、ＩＣ，ＬＳＩなどの半導体装置には、金属ケ
ースに半導体素子を収容したハーメチック封止型と、モ
ールド樹脂で固めたモールド樹脂封止型とがあり、後者
のモールド樹脂封止型半導体装置は廉価で大量生産でき
る特色があり、一般用として広く利用されている。Traditionally, semiconductor devices such as ICs and LSIs have been divided into hermetic sealing types, in which semiconductor elements are housed in metal cases, and mold resin sealing types, in which semiconductor elements are hardened with mold resin. It has the advantage of being inexpensive and mass-produced, and is widely used for general purposes.
しかし、このようなモールド樹脂封止型半導体装置にお
いても、勿論、その信頼性について十分な配慮が望まれ
ている。However, even in such a molded resin-encapsulated semiconductor device, sufficient consideration must be given to its reliability.
［従来の技術］
第２図はモールド樹脂封止型ＩＣ（モールド１Ｃ）の断
面概要図を示しており、１はリードフレ−ム、２は半導
体素子（チップ）、３はリードワイヤー、４はモールド
樹脂で、モールド樹脂４は加熱成形して固化させるエポ
キシ樹脂やシリコン樹脂等が用いられている。また、リ
ードフレーム１は、第２図に示すように整型された状態
では、半導体素子２を接着した部分がステージとなり、
モールド樹脂より外部に表出した部分がリードになるが
、本発明ではリードフレームと総称している。このリー
ドフレームは半導体素子の裏面を接着させるために、熱
膨張率が半導体に近位している金属材料、例えば、鉄ニ
ツケル合金材から成形されたものである。[Prior Art] Fig. 2 shows a schematic cross-sectional view of a molded resin-sealed IC (mold 1C), in which 1 is a lead frame, 2 is a semiconductor element (chip), 3 is a lead wire, and 4 is a mold. The molding resin 4 is made of epoxy resin, silicone resin, etc., which is heated and solidified. Furthermore, when the lead frame 1 is shaped as shown in FIG. 2, the part to which the semiconductor element 2 is bonded becomes a stage.
The parts exposed to the outside from the mold resin become leads, which are collectively referred to as lead frames in the present invention. This lead frame is molded from a metal material having a thermal expansion coefficient close to that of the semiconductor, such as an iron-nickel alloy material, in order to bond the back side of the semiconductor element.
他方、半導体素子の表面は直接モールド樹脂４に接触さ
せると色々と悪影響があるため、第３図に示すモールド
ｔＣの部分断面図のように、絶縁保護膜で被覆されてい
る。第３図において、１はリードフレーム、２は半導体
素子、５は素子上の配線層、６はパッシベーション膜、
７はコーティング樹脂膜、４はモールド樹脂で、パッシ
ベーション膜６は化学気相成長（ＣＶＤ）法で被着した
燐シリケートガラス（Ｐ Ｓ Ｇ）膜やプラズマＣＶＤ
法で被着した窒化シリコン（Ｓｉ３ Ｎ４ ）膜が用い
られ、この膜６は半導体素子２べの水分やアルカリイオ
ンの侵入を防ぎ、優れた被覆性をもつ材質の膜が使用さ
れる。On the other hand, if the surface of the semiconductor element is brought into direct contact with the mold resin 4, it will have various adverse effects, so it is covered with an insulating protective film as shown in the partial cross-sectional view of the mold tC shown in FIG. In FIG. 3, 1 is a lead frame, 2 is a semiconductor element, 5 is a wiring layer on the element, 6 is a passivation film,
7 is a coating resin film, 4 is a molding resin, and the passivation film 6 is a phosphorous silicate glass (PSG) film deposited by chemical vapor deposition (CVD) or plasma CVD.
A silicon nitride (Si3 N4) film deposited by a method is used, and this film 6 is made of a material that prevents moisture and alkali ions from entering the semiconductor element 2 and has excellent covering properties.
また、その上面のコーティング樹脂膜７も内部を保護す
るのが目的で、耐湿性をもたせ、且つ、塗布して表面を
平坦化させており、このコーティング樹脂膜として著名
なものに耐熱性・絶縁性の良いポリイミド膜がある。か
（してモールドＩＣの表面は、第３図のような断面構造
にして半導体素子を保護し、モールド樹脂で封止しであ
る。In addition, the coating resin film 7 on the top surface is also intended to protect the inside, and is made to have moisture resistance and is coated to flatten the surface.The most famous coating resin film is heat resistance and insulation. There is a polyimide film with good properties. (The surface of the molded IC is formed into a cross-sectional structure as shown in FIG. 3 to protect the semiconductor element, and is sealed with a molding resin.
［発明が解決しようとする問題点］
ところが、上記のようにコーティング樹脂膜７、例えば
、ポリイミド膜を用いた場合、確かに耐湿性と平坦化と
が得られるが、ポリイミド膜とモールド樹脂とは同じ有
機樹脂であるから、両者は極めて密着性が良い。[Problems to be Solved by the Invention] However, when the coating resin film 7, for example, a polyimide film is used as described above, moisture resistance and flatness can certainly be obtained, but the difference between the polyimide film and the molding resin is Since they are made of the same organic resin, both have extremely good adhesion.
そのため、パッシベーション膜にクランク（割れ）を与
えることがある。これは、モールド樹脂を加熱溶融して
成形し、次いで、冷却固化させる際、モールド樹脂は若
干収縮し、その時、凹凸あるパッシベーション膜に食い
込んだコーティング樹脂膜が、モールド樹脂によって引
っ張られて動き、その力（矢印で示す）によってパッシ
ベーション膜にクランクを与えるものである。Therefore, the passivation film may be cracked. This is because when molding resin is heated and melted and then cooled and solidified, the molding resin contracts slightly, and at that time, the coating resin film that has bitten into the uneven passivation film is pulled and moved by the molding resin. The force (indicated by the arrow) applies a crank to the passivation film.
しかし、このように、パッシベーション膜にクラックが
生じると、半導体素子の保護効果が減退して、その信頼
性が低下する。However, when cracks occur in the passivation film as described above, the protection effect of the semiconductor element is reduced and the reliability thereof is reduced.
本発明は、このようなパッシベーション膜のクランクを
減少させ゛て、信頼性を向上するためのモールド樹脂封
止型半導体装置を提案するものである。The present invention proposes a molded resin-encapsulated semiconductor device for reducing such cranking of the passivation film and improving reliability.
Ｆ問題点を解決するための手段］
その問題は、半導体素子上に塗布し固化させたコーティ
ング樹脂膜と、モールド樹脂との間に、低温プラズマ成
長させた無機絶縁膜、例えば、酸化シリコン膜や窒化シ
リコン膜が介在している半導体装置によって解決される
。Measures to Solve Problem F] The problem is that an inorganic insulating film grown by low-temperature plasma, such as a silicon oxide film or This problem is solved by a semiconductor device in which a silicon nitride film is interposed.
［作用］
部ち、本発明は、コーティング樹脂膜とモールド樹脂と
の間に、低温プラズマ成長させた無機絶縁膜、例えば、
酸化シリコン膜、または、窒化シリコン膜を介在させる
。そうすると、その介在させた絶縁膜がストレスの緩衝
層となって、パッシベーション膜の破壊が減少し、半導
体装置が高僧転化される。[Function] Firstly, the present invention provides an inorganic insulating film grown by low-temperature plasma between the coating resin film and the mold resin, for example,
A silicon oxide film or a silicon nitride film is interposed. Then, the interposed insulating film acts as a stress buffer layer, reducing breakdown of the passivation film and improving the semiconductor device.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図は本発明にかかるモールドＩＣの部分断面図を示
しており、１０が低温プラズマ成長させた無機絶縁膜の
酸化シリコン（Ｓｉ０２）膜である。FIG. 1 shows a partial cross-sectional view of a molded IC according to the present invention, and numeral 10 is a silicon oxide (Si02) film, which is an inorganic insulating film grown by low-temperature plasma.
その寵の部材は、第３図と同じく、１はリードフレーム
、２は半導体素子、５は素子上の配線層。As in FIG. 3, the key components are a lead frame 1, a semiconductor element 2, and a wiring layer 5 on the element.
６はパッシベーション膜、７はコーティング樹脂膜、４
はモールド樹脂である。6 is a passivation film, 7 is a coating resin film, 4
is mold resin.
低温プラズマ成長させる５ｉ０２膜１０は、その基板加
熱温度を１００〜２００°Ｃと低くして被着する。The 5i02 film 10 grown by low temperature plasma is deposited at a low substrate heating temperature of 100 to 200°C.
通常のＣＶＤ法による加熱温度は３００〜４００℃であ
るが、このような低温度で被着すると、膜質が若干悪く
なるが、軟らかくなる。そのため、モールド樹脂が固化
して収縮する時、その応力の緩衝層となって、コーティ
ング樹脂膜を動かすことがなくなる。その膜厚は０．２
〜０．６μｍが適当であり、この無機絶縁膜はモールド
整型時にクランクが入っても構わない。このような構造
にすれば、モールド整型時のパンシベーション［６のク
ランクが解消し、半導体装置の信顛性が向上する。The heating temperature in the usual CVD method is 300 to 400°C, but if the film is deposited at such a low temperature, the film quality will deteriorate slightly, but it will become softer. Therefore, when the mold resin solidifies and contracts, it acts as a stress buffer layer and prevents the coating resin film from moving. Its film thickness is 0.2
~0.6 μm is appropriate, and this inorganic insulating film may be cranked during mold shaping. With such a structure, the cranking of pansivation [6] during mold shaping is eliminated, and the reliability of the semiconductor device is improved.
次に、これらの保護膜の形成方法の概要を説明すると、
まず、基板加熱温度を３００〜４００℃にして、膜厚８
０００人のＰＳＧ膜（パッシベーション膜６）を被着し
、その上に、膜厚２μｍ程度のポリイミド膜（コーティ
ング樹脂膜７）を塗布して、約４００℃でキュアさせる
。次いで、上記のような５ｉ０２膜（無機絶縁膜１０）
を、基板加熱温度１００〜２００℃と低くしてプラズマ
ＣＶＤ法で膜厚４０００人程度に被着する。なお、リー
ドワイヤー３ （第２図参照）をポンディングするポン
ディングバンドの窓開けは、その後に、フォトプロセス
を適用して保護膜全部を同時におこなう。Next, the outline of the method for forming these protective films will be explained as follows.
First, the substrate heating temperature is set to 300 to 400°C, and the film thickness is 8
000 PSG film (passivation film 6) is applied, and a polyimide film (coating resin film 7) with a thickness of about 2 μm is applied thereon and cured at about 400°C. Next, a 5i02 film (inorganic insulating film 10) as described above is formed.
The substrate is heated to a low temperature of 100 to 200° C., and the film is deposited to a thickness of about 4,000 by plasma CVD. Incidentally, the opening of the bonding band for bonding the lead wire 3 (see FIG. 2) is then performed simultaneously on all the protective films by applying a photo process.
上記は、低温プラズマ成長させる無機絶縁膜１０として
ＳｉＯ２膜で説明しているが、Ｓｉ３Ｎ４膜を用いる場
合も、同様に低温プラズマ成長させて、形成方法も略同
様で、同様の効果が得られる。In the above description, a SiO2 film is used as the inorganic insulating film 10 grown by low-temperature plasma, but when using a Si3N4 film, low-temperature plasma growth is similarly performed, the formation method is substantially the same, and similar effects can be obtained.
［発明の効果］
以上の説明から明らかなように、本発明による保護膜の
構造にすれば、パッシベーション膜の破壊が減少して、
半導体装置の高信転化に顕著な効果があるものである。[Effects of the Invention] As is clear from the above explanation, the structure of the protective film according to the present invention reduces the destruction of the passivation film.
This has a remarkable effect on improving the reliability of semiconductor devices.
第１図は本発明にかかるモールドＩＣの部分断面図、
第２図はモールド【Ｃの断面図、
第３図は従来のモールドＩＣの部分断面図である。
図において、
１はリードフレーム、 ２は半導体素子、３はリード
ワイヤー、 ４はモールド樹脂、５は配線層、
６はパッシベーション膜、７はコーティング樹脂
膜、
１０は低温プラズマ成長させた無機絶縁膜を示している
。
ｍ１ｌ１片浄か３七→レドエＣの湾状ｌ介面図第１図
七−ルｇＩＣの由γ面圓
第 ２ 図FIG. 1 is a partial sectional view of a molded IC according to the present invention, FIG. 2 is a sectional view of a mold [C], and FIG. 3 is a partial sectional view of a conventional molded IC. In the figure, 1 is a lead frame, 2 is a semiconductor element, 3 is a lead wire, 4 is a molding resin, 5 is a wiring layer,
6 is a passivation film, 7 is a coating resin film, and 10 is an inorganic insulating film grown by low-temperature plasma. m1l1Katajika 37->Bay l-interface view of Redoe C Figure 1 Figure 7-G IC diagram Figure 2
Claims (2)
脂膜と、モールド樹脂との間に、低温プラズマ成長させ
た無機絶縁膜が介在していることを特徴とする半導体装
置。(1) A semiconductor device characterized in that an inorganic insulating film grown by low-temperature plasma is interposed between a coating resin film applied and solidified on a semiconductor element and a molding resin.
リコン膜、または、窒化シリコン膜であることを特徴と
する特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the inorganic insulating film grown by low-temperature plasma is a silicon oxide film or a silicon nitride film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61100096A JPS62256457A (en) | 1986-04-29 | 1986-04-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61100096A JPS62256457A (en) | 1986-04-29 | 1986-04-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62256457A true JPS62256457A (en) | 1987-11-09 |
Family
ID=14264870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61100096A Pending JPS62256457A (en) | 1986-04-29 | 1986-04-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62256457A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183431A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Semiconductor device and its manufacture |
| JP2005508763A (en) * | 2001-11-09 | 2005-04-07 | ３デー プリュー | Device for hermetic encapsulation of components protected from arbitrary stress |
| CN105914188A (en) * | 2015-02-24 | 2016-08-31 | 丰田自动车株式会社 | Semiconductor module |
-
1986
- 1986-04-29 JP JP61100096A patent/JPS62256457A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07183431A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Semiconductor device and its manufacture |
| JP2005508763A (en) * | 2001-11-09 | 2005-04-07 | ３デー プリュー | Device for hermetic encapsulation of components protected from arbitrary stress |
| CN105914188A (en) * | 2015-02-24 | 2016-08-31 | 丰田自动车株式会社 | Semiconductor module |
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