JPH01135052A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01135052A JPH01135052A JP62292121A JP29212187A JPH01135052A JP H01135052 A JPH01135052 A JP H01135052A JP 62292121 A JP62292121 A JP 62292121A JP 29212187 A JP29212187 A JP 29212187A JP H01135052 A JPH01135052 A JP H01135052A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- resin layer
- semiconductor device
- semiconductor
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 141
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 229920005989 resin Polymers 0.000 claims abstract description 71
- 239000011347 resin Substances 0.000 claims abstract description 71
- 238000007789 sealing Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 10
- 229920002050 silicone resin Polymers 0.000 claims abstract description 4
- 230000001681 protective effect Effects 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000009434 installation Methods 0.000 claims 1
- 230000008646 thermal stress Effects 0.000 abstract description 9
- 239000007788 liquid Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000010008 shearing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に関し、特に、比較的大型の半導
体素子を備えた半導体装置における信頼性の向上などに
適用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a technique that is effective when applied to improve reliability in a semiconductor device including a relatively large semiconductor element.
パッケージ内に封入された半導体素子の耐湿性を向上さ
せることにより、半導体素子とボンディング・ワイヤと
の接続部における腐蝕などを防止して信頼性を向上させ
る技術としては、たとえば、特開昭５６−２３７５９号
公報に開示される技トトテが知られている。For example, Japanese Unexamined Patent Application Publication No. 1983-1997 discloses a technique for improving reliability by improving the moisture resistance of a semiconductor element sealed in a package to prevent corrosion at the connection between the semiconductor element and bonding wires. The technique Totote disclosed in Japanese Patent No. 23759 is known.
その概要は、半導体素子の表面に露出した接続電極とリ
ード・フレームとをボンディング・ワイヤによって電気
的に接続した後、パッケージ内への封入に先立って、半
導体素子に樹脂を滴下し、滴下された塊状を呈する峙（
脂によって、少なくとも半導体素子の露出するボンディ
ング・パッドとこのボンディング・パッドに接続された
ボンディング・ワイヤとを包囲するように被覆したもの
である。The outline is that after the connection electrodes exposed on the surface of the semiconductor element and the lead frame are electrically connected using bonding wires, resin is dripped onto the semiconductor element prior to encapsulating it in a package. A blocky surface (
At least the exposed bonding pads of the semiconductor element and the bonding wires connected to the bonding pads are coated with oil so as to surround them.
ところが、上記のような従来技術においては、半導体素
子の耐湿性を向上させることができるという利点はある
ものの、半導体素子の高集積化などにともなって半導体
素子自体が大型化すると、半導体素子と塊状の樹脂との
間における熱膨張率の差異などに起因して、半導体素子
の表面などに大きな熱応力が作用することが避けられず
、半導体素子とともに包囲されるボンディング・ワイヤ
の端部が半導体素子の接続電極から不時に剥離するなど
して、半導体装置の動作の信頼性が低下するという問題
がある。However, although the conventional technology described above has the advantage of being able to improve the moisture resistance of the semiconductor element, as the semiconductor element itself becomes larger due to higher integration of semiconductor elements, it becomes difficult for the semiconductor element to become bulky. Due to the difference in coefficient of thermal expansion between the semiconductor element and the resin, it is unavoidable that large thermal stress will be applied to the surface of the semiconductor element, and the end of the bonding wire surrounded by the semiconductor element will be exposed to the semiconductor element. There is a problem in that the reliability of the operation of the semiconductor device decreases due to inadvertent peeling off from the connection electrode of the semiconductor device.
さらに、金型などによって所定の形状に成形される封止
樹脂などに埋設することにより、半導体素子を封止する
いわゆる樹脂封止型の半導体装置おいては、半導体素子
とリード・フレームとを接続するボンディング・ワイヤ
が、半導体素子に被着された塊状の樹脂と、その外側を
さらに包囲する封止樹脂の両方に埋設された状態となる
ため、温度変化などに際して、各樹脂の界面においてボ
ンディング・ワイヤに剪断応力が作用し、ボンディング
・ワイヤが不時に破断する恐れがあるなど、種々の問題
があることを本発明者は見い出した。Furthermore, in so-called resin-encapsulated semiconductor devices, in which the semiconductor element is sealed by embedding it in a sealing resin that is molded into a predetermined shape using a mold, etc., the semiconductor element and the lead frame are connected. The bonding wires are buried in both the lumpy resin adhered to the semiconductor element and the sealing resin that surrounds the outside of the semiconductor element, so the bonding wires are buried at the interface between each resin in the event of a temperature change, etc. The inventor has discovered that there are various problems such as shearing stress acting on the wire and the possibility of the bonding wire breaking unexpectedly.
本発明の目的は、半導体素子に対する熱応力などの発生
を招くことなく、耐湿性を向上させることが可能な半導
体装置およびその製造技術を提供することにある。An object of the present invention is to provide a semiconductor device and a manufacturing technique thereof that can improve moisture resistance without causing thermal stress to the semiconductor element.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明は、支持部材と、支持部材に搭載され
、表面に樹脂層が被着された半導体素子と、半導体素子
と支持部材とを接続するボンディング・ワイヤとで半導
体装置を構成したものである。That is, in the present invention, a semiconductor device is constructed of a support member, a semiconductor element mounted on the support member and having a resin layer applied to its surface, and bonding wires that connect the semiconductor element and the support member. be.
また、本発明は、半導体素子における最終保護膜および
最終保護膜から露出した接続電極の全面に樹脂層を形成
する第１の段階と、支持部材に搭載された半導体素子の
接続電極の上に被着された樹脂層を突き破ることにより
、接続電極と支持部材との間に導体からなるボンディン
グ・ワイヤを架設する第２の段階とを有する半導体装置
の製造技術を提供するものである。Further, the present invention includes a first step of forming a resin layer on the entire surface of the final protective film of the semiconductor element and the connection electrode exposed from the final protective film, and a first step of forming a resin layer on the entire surface of the connection electrode of the semiconductor element mounted on the support member. The present invention provides a semiconductor device manufacturing technique including a second step of constructing a bonding wire made of a conductor between the connection electrode and the support member by breaking through the attached resin layer.
上記した手段によれば、半導体素子の表面に被着される
樹脂層の中に、半導体素子の接続電極と支持部材とを接
続するボンディング・ワイヤが埋没することがないので
、熱応力などに起因して、不時に、ボンディング・ワイ
ヤの切断や半導体素子からの剥離などを生じることが防
止されるとともに、半導体素子の接続電極の上部に被着
され、ボンディング・ワイヤによって突き破られた樹脂
層は、自身の弾性によってボンディング・ワイヤと接続
電極部との接続部の周囲に充満された状態となり、半導
体素子の表面が樹脂層で確実に覆われるのでの耐湿性が
向上する。According to the above-described means, the bonding wire that connects the connection electrode of the semiconductor element and the support member is not buried in the resin layer that is adhered to the surface of the semiconductor element, so that the bonding wire that connects the connection electrode of the semiconductor element and the support member is not buried, which is caused by thermal stress or the like. This prevents the bonding wire from being accidentally cut or peeled off from the semiconductor element, and also prevents the resin layer that is adhered to the top of the connection electrode of the semiconductor element and is pierced by the bonding wire. Due to its own elasticity, it fills the area around the connection between the bonding wire and the connection electrode, and the surface of the semiconductor element is reliably covered with the resin layer, improving moisture resistance.
第１図（ａ）およびら）は、本発明の一実施例である半
導体装置の製造方法の一例を工程順に示す説明図であり
、第２図はこの製造方法によって製造された半導体装置
の一例を示す断面図である。FIGS. 1(a) and 1(a) are explanatory diagrams showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps, and FIG. 2 is an example of a semiconductor device manufactured by this manufacturing method. FIG.
中央に設けられたタブ１ａと、このタブ１ａを取り囲む
ように配設された複数のリード１ｂからなるリード・フ
レーム１ （支持部材）において、中央部のタブｌａの
上には、所定の図示しない集積回路などが形成された半
導体素子２が搭載されている。In a lead frame 1 (supporting member) consisting of a tab 1a provided in the center and a plurality of leads 1b arranged to surround this tab 1a, a predetermined (not shown) tab is placed above the tab 1a in the center. A semiconductor element 2 on which an integrated circuit or the like is formed is mounted.
この半導体素子２は、たとえば、前段のウェハ処理工程
などにおいて、ンリコン単結晶基板などからなる図示し
ない半導体ウェハにフォトリングラフィを施すことによ
り、−括して形成されたものであり、該半導体ウェハを
分割することにより、個々に分離されたものである。This semiconductor element 2 is formed in one step, for example, by applying photolithography to a semiconductor wafer (not shown) made of a silicon single crystal substrate or the like in a previous wafer processing step. These are separated into individual parts by dividing them.
半導体素子２の表面には、絶縁性の最終保護膜２ａが形
成され、この最終保護膜２ａの一部を除去することによ
って、該半導体素子２の内部に形成された内部配線構造
２ｂに接続された複数の接続電極２Ｃが外部に露出して
いる。An insulating final protective film 2a is formed on the surface of the semiconductor element 2, and by removing a portion of this final protective film 2a, the semiconductor element 2 is connected to the internal wiring structure 2b formed inside the semiconductor element 2. A plurality of connection electrodes 2C are exposed to the outside.
この場合、半導体素子２の表面には、たとえば、シリコ
ーン系の樹脂などからなる樹脂層３が被着されている。In this case, a resin layer 3 made of, for example, silicone resin is adhered to the surface of the semiconductor element 2.
この樹脂層３は、たとえば、前述の図示しない半導体ウ
ェハの状、熊において、回転塗布などの方法により、液
状の樹脂を塗布した後、加熱硬化処理（キュア）などを
施すことによって、たとえば、１０μｍ程度の厚さに均
一に形成されるものである。（第１の段階） −
そして、樹脂層３が全面に形成された図示しない半導体
ウェハからダイシングにより切り出された半導体素子２
をリード・フレーム１に搭載した状態が第１図（ａ）で
あり、この第１図（ａ）の状態から、樹脂層３が全面に
被着された状態の半導体素子２におけろ複数の接続電極
２ｃと、リード・フレーム１の複数のり−ド１ｂとの間
に金属線などの導体からなるボンディング・ワイヤ４が
、良く知られた超音波ボンディングなどにより架設され
る。This resin layer 3 is formed, for example, to a thickness of 10 μm by applying a liquid resin on the aforementioned semiconductor wafer (not shown) by a method such as spin coating, and then subjecting it to heat curing. It is formed uniformly to a certain thickness. (First step) - Then, the semiconductor element 2 is cut out by dicing from a semiconductor wafer (not shown) on which the resin layer 3 is formed on the entire surface.
The state shown in FIG. 1(a) is that the semiconductor element 2 is mounted on the lead frame 1, and from this state shown in FIG. 1(a), a plurality of A bonding wire 4 made of a conductor such as a metal wire is installed between the connection electrode 2c and the plurality of bonds 1b of the lead frame 1 by well-known ultrasonic bonding or the like.
すなわち、図示しないボンディング工具を介して印加さ
れた超音波振動の二不ルギにより、すでに接続電極２ｃ
の上に薄く被着している樹脂層３を突き破ってボンディ
ング・ワイヤ４の一端を半導゛体素子２の接続電極２ｃ
に接続し、他端をリード１ｂの側にボンディングするこ
とにより、半導体素子２の複数の接続電極２ｃおよび複
数のリードｔｂが個々に電気的に接続され、第１図ら）
に示される状態となる。（第２の段階）
この時、接続電極２ｃの上面に被着し、ボンディング・
ワイヤ４によって突き破られる樹脂層３Ｃは、それ自体
の弾性による復元性によって、ボンディング・ワイヤ４
と接続電極２ｃとの接続部の周囲の楔形の空間に充填さ
れた状態となり、半導体素子２の表面は、全体が樹脂層
３によって確実に覆われた状態となる。That is, the connection electrode 2c has already been damaged by the ultrasonic vibration applied via a bonding tool (not shown).
One end of the bonding wire 4 is connected to the connecting electrode 2c of the semiconductor element 2 by breaking through the resin layer 3 thinly applied thereon.
By bonding the other end to the lead 1b side, the plurality of connection electrodes 2c and the plurality of leads tb of the semiconductor element 2 are electrically connected to each other individually (see FIG. 1).
The state shown in is reached. (Second stage) At this time, it is deposited on the upper surface of the connection electrode 2c, and the bonding
The resin layer 3C that is pierced by the wire 4 is resilient to the bonding wire 4 due to its own elasticity.
The wedge-shaped space around the connection portion between the resin layer 3 and the connection electrode 2c is filled, and the entire surface of the semiconductor element 2 is reliably covered with the resin layer 3.
その後、図示しない金型などに、リード・フレームｌの
タブ１ａに搭載された半導体素子２を収容した状態で、
封止樹脂５を金型内に加圧充填することにより、図示し
ない金型によって、所定のパッケージに成形された当該
封止樹脂５によって半導体素子２が封止され、さらに、
成形された封止樹脂５から外部に突出した複数のリード
１ｂの切断や曲げ工程などを経ることによって、第２図
に示されるように、いわゆる樹脂封止型の半導体装置６
が形成される。Thereafter, with the semiconductor element 2 mounted on the tab 1a of the lead frame l accommodated in a mold (not shown), etc.,
By pressurizing and filling the sealing resin 5 into the mold, the semiconductor element 2 is sealed with the sealing resin 5 molded into a predetermined package using a mold (not shown), and further,
As shown in FIG. 2, a so-called resin-sealed semiconductor device 6 is formed by cutting and bending the plurality of leads 1b protruding outward from the molded sealing resin 5.
is formed.
なお、半導体素子２に対する樹脂層３を形成する時期と
しては、上述のように、半導体ウエノ１の段階に限らず
、半導体ウェハから切り出され、リード・フレーム１に
搭載された状態で行ってもよく、さらに半導体素子２に
被着された樹脂層３の加熱硬化処理は、ボンディング・
ワイヤ４を架設した後に行ってもよいものである。Note that the timing for forming the resin layer 3 on the semiconductor element 2 is not limited to the stage of the semiconductor wafer 1 as described above, but may be performed after the semiconductor wafer is cut out and mounted on the lead frame 1. Furthermore, the heat curing treatment of the resin layer 3 adhered to the semiconductor element 2 is performed by bonding and
This may be done after the wire 4 is installed.
ここで、本実施例では、樹脂層３が半導体素子２の全面
に薄く被着されているため、半導体素子２と封止樹脂５
との界面に溜りやすい水分などから半導体素子２が確実
に保護され、耐湿性が向上するとともに、半導体素子２
とリード１ｂとの間に架設されるボンディング・ワイヤ
４は、封止樹脂５の内部に封止された第２図に示される
状態では、当該封止樹脂５のみに埋設された状態となっ
ている。Here, in this embodiment, since the resin layer 3 is thinly applied over the entire surface of the semiconductor element 2, the semiconductor element 2 and the sealing resin 5
The semiconductor element 2 is reliably protected from moisture that tends to accumulate at the interface between the semiconductor element 2 and the semiconductor element 2.
In the state shown in FIG. 2 in which the bonding wire 4 is installed between the lead 1b and the lead 1b and is sealed inside the sealing resin 5, it is buried only in the sealing resin 5. There is.
このため、熱膨張率の異なる異種の物質に同時に埋設さ
れ状態となることに起因して、ボンディング・ワイヤ４
の途中や、接続電極２Ｃに対する接続端などが熱応力な
どを受けることが回避され、ボンディング・ワイヤ４が
不時に破断することが防止される。For this reason, the bonding wire 4 may be buried in different materials with different coefficients of thermal expansion at the same time.
This prevents the middle portion of the bonding wire 4 and the connection end to the connection electrode 2C from being subjected to thermal stress, thereby preventing the bonding wire 4 from breaking inadvertently.
また、半導体素子２の寸法が比較的大きい場合でも、表
面に被着される樹脂層３が薄いので、大きな熱応力が発
生することもない。Furthermore, even if the dimensions of the semiconductor element 2 are relatively large, large thermal stress will not occur because the resin layer 3 applied to the surface is thin.
なお、以上の説明では、第２図に示されるように樹脂封
止型の半導体装置６について説明したが、第３図に示さ
れるような、いわゆるピン・グリッド・アレイ型の封止
形態を呈する半導体装置６ａに適用してもよいものであ
る。In the above description, the resin-sealed semiconductor device 6 as shown in FIG. 2 has been described, but the semiconductor device 6 exhibits a so-called pin grid array type encapsulation form as shown in FIG. 3. This may be applied to the semiconductor device 6a.
すなわち、第３図の半導体装置６ａは、図示しない配線
構造および複数のビン７が設けられた配線基板７ （支
持部材）の上に、樹脂層３が被着された半導体素子２を
搭載し、ボンディング・ワイヤ４によって半導体素子２
の接続電極２Ｃと配線基板７とを電気的に接続し、さら
に、配線基板子に搭載された半導体素子２は、該配線基
板７に冠着されたキャンプ８およびキャップ８の内部に
充満された封止樹脂９によって封止されるようにしたも
のである。That is, the semiconductor device 6a in FIG. 3 has a semiconductor element 2 on which a resin layer 3 is deposited mounted on a wiring board 7 (supporting member) provided with a wiring structure (not shown) and a plurality of bins 7. Semiconductor element 2 by bonding wire 4
The connecting electrode 2C and the wiring board 7 are electrically connected, and the semiconductor element 2 mounted on the wiring board element is filled in the camp 8 and the cap 8 attached to the wiring board 7. It is configured to be sealed with a sealing resin 9.
また、第４図に示される半導体装１１１６ｂは、キャッ
プ８と配線基板７のみによって半導体素子２を封止した
ものである。Further, a semiconductor device 1116b shown in FIG. 4 is one in which a semiconductor element 2 is sealed with only a cap 8 and a wiring board 7.
このように、本実施例によれば以下の効果を得ることが
できる。As described above, according to this embodiment, the following effects can be obtained.
（１）、半導体素子２における最終保護膜２ａおよびこ
の最終保護膜２ａから露出した接続電極２Ｃの全域に樹
脂層３を薄く被着する第１の段階と、半導体素子２の接
続電極２Ｃの上に被着された樹脂層３を、超音波振動の
エネルギなどによって突き破ることにより、接続電極２
Ｃと、リード・フレーム１のリードｌｂとを接続する第
２の段階とを経て、ボンディング・ワイヤ４の架設が行
われるので、ボンディング・ワイヤ４が樹脂層３の内部
に埋没することがなく、たとえば、封止樹脂５の内部に
封止される場合には、当該封止樹脂５のみに埋設された
状態となる。(1) A first step of thinly depositing the resin layer 3 over the entire area of the final protective film 2a of the semiconductor element 2 and the connecting electrode 2C exposed from the final protective film 2a; By using ultrasonic vibration energy or the like to break through the resin layer 3 adhered to the connecting electrode 2.
Since the bonding wire 4 is installed after the second step of connecting the lead lb of the lead frame 1 and the lead lb of the lead frame 1, the bonding wire 4 is not buried inside the resin layer 3. For example, when it is sealed inside the sealing resin 5, it will be in a state where it is buried only in the sealing resin 5.
このため、熱膨張率の異なる異種の物質に同時に埋設さ
れ状態となることに起因して、ボンディング・ワイヤ４
の途中や、接続電極２Ｃに対する接続端などが熱応力な
どを受けることが回避され、ボンディング・ワイヤ４が
不時に破断することが防止されるとともに、半導体素子
２０寸法が比較的大きい場合でも、表面に被着される樹
脂層３が薄いので、大きな熱応力が発生することもない
。For this reason, the bonding wire 4 may be buried in different materials with different coefficients of thermal expansion at the same time.
This prevents the bonding wire 4 from being exposed to thermal stress, etc., and the connection end to the connection electrode 2C, thereby preventing the bonding wire 4 from breaking unexpectedly, and even when the semiconductor element 20 is relatively large, the surface Since the resin layer 3 to be applied is thin, large thermal stress does not occur.
また、半導体素子２の全面に薄く被着された樹脂層３に
より、半導体素子２と、半導体素子２が封止される封止
樹脂５との界面に溜りやすい水分などから半導体素子２
が確実に保護され、耐湿性が向上する。In addition, the resin layer 3 thinly deposited on the entire surface of the semiconductor element 2 protects the semiconductor element 2 from moisture that tends to accumulate at the interface between the semiconductor element 2 and the sealing resin 5 in which the semiconductor element 2 is sealed.
is reliably protected and moisture resistance is improved.
（２）、前記（１）の結果、不時のボンディング・ワイ
ヤ４の破断や、ボンディング・ワイヤ４と半導体素子２
の接続電極２Ｃとの接合部の腐蝕などに起因する導通不
良の発生が回避され、半導体装置６の動作の信頼性を向
上させることができる。(2) As a result of (1) above, the bonding wire 4 may be accidentally broken or the bonding wire 4 and the semiconductor element 2 may be damaged.
The occurrence of poor conduction due to corrosion of the joint with the connection electrode 2C can be avoided, and the reliability of the operation of the semiconductor device 6 can be improved.
（３）、前記（１）の結果、半導体装置の製造における
生産性が向上する。(3) As a result of (1) above, productivity in manufacturing semiconductor devices is improved.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor.
たとえば、半導体装置の封止形態としては、樹脂封止型
やピン・グリッド・アレイ型のものに限らず、他のいか
なる封止形態のものであってもよい。For example, the sealing form of the semiconductor device is not limited to a resin sealing type or a pin grid array type, but any other sealing form may be used.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である半導体装置およびそ
の製造技術に適用した場合について説明したが、これに
限定されるものではなく、一般の電子部品の製造技術な
どに広く適用できる。In the above explanation, the invention made by the present inventor was mainly applied to the field of application which is the background of the invention, which is a semiconductor device and its manufacturing technology. It can be widely applied to manufacturing technology.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、支持部材と、該支持部材に搭載され、表面に
樹脂層が被着された半導体素子と、該半導体素子と前記
支持部材とを接続するボンディング・ワイヤとからなる
構造であるため、半導体素子の表面に被着される樹脂層
の中に、半導体素子の接続電極と支持部材とを接続する
ボンディング・ワイヤが埋没することがないので、熱応
力などに起因して、不時に、ボンディング・ワイヤの切
断や半導体素子からの剥離などを生じることが防止され
るとともに、半導体素子の接続電極の上部に被着され、
ボンディング・ワイヤによって突き破られた樹脂層は、
自身の弾性によってボンディング・ワイヤと接続電極部
との接続部の周囲に充満された状態となり、半導体素子
の表面が樹脂層に確実に覆われるので、該半導体素子の
耐湿性が向上する。That is, since the structure is made up of a support member, a semiconductor element mounted on the support member and having a resin layer coated on its surface, and bonding wires that connect the semiconductor element and the support member, the semiconductor element Since the bonding wires that connect the connection electrodes of the semiconductor element and the support member are not buried in the resin layer that is adhered to the surface of the It is possible to prevent cutting of the semiconductor element or peeling off from the semiconductor element, and also to coat the upper part of the connection electrode of the semiconductor element.
The resin layer pierced by the bonding wire is
Due to its own elasticity, the resin layer fills the area around the connection between the bonding wire and the connection electrode, and the surface of the semiconductor element is reliably covered with the resin layer, thereby improving the moisture resistance of the semiconductor element.
また、半導体素子における最終保護膜および該最終保護
膜から露出した接続電極の全面に樹脂層を形成する第１
の段階と、支持部材に搭載された前記半導体素子の前記
接続電極の上に被着された前記樹脂層を突き破ることに
より、該接続電極と前記支持部材との間に導体からなる
ボンディング・ワイヤを架設する第２の段階とを行うの
で、半導体素子の表面に被着される樹脂層の中に、半導
体素子の接続電極と支持部材とを接続するボンディング
・ワイヤが埋没することがなく、熱応力などに起因して
、不時に、ボンディング・ワイヤの切断や半導体素子か
らの剥離などを生じることが防止されるとともに、半導
体素子の接続電極の上部に被着され、ボンディング・ワ
イヤによって突き破られた樹脂層は、自身の弾性によっ
てボンディング・ワイヤと接続電極部との接続部の周囲
に充満された状態となり、半導体素子の表面が樹脂層に
確実に覆われるので、該半導体素子の耐湿性が向上する
。In addition, a first resin layer is formed on the entire surface of the final protective film in the semiconductor element and the connection electrode exposed from the final protective film.
A bonding wire made of a conductor is inserted between the connection electrode and the support member by breaking through the resin layer deposited on the connection electrode of the semiconductor element mounted on the support member. Since the second stage of erection is performed, the bonding wires that connect the connection electrodes of the semiconductor element and the support member are not buried in the resin layer applied to the surface of the semiconductor element, and thermal stress is avoided. This prevents the bonding wire from being accidentally cut or peeled off from the semiconductor element due to Due to its own elasticity, the resin layer fills the area around the connection between the bonding wire and the connection electrode, ensuring that the surface of the semiconductor element is covered with the resin layer, improving the moisture resistance of the semiconductor element. do.
第１図（ａ）および（ｂＪは本発明の一実施例である半
導体装置の製造方法の一例を工程順に示す説明図、第２
図は本発明の一実施例である半導体装置の一例を示す断
面図、
第３図は同じく半導体装置の一例を示す断面図、第４図
は同じく半導体装置の一例を示す断面図である。
１・・・リード・フレーム（支持部材）、１ａ・・・タ
ブ、ｌｂ・・・リード、２・・・半導体素子、２ａ・・
・最終保護膜、２ｂ・・・内部配線構造、２Ｃ・・・接
続電極、３・・・樹脂層、４・・・ボンディング・ワイ
ヤ、５・・・封止樹脂、６．６ａ、６ｂ・・・半導体装
置、７・・・配線基板（支持部材）、７ａ・・・ビン、
８・・・キャップ、９・・・封止樹脂。FIGS. 1(a) and 1(b) are explanatory diagrams showing an example of a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps;
3 is a sectional view showing an example of a semiconductor device, and FIG. 4 is a sectional view showing an example of a semiconductor device. DESCRIPTION OF SYMBOLS 1... Lead frame (supporting member), 1a... Tab, lb... Lead, 2... Semiconductor element, 2a...
- Final protective film, 2b... Internal wiring structure, 2C... Connection electrode, 3... Resin layer, 4... Bonding wire, 5... Sealing resin, 6.6a, 6b... - Semiconductor device, 7... wiring board (supporting member), 7a... bottle,
8... Cap, 9... Sealing resin.
Claims (1)
が被着された半導体素子と、該半導体素子と前記支持部
材とを接続するボンディング・ワイヤとからなることを
特徴とする半導体装置。 ２、前記樹脂層は、前記ボンディング・ワイヤの架設に
先立って前記半導体素子の全面に被着され、前記ボンデ
ィング・ワイヤは、前記半導体素子の最終保護膜から露
出した接続電極の上に被着された前記樹脂層を超音波振
動の印加によって突き破ることにより、該接続電極に接
続されていることを特徴とする特許請求の範囲第１項記
載の半導体装置。 ３、前記樹脂層がシリコーン系の樹脂からなり、前記半
導体素子の表面にほぼ１０μｍ程度の厚さに均一に被着
されていることを特徴とする特許請求の範囲第１項記載
の半導体装置。 ４、前記樹脂層は、複数の半導体素子が一括して形成さ
れる半導体ウェハの段階で、回転塗布により一括して被
着されることを特徴とする特許請求の範囲第１項記載の
半導体装置。 ５、前記支持部材がリードフレームであり、前記半導体
素子が封止樹脂中に埋設された封止形態よりなることを
特徴とする特許請求の範囲第１項記載の半導体装置。 ６、前記支持部材が配線基板であり、ピン・グリッド・
アレイ型の封止形態よりなることを特徴とする特許請求
の範囲第１項記載の半導体装置。 ７、半導体素子における最終保護膜および該最終保護膜
から露出した接続電極の全面に樹脂層を形成する第１の
段階と、支持部材に搭載された前記半導体素子の前記接
続電極の上に被着された前記樹脂層を突き破ることによ
り、該接続電極と前記支持部材との間に導体からなるボ
ンディング・ワイヤを架設する第２の段階とを有するこ
とを特徴とする半導体装置の製造方法。 ８、前記樹脂層がシリコーン系の樹脂からなり、前記半
導体素子の表面にほぼ１０μｍ程度の厚さに均一に被着
されることを特徴とする特許請求の範囲７項記載の半導
体装置の製造方法。 ９、前記樹脂層は、複数の半導体素子が一括して形成さ
れる半導体ウェハの段階で、回転塗布により一括して被
着されることを特徴とする特許請求の範囲第７項記載の
半導体装置の製造方法。 １０、前記支持部材がリードフレームであり、前記半導
体素子が封止樹脂中に埋設された封止形態よりなること
を特徴とする特許請求の範囲第７項記載の半導体装置の
製造方法。 １１、前記支持部材が配線基板であり、ピン・グリッド
・アレイ型の封止形態よりなることを特徴とする特許請
求の範囲第７項記載の半導体装置の製造方法。[Scope of Claims] 1. Consisting of a support member, a semiconductor element mounted on the support member and having a resin layer adhered to its surface, and a bonding wire connecting the semiconductor element and the support member. A semiconductor device characterized by: 2. The resin layer is deposited on the entire surface of the semiconductor element prior to installation of the bonding wire, and the bonding wire is deposited on the connection electrode exposed from the final protective film of the semiconductor element. 2. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the connection electrode by piercing the resin layer by applying ultrasonic vibration. 3. The semiconductor device according to claim 1, wherein the resin layer is made of silicone resin and is uniformly applied to the surface of the semiconductor element to a thickness of approximately 10 μm. 4. The semiconductor device according to claim 1, wherein the resin layer is deposited all at once by spin coating at the stage of forming a semiconductor wafer on which a plurality of semiconductor elements are collectively formed. . 5. The semiconductor device according to claim 1, wherein the supporting member is a lead frame, and the semiconductor element is in a sealed form embedded in a sealing resin. 6. The support member is a wiring board, and includes pins, grids,
2. The semiconductor device according to claim 1, wherein the semiconductor device has an array type sealing configuration. 7. A first step of forming a resin layer on the entire surface of the final protective film in the semiconductor element and the connection electrode exposed from the final protective film, and depositing it on the connection electrode of the semiconductor element mounted on the support member. a second step of constructing a bonding wire made of a conductor between the connection electrode and the support member by breaking through the resin layer. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the resin layer is made of a silicone resin and is uniformly deposited on the surface of the semiconductor element to a thickness of about 10 μm. . 9. The semiconductor device according to claim 7, wherein the resin layer is deposited all at once by spin coating at the stage of a semiconductor wafer on which a plurality of semiconductor elements are collectively formed. manufacturing method. 10. The method of manufacturing a semiconductor device according to claim 7, wherein the supporting member is a lead frame, and the semiconductor element is in a sealed form embedded in a sealing resin. 11. The method of manufacturing a semiconductor device according to claim 7, wherein the supporting member is a wiring board and has a pin grid array type sealing form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292121A JPH01135052A (en) | 1987-11-20 | 1987-11-20 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62292121A JPH01135052A (en) | 1987-11-20 | 1987-11-20 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01135052A true JPH01135052A (en) | 1989-05-26 |
Family
ID=17777814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62292121A Pending JPH01135052A (en) | 1987-11-20 | 1987-11-20 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01135052A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184720A (en) * | 2000-12-15 | 2002-06-28 | Murata Mfg Co Ltd | Method of manufacturing device |
| WO2007119673A1 (en) * | 2006-04-14 | 2007-10-25 | Sharp Kabushiki Kaisha | Solar cell, solar cell module using the solar cell and method for manufacturing the solar cell module |
| CN108257884A (en) * | 2018-01-24 | 2018-07-06 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
-
1987
- 1987-11-20 JP JP62292121A patent/JPH01135052A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184720A (en) * | 2000-12-15 | 2002-06-28 | Murata Mfg Co Ltd | Method of manufacturing device |
| WO2007119673A1 (en) * | 2006-04-14 | 2007-10-25 | Sharp Kabushiki Kaisha | Solar cell, solar cell module using the solar cell and method for manufacturing the solar cell module |
| CN108257884A (en) * | 2018-01-24 | 2018-07-06 | 德淮半导体有限公司 | Semiconductor devices and forming method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3591839A (en) | Micro-electronic circuit with novel hermetic sealing structure and method of manufacture | |
| US5256598A (en) | Shrink accommodating lead frame | |
| US20020109216A1 (en) | Integrated electronic device and integration method | |
| KR950704838A (en) | TAB TESTING OF AREA ARRAY INTERCONNECTED CHIPS | |
| JP2000269166A (en) | Manufacture of integrated circuit chip and semiconductor device | |
| US5780923A (en) | Modified bus bar with Kapton™ tape or insulative material on LOC packaged part | |
| JPH01135052A (en) | Semiconductor device and manufacture thereof | |
| JPH09172029A (en) | Semiconductor chip, manufacturing method thereof and semiconductor device | |
| EP0902468B1 (en) | Resin-sealed semiconductor device and method of manufacturing the device | |
| JPS6118862B2 (en) | ||
| JP2973988B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0547988A (en) | Semiconductor device | |
| JPH0511660B2 (en) | ||
| JPS6313337A (en) | Process of mounting semiconductor element | |
| KR100209682B1 (en) | Manufacturing method of semiconductor package | |
| JPS6080258A (en) | Manufacture of resin-sealed type semiconductor device | |
| JPH04192421A (en) | Semiconductor device | |
| JPS62147752A (en) | Semiconductor device | |
| JPH0511661B2 (en) | ||
| JPH0493052A (en) | Semiconductor integrated circuit device | |
| KR100214563B1 (en) | Method of fabricating substrate for semiconductor device package and of packaging of semiconductor device | |
| JPH1140704A (en) | Semiconductor device | |
| JP2865224B2 (en) | Resin-sealed semiconductor device | |
| JP2834074B2 (en) | Lead frame and resin-sealed semiconductor device using the same | |
| JPH11162998A (en) | Semiconductor device and its manufacture |