JPH1140704A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1140704A JPH1140704A JP9189455A JP18945597A JPH1140704A JP H1140704 A JPH1140704 A JP H1140704A JP 9189455 A JP9189455 A JP 9189455A JP 18945597 A JP18945597 A JP 18945597A JP H1140704 A JPH1140704 A JP H1140704A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- film
- die pad
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造方法に関し、特に小形・薄型の半導体装置のプ
リント配線板への実装時の信頼性向上に有効な技術であ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effective for improving the reliability of a small and thin semiconductor device when mounted on a printed wiring board.
【０００２】[0002]
【従来の技術】各種電子機器は高機能化あるいは小形化
の傾向にあり、これに搭載する半導体装置は、電子機器
の実装密度を向上させるため、小型・薄型化の傾向にあ
る。これら半導体装置はプリント配線板上に実装される
際、実装密度を向上させるため面実装方式が採用される
のが一般的である。すなわち、プリント配線板上の所定
箇所にはんだペースト等を塗布し、半導体装置の端子が
はんだペースト部に来るように半導体装置を搭載し、エ
アーリフロ炉、赤外線リフロ炉あるいは窒素リフロ炉等
ではんだの溶融温度以上まで加熱し、プリント配線板上
に半導体装置を接続する方法が採られていた。2. Description of the Related Art Various electronic devices tend to have higher functions or smaller sizes, and semiconductor devices mounted on them tend to be smaller and thinner in order to increase the mounting density of the electronic devices. When these semiconductor devices are mounted on a printed wiring board, a surface mounting method is generally adopted in order to increase the mounting density. That is, a solder paste or the like is applied to a predetermined portion of the printed wiring board, and the semiconductor device is mounted so that the terminals of the semiconductor device come to the solder paste portion. A method has been adopted in which a semiconductor device is connected to a printed wiring board by heating it to a temperature or higher.
【０００３】実装前に半導体装置が吸湿しているとこの
実装工程で吸湿した水分が急激に膨張しパッケージクラ
ックを生じさせるという問題が生じる。このような問題
を解決する方法として、例えば特許公開公告 平成２年
第３９８６５号公報記載のように、半導体素子を搭載す
るリードフレームのダイパッドの下側に、ダイパッド部
に薄い樹脂層が残るような開口部を設け、実装時に膨張
した水分が前記薄い樹脂層を破壊して外部に排出される
ことにより、パッケージクラックを防止するという方法
がある。If the semiconductor device absorbs moisture before mounting, there is a problem that the moisture absorbed in this mounting step expands abruptly to cause a package crack. As a method for solving such a problem, for example, as described in Japanese Patent Publication No. 39865/1990, a thin resin layer is left in a die pad portion below a die pad of a lead frame on which a semiconductor element is mounted. There is a method in which an opening is provided, and the moisture expanded during mounting destroys the thin resin layer and is discharged to the outside, thereby preventing a package crack.
【０００４】[0004]
【発明が解決しようとする課題】前記ダイパッド下側に
薄い樹脂層を形成し膨張した水分を排出させる方法は実
装時の吸湿した水分の膨張によるパッケージクラック確
かに有効な手段ではあるが、実際に半導体装置を製造す
る場合、ダイパッドの垂直方向の位置がばらつくため樹
脂層の厚さが異なり、その効果もばらつく。また、膨張
した水分を排出する際に薄い樹脂層が破壊されるが、そ
の際クラックや剥離がダイパッド下面あるいは半導体素
子下面に進展し以後の信頼性を低下させることがある。The method of forming a thin resin layer below the die pad and discharging the expanded water is certainly an effective means for cracking the package due to expansion of the water absorbed during mounting. When manufacturing a semiconductor device, the position of the die pad in the vertical direction varies, so that the thickness of the resin layer differs, and the effect also varies. Further, when the expanded water is discharged, the thin resin layer is destroyed. At this time, cracks and peeling may extend to the lower surface of the die pad or the lower surface of the semiconductor element, which may lower the reliability thereafter.
【０００５】[0005]
【課題を解決するための手段】上記課題を解決する方法
として、樹脂層の破壊等を起こさずに膨張した水分を排
出する方式として、半導体素子とダイパッドの接着に多
孔質の接着シートを用い、その接着シートの一部が半導
体装置の樹脂封止部の外に露出した形態となることによ
り、樹脂層の破壊を伴わずに膨張した水分が排出される
ため、以後の半導体装置の信頼性を確保することが可能
なことを見い出した。As a method for solving the above-mentioned problems, a method of discharging expanded water without destruction of a resin layer or the like, using a porous adhesive sheet for bonding a semiconductor element and a die pad, Since a part of the adhesive sheet is exposed outside the resin sealing portion of the semiconductor device, the expanded water is discharged without destruction of the resin layer, and the reliability of the subsequent semiconductor device is reduced. I found that it was possible to secure it.
【０００６】[0006]
【発明の実施の形態】以下、本発明について、図を参照
して実施の形態とともに詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings and embodiments.
【０００７】なお、実施の形態を説明するための全図に
おいて、同一の機能を有するものは同一符号を付け、そ
の繰り返しの説明は省略する。[0007] In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
【０００８】図５は従来の技術による基板に半導体装置
の断面概略図である。FIG. 5 is a schematic sectional view of a conventional semiconductor device on a substrate.
【０００９】従来方式では、図５（ａ）に示したよう
に、半導体素子はリードフレームのダイパッド上に接着
剤９を介して接着され、半導体素子とリードフレームの
インナーリード６が金線等で接続された後、樹脂で封止
される。実装時に吸湿した水分の膨張は、半導体装置の
中で相対的に接着力の弱い部分、例えば接着層やダイパ
ッドと封止樹脂層界面を剥離させ、図５（ｂ）に示した
ように樹脂層が変形しパッケージクラック１０が発生す
る。In the conventional method, as shown in FIG. 5A, a semiconductor element is bonded on a die pad of a lead frame via an adhesive 9, and the semiconductor element and the inner lead 6 of the lead frame are connected by a gold wire or the like. After connection, it is sealed with resin. The expansion of the moisture absorbed at the time of mounting causes a portion of the semiconductor device having a relatively weak adhesive force, for example, an adhesive layer or an interface between the die pad and the sealing resin layer to be peeled off, and as shown in FIG. Are deformed and a package crack 10 is generated.
【００１０】図１は、本方式の実施の形態を示した図で
ある。本発明では半導体素子１はリードフレームのダイ
パッド上に接着剤を介して接着され、半導体素子とリー
ドフレームのインナーリードが金線４等で接続された
後、樹脂５で封止された構造であるが、ダイパッドと半
導体素子の接着に多孔質の接着フィルム３を用いること
が特徴である。多孔質フィルムは、たとえばふっ素樹脂
繊維、シリコーン樹脂繊維、ポリイミド樹脂繊維を含有
したエポキシ樹脂、フェノール樹脂等の接着フィルム
で、フィルム側面にこれら繊維がつながっているもの、
あるいは、フィルム中に２０μｍ以下の無数の穴があい
ており、相互に連結してフィルム側面につながっている
ものが利用可能である。本方式では、半導体装置実装時
に吸湿した水分が膨張しても、前記のフィルムの外部に
連結した繊維や穴を通って水分が排出されパッケージク
ラックにいたらない。FIG. 1 is a diagram showing an embodiment of the present system. In the present invention, the semiconductor element 1 has a structure in which the semiconductor element 1 is bonded to the die pad of the lead frame via an adhesive, and the semiconductor element and the inner lead of the lead frame are connected with the gold wire 4 or the like and then sealed with the resin 5. However, it is characterized in that a porous adhesive film 3 is used for bonding the die pad and the semiconductor element. The porous film is, for example, an adhesive film such as a fluororesin fiber, a silicone resin fiber, an epoxy resin containing a polyimide resin fiber, and a phenol resin, in which these fibers are connected to the side surface of the film,
Alternatively, a film having an infinite number of holes of 20 μm or less in the film, which are interconnected and connected to the side surface of the film can be used. In this method, even if the moisture absorbed when the semiconductor device is mounted expands, the moisture is discharged through the fibers and holes connected to the outside of the film and the package does not crack.
【００１１】図２は、本方式による多孔質フィルムと半
導体素子、封止樹脂外形の関係を示したものである。本
方式では、半導体装置実装時に膨張した水分が半導体装
置外部へ容易に排出されるように、ワイヤボンディング
等に支障を起こさない範囲で、多孔質フィルムを外部へ
露出させる必要がある。図２では、半導体装置の四隅に
多孔質フィルムを露出させているが、少なくとも一箇所
が樹脂封止部の外に露出していれば、加熱時の水分排出
の効果はある。FIG. 2 shows the relationship between the porous film according to the present method, the semiconductor element, and the outer shape of the sealing resin. In this method, it is necessary to expose the porous film to the outside in a range that does not hinder wire bonding or the like so that the water that has expanded when the semiconductor device is mounted is easily discharged to the outside of the semiconductor device. In FIG. 2, the porous film is exposed at the four corners of the semiconductor device. However, if at least one portion is exposed outside the resin sealing portion, there is an effect of discharging moisture during heating.
【００１２】図３は、本発明の実施の形態を製造するた
めの、製造工程の概略を示したものである。本発明で
は、半導体装置とリードフレームのダイパッドの接着に
多孔質の接着フィルムを使用すること以外は、通常の半
導体装置の製造工程を適用することができる。FIG. 3 schematically shows a manufacturing process for manufacturing an embodiment of the present invention. In the present invention, a normal semiconductor device manufacturing process can be applied, except that a porous adhesive film is used for bonding a semiconductor device and a die frame die pad.
【００１３】図３（ａ）は、リードフレームのダイパッ
ド部分２に多孔質フィルム３を適当な治具を用いて貼り
付ける工程である。FIG. 3A shows a step of attaching the porous film 3 to the die pad portion 2 of the lead frame by using an appropriate jig.
【００１４】その後、図３（ｂ）では、多孔質接着フィ
ルム上に半導体素子１を貼り付ける。その後、必要が有
れば加熱炉等で多孔質接着フィルムを硬化させる。After that, in FIG. 3B, the semiconductor element 1 is attached on the porous adhesive film. Thereafter, if necessary, the porous adhesive film is cured in a heating furnace or the like.
【００１５】図３（ｃ）では、接着後の半導体装置とリ
ードフレームのインナーリード部を金線４等でワイヤボ
ンディング接続を行う。In FIG. 3C, the semiconductor device after bonding and the inner lead portion of the lead frame are connected by wire bonding with a gold wire 4 or the like.
【００１６】その後、図３（ｄ）では、ワイヤボンディ
ング終了後の半導体装置を樹脂５で封止し最終製品の半
導体装置が得られる。Thereafter, in FIG. 3D, the semiconductor device after the completion of the wire bonding is sealed with a resin 5 to obtain a final product semiconductor device.
【００１７】図４は、リードフレームを用いない半導体
装置で、基板７上に半導体素子を多孔質接着フィルムを
用いて接着し、基板上の端子と半導体素子を金線等で接
続し、その後樹脂封止し、はんだバンプ８を設けた実施
の形態を示す図である。図４の方法においても、図１の
場合と同様、吸湿した水分が実装時に膨張しても、多孔
質フィルムを介してその水分が排出されるため、樹脂層
と基板の剥離やパッケージクラックを起こし難くなる。FIG. 4 shows a semiconductor device that does not use a lead frame. A semiconductor element is bonded to a substrate 7 using a porous adhesive film, and the terminals on the substrate are connected to the semiconductor element with a gold wire or the like. FIG. 4 is a view showing an embodiment in which sealing and solder bumps 8 are provided. In the method of FIG. 4 as well, as in the case of FIG. 1, even if the absorbed moisture expands at the time of mounting, the moisture is discharged through the porous film, which causes peeling of the resin layer from the substrate and cracking of the package. It becomes difficult.
【００１８】以上、本発明について実施の形態を用いて
具体的に説明したが、本発明は前記実施の形態に限定さ
れるものではなく、その要旨を逸脱しない範囲で種々変
更可能である。Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.
【００１９】[0019]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば下
記の通りである。The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
【００２０】半導体素子はリードフレームのダイパッド
上に接着剤を介して接着され、半導体素子とリードフレ
ームのインナーリードが金線等で接続された後、樹脂で
封止される方式において、半導体素子とダイパッドの接
着に多孔質の接着シートを用い、その接着シートの一部
が半導体装置の樹脂封止部の外に露出した形態となるこ
とにより、樹脂層の破壊を伴わずに膨張した水分が排出
されるため、以後の半導体装置の信頼性を確保すること
が可能となる。The semiconductor element is bonded to the die pad of the lead frame via an adhesive, and the semiconductor element and the inner lead of the lead frame are connected by a gold wire or the like and then sealed with a resin. A porous adhesive sheet is used for bonding the die pad, and a part of the adhesive sheet is exposed outside the resin sealing portion of the semiconductor device, so that the expanded water is discharged without destruction of the resin layer. Therefore, it is possible to ensure the reliability of the semiconductor device thereafter.
【図１】本発明の実施の形態を示す断面概略図である。FIG. 1 is a schematic sectional view showing an embodiment of the present invention.
【図２】本発明の実施の形態である図１の多孔質接着フ
ィルクを示した図である。FIG. 2 is a diagram showing the porous adhesive film of FIG. 1 according to an embodiment of the present invention.
【図３】本発明の半導体装置の製造工程を説明した図で
ある。FIG. 3 is a diagram illustrating a manufacturing process of the semiconductor device of the present invention.
【図４】本発明の他の実施の形態を示す断面概略図であ
る。FIG. 4 is a schematic sectional view showing another embodiment of the present invention.
【図５】従来技術による半導体装置の断面概略図であ
る。FIG. 5 is a schematic sectional view of a conventional semiconductor device.
１…半導体素子、 ２…ダイパッド、 ３…
接着フィルム、４…金線、 ５…樹脂、
６…インナーリード、７…基板、
８…はんだバンプ、 ９…接着剤、10…パッケー
ジクラック。1 ... semiconductor element, 2 ... die pad, 3 ...
Adhesive film, 4 ... gold wire, 5 ... resin,
6 ... Inner lead, 7 ... Substrate,
8 solder bumps 9 adhesives 10 package cracks.
Claims (3)
用いて半導体素子を接着し、半導体素子とリードフレー
ムのインナーリードを金線等を用いて接続した後、樹脂
によって封止される樹脂封止型半導体装置において、接
着剤が多孔質の接着剤で、少なくともその一部が樹脂封
止型半導体装置の露出していることを特徴とする半導体
装置。A semiconductor device is bonded to a die pad of a lead frame using an adhesive, and the semiconductor device is connected to an inner lead of the lead frame using a gold wire or the like, and then sealed with a resin. A semiconductor device, wherein the adhesive is a porous adhesive, at least a part of which is exposed from the resin-sealed semiconductor device.
し、半導体素子と基板上の端子を金線等を用いて接続し
た後、樹脂によって封止される半導体装置において、接
着剤が多孔質の接着剤で、少なくともその一部が樹脂封
止型半導体装置の露出していることを特徴とする半導体
装置。2. A semiconductor device in which a semiconductor element is bonded to a substrate via an adhesive, and the semiconductor element is connected to a terminal on the substrate using a gold wire or the like, and then sealed with a resin. A semiconductor device comprising a porous adhesive, at least a part of which is exposed from a resin-sealed semiconductor device.
とする請求項１および２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein said adhesive is in the form of a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9189455A JPH1140704A (en) | 1997-07-15 | 1997-07-15 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9189455A JPH1140704A (en) | 1997-07-15 | 1997-07-15 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1140704A true JPH1140704A (en) | 1999-02-12 |
Family
ID=16241554
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9189455A Pending JPH1140704A (en) | 1997-07-15 | 1997-07-15 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH1140704A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006103918A1 (en) * | 2005-03-28 | 2006-10-05 | Matsushita Electric Industrial Co., Ltd. | Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus |
| JP2016225373A (en) * | 2015-05-27 | 2016-12-28 | 日立化成株式会社 | Semiconductor device and adhesive sheet |
-
1997
- 1997-07-15 JP JP9189455A patent/JPH1140704A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006103918A1 (en) * | 2005-03-28 | 2006-10-05 | Matsushita Electric Industrial Co., Ltd. | Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus |
| US7732920B2 (en) | 2005-03-28 | 2010-06-08 | Panasonic Corporation | Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus |
| US8071425B2 (en) | 2005-03-28 | 2011-12-06 | Panasonic Corporation | Flip chip mounting body, flip chip mounting method and flip chip mounting apparatus |
| JP2016225373A (en) * | 2015-05-27 | 2016-12-28 | 日立化成株式会社 | Semiconductor device and adhesive sheet |
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