JPH0729927A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH0729927A JPH0729927A JP5167238A JP16723893A JPH0729927A JP H0729927 A JPH0729927 A JP H0729927A JP 5167238 A JP5167238 A JP 5167238A JP 16723893 A JP16723893 A JP 16723893A JP H0729927 A JPH0729927 A JP H0729927A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- base material
- leads
- integrated circuit
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置の
製造方法に関し、特に薄型の半導体集積回路装置の製造
方法について有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to an effective technique for a method for manufacturing a thin semiconductor integrated circuit device.
【０００２】[0002]
【従来の技術】今日においては、半導体集積回路装置は
高密度化、小型化とともに薄型化が一層要求されてい
る。2. Description of the Related Art Today, semiconductor integrated circuit devices are required to have higher densities, smaller sizes, and thinner thicknesses.
【０００３】このような状況下において、従来は、たと
えば図６に示すＴＱＦＰ（ＴｈｉｎＱｕａｄ Ｆｌａｔ
Ｐａｃｋａｇｅ）やＴＳＯＰ（Ｔｈｉｎ Ｓｍａｌｌ
Ｏｕｔｌｉｎｅ Ｐａｃｋａｇｅ）に見られるように、
厚さの薄いタブ１８と半導体チップ１４とを用い、パッ
ケージの肉厚を約１ミリ程度と薄くし、一方、工法はそ
れまでと同様にして、薄型の半導体集積回路装置を製造
している。Under such circumstances, conventionally, for example, a TQFP (ThinQuad Flat) shown in FIG. 6 is used.
Package) and TSOP (Thin Small)
As seen on the Outline Package)
By using the thin tab 18 and the semiconductor chip 14, the thickness of the package is reduced to about 1 mm, while the method is the same as before to manufacture a thin semiconductor integrated circuit device.
【０００４】また、スマートカード用などの半導体集積
回路装置であるＣＯＢ（ＣｈｉｐＯｎ Ｂｏａｒｄ）で
は、薄型化を図るために、前記のように薄い半導体チッ
プ２４を使用することなどに加えて、図７に示すよう
に、基板２８に凹状部２８ａを形成して半導体チップ２
４を搭載している。Further, in a COB (Chip On Board) which is a semiconductor integrated circuit device for a smart card or the like, in addition to using the thin semiconductor chip 24 as described above in order to reduce the thickness, FIG. As shown in FIG.
It is equipped with 4.
【０００５】[0005]
【発明が解決しようとする課題】しかし、このような従
来の方法では、半導体チップを搭載する場所であるタブ
あるいは基板が必須であり、その分だけ半導体集積回路
装置の厚みが厚くなっていた。However, in such a conventional method, a tab or a substrate on which a semiconductor chip is mounted is indispensable, and the thickness of the semiconductor integrated circuit device is correspondingly increased.
【０００６】確かに、タブや基板など半導体チップ搭載
部の厚さを薄くするアプローチはなされてはいるもの
の、薄肉化には一定の限界が存する。Certainly, although an approach to reduce the thickness of a semiconductor chip mounting portion such as a tab or a substrate has been taken, there is a certain limit to thinning.
【０００７】そこで、本発明の目的は、半導体チップ搭
載部を不要とし、より薄型の半導体集積回路装置を製造
できる技術を提供することにある。Therefore, an object of the present invention is to provide a technique capable of manufacturing a thinner semiconductor integrated circuit device without requiring a semiconductor chip mounting portion.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を説明すれば、次の通
りである。The typical ones of the inventions disclosed in the present application will be outlined below.
【００１０】すなわち、本発明の半導体集積回路装置の
製造方法は、リードが貼着された基材の上面に半導体チ
ップを接着し、この半導体チップとリードとを電気的に
接続した後、基材より上部を封止樹脂によって封止し、
封止後に基材を加熱手段によって加熱して剥離するもの
である。That is, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a semiconductor chip is adhered to the upper surface of a base material to which a lead is attached, the semiconductor chip and the lead are electrically connected, and then the base material. The upper part is sealed with a sealing resin,
After sealing, the base material is heated by a heating means to be peeled off.
【００１１】また、リードが貼着された基材の上面に半
導体チップを接着し、半導体チップとリードとを電気的
に接続した後に、基材より上部を封止樹脂によって封止
し、リードおよび半導体チップと基材との粘着力を、リ
ードおよび半導体チップと封止樹脂との粘着力よりも弱
くすることによって、封止後に前記基材を剥離するもの
である。Further, after bonding the semiconductor chip to the upper surface of the base material to which the leads are attached and electrically connecting the semiconductor chip and the leads, the upper part of the base material is sealed with a sealing resin, and the lead and By making the adhesive force between the semiconductor chip and the base material weaker than the adhesive force between the leads and the semiconductor chip and the sealing resin, the base material is peeled off after the sealing.
【００１２】そして、リードが貼着され、透明なポリイ
ミドからなる基材の上面に半導体チップを接着し、この
半導体チップとリードとを電気的に接続した後、基材よ
り上部を封止樹脂によって封止し、封止後に基材に紫外
線を照射して剥離するものである。Then, the semiconductor chip is adhered to the upper surface of the transparent polyimide base material to which the leads are attached, the semiconductor chip and the leads are electrically connected, and the upper part of the base material is sealed with a sealing resin. After sealing, the base material is peeled off by irradiating it with ultraviolet rays after sealing.
【００１３】[0013]
【作用】上記のような半導体集積回路装置の製造方法に
よれば、半導体チップが接着された基材をモールド後に
剥離することによって、半導体チップを搭載する場所で
あるタブや基板が不要となり、それだけ半導体集積回路
装置の厚さを薄くすることが可能になる。According to the method of manufacturing a semiconductor integrated circuit device as described above, by removing the base material to which the semiconductor chip is adhered after the molding, the tab or the substrate, which is a place for mounting the semiconductor chip, becomes unnecessary. It is possible to reduce the thickness of the semiconductor integrated circuit device.
【００１４】[0014]
【実施例】以下、本発明の実施例を、図面に基づいてさ
らに詳細に説明する。Embodiments of the present invention will now be described in more detail with reference to the drawings.
【００１５】図１〜図５は、本発明の一実施例である半
導体集積回路装置の製造工程を示す説明図である。1 to 5 are explanatory views showing a manufacturing process of a semiconductor integrated circuit device which is an embodiment of the present invention.
【００１６】本実施例における半導体集積回路装置の製
造方法は、次に示すものである。The method of manufacturing the semiconductor integrated circuit device according to this embodiment is as follows.
【００１７】まず、図１に示すように、リード１が貼着
されたテープ（基材）２の上面に、図２に示すように、
たとえば銀エポキシ系のダイボンディングペースト剤
（接着部材）３によって半導体チップ４を接着し、この
半導体チップ４とリード１とをボンディングワイヤ５で
電気的に接続する。First, as shown in FIG. 1, on the upper surface of the tape (base material) 2 to which the leads 1 are attached, as shown in FIG.
For example, a semiconductor chip 4 is adhered by a silver epoxy type die bonding paste agent (adhesive member) 3, and the semiconductor chip 4 and the lead 1 are electrically connected by a bonding wire 5.
【００１８】次に、図３に示すように、テープ２より上
部をエポキシレジン（封止樹脂）６によってモールド封
止する。Next, as shown in FIG. 3, the upper portion of the tape 2 is mold-sealed with an epoxy resin (sealing resin) 6.
【００１９】そして、図４に示すように、テープ２をヒ
ータ（加熱手段）７で加熱することによってリード１お
よび半導体チップ４界面との接着力を低下させて剥離す
る。Then, as shown in FIG. 4, the tape 2 is heated by a heater (heating means) 7 to reduce the adhesive force with the interface between the lead 1 and the semiconductor chip 4 and peel it off.
【００２０】最後に、図５に示すように、半田実装を良
好にするためにリード１下面にメッキ処理を施して、必
要ならばダムバー（図示せず）をカットし、リード１を
所定の形状に成形して、製品としての半導体集積回路装
置が完成する。Finally, as shown in FIG. 5, the lower surface of the lead 1 is plated to improve solder mounting, and a dam bar (not shown) is cut if necessary to form the lead 1 into a predetermined shape. Then, the semiconductor integrated circuit device as a product is completed.
【００２１】本実施例に示すような半導体集積回路装置
の製造方法によれば、半導体チップ４が接着されたテー
プ２をモールド後に剥離することによって、半導体チッ
プを搭載する場所であるタブが不要となるので、それだ
け半導体集積回路装置の厚さを薄くすることが可能にな
る。According to the method for manufacturing a semiconductor integrated circuit device as shown in this embodiment, the tape 2 to which the semiconductor chip 4 is adhered is peeled off after molding, thereby eliminating the need for a tab for mounting the semiconductor chip. Therefore, the thickness of the semiconductor integrated circuit device can be reduced accordingly.
【００２２】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることは言うまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.
【００２３】たとえば、前記実施例においては、接着部
材３としてダイボンディングペースト剤を用い、これに
よって半導体チップ４をテープ２の上面に接着したが、
この接着部材３はダイボンディングペースト剤以外にも
種々のものを用いることが可能である。For example, in the above-described embodiment, the die bonding paste agent is used as the adhesive member 3, and the semiconductor chip 4 is adhered to the upper surface of the tape 2 by this,
As the adhesive member 3, various materials other than the die bonding paste agent can be used.
【００２４】また、前記実施例においては、ヒータ７で
テープ２を加熱することによってリード１および半導体
チップ４界面との接着力を低下させてテープ２を剥離し
ているが、それ以外にも、たとえば、リード１および半
導体チップ４とテープ２との接着力を、リード１および
半導体チップ４と封止樹脂６との接着力よりも弱くする
ことによって剥離する方法や、テープ２を透明なポリイ
ミドからなるものとし、これに紫外線を照射して接着力
を弱めることによって剥離する方法などが考えられる。Further, in the above embodiment, the tape 2 is peeled off by heating the tape 2 by the heater 7 to reduce the adhesive force with the interface between the lead 1 and the semiconductor chip 4, but other than that. For example, a method of peeling the tape 1 by making the adhesive force between the lead 1 and the semiconductor chip 4 and the tape 2 weaker than the adhesive force between the lead 1 and the semiconductor chip 4 and the sealing resin 6, or the tape 2 from transparent polyimide It is conceivable that a method of irradiating this with ultraviolet rays to weaken the adhesive force and peeling it off can be considered.
【００２５】さらに、前記実施例では、半導体チップ４
の封止をエポキシレジンを封止樹脂６としてトランスフ
ァーモールドにより行っているが、ポッティング剤を封
止樹脂６として用いることによってＣＯＢに適用するこ
とも可能である。Further, in the above embodiment, the semiconductor chip 4 is used.
Although the epoxy resin is used as the sealing resin 6 to perform the sealing by transfer molding, the potting agent may be used as the sealing resin 6 to be applied to the COB.
【００２６】なお、半田実装を良好にするためのリード
１下面のメッキ処理工程は省略することができ、ダムバ
ーとしてテープを用いた場合にはダムバーのカットも省
略することができる。The plating process on the lower surface of the lead 1 for improving the solder mounting can be omitted, and the cutting of the dam bar can be omitted when a tape is used as the dam bar.
【００２７】[0027]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば下
記の通りである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００２８】(1).すなわち、本発明の半導体集積回路装
置の製造方法によれば、リードが貼着された基材の上面
に半導体チップを接着し、この半導体チップとリードと
を電気的に接続した後に基材より上部を封止樹脂によっ
て封止し、封止後に基材を剥離することによって、タブ
や基板などの半導体チップ搭載部が不要となる。(1) That is, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, a semiconductor chip is adhered to the upper surface of the base material to which the lead is attached, and the semiconductor chip and the lead are electrically connected. By sealing the upper part of the base material with a sealing resin after connection and peeling the base material after sealing, a semiconductor chip mounting portion such as a tab or a substrate becomes unnecessary.
【００２９】(2).したがって、半導体集積回路装置の厚
さが上部の封止樹脂部と半導体チップの厚さとなり、従
来の半導体集積回路装置に比較して、下部の封止樹脂部
と半導体チップ搭載部の厚さがなくなり、その分だけ半
導体集積回路装置の薄型化を図ることができる。(2) Therefore, the thickness of the semiconductor integrated circuit device becomes the thickness of the upper sealing resin portion and the semiconductor chip, which is lower than that of the conventional semiconductor integrated circuit device. Since the thickness of the chip mounting portion is reduced, the semiconductor integrated circuit device can be thinned accordingly.
【００３０】(3).さらに、本発明の半導体集積回路装置
によれば、下部の封止樹脂部と半導体チップ搭載部とを
省略することができるので、前記のような薄型化と同時
に、半導体集積回路装置の軽量化も図ることができる。(3) Further, according to the semiconductor integrated circuit device of the present invention, the lower encapsulating resin portion and the semiconductor chip mounting portion can be omitted. It is also possible to reduce the weight of the integrated circuit device.
【図１】本発明の実施例による半導体集積回路装置の製
造工程を示す説明図である。FIG. 1 is an explanatory view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.
【図２】本発明の実施例による半導体集積回路装置の製
造工程を示す説明図である。FIG. 2 is an explanatory view showing a manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention.
【図３】本発明の実施例による半導体集積回路装置の製
造工程を示す説明図である。FIG. 3 is an explanatory diagram showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.
【図４】本発明の実施例による半導体集積回路装置の製
造工程を示す説明図である。FIG. 4 is an explanatory view showing a manufacturing process of the semiconductor integrated circuit device according to the embodiment of the present invention.
【図５】本発明の実施例による半導体集積回路装置の製
造工程を示す説明図である。FIG. 5 is an explanatory diagram showing the manufacturing process of the semiconductor integrated circuit device according to the embodiment of the invention.
【図６】従来の半導体集積回路装置を示す断面図であ
る。FIG. 6 is a sectional view showing a conventional semiconductor integrated circuit device.
【図７】従来の半導体集積回路装置を示す断面図であ
る。FIG. 7 is a cross-sectional view showing a conventional semiconductor integrated circuit device.
１ リード ２ テープ（基材） ３ ダイボンディングペースト剤（接着部材） ４ 半導体チップ ５ ボンディングワイヤ ６ エポキシレジン（封止樹脂） ７ ヒータ（加熱手段） １４ 半導体チップ １８ タブ ２４ 半導体チップ ２８ 基板 ２８ａ 凹状部 DESCRIPTION OF SYMBOLS 1 lead 2 tape (base material) 3 die bonding paste agent (adhesive member) 4 semiconductor chip 5 bonding wire 6 epoxy resin (sealing resin) 7 heater (heating means) 14 semiconductor chip 18 tab 24 semiconductor chip 28 substrate 28a concave portion
Claims (3)
チップを接着し、前記半導体チップと前記リードとを電
気的に接続した後、前記基材より上部を封止樹脂によっ
て封止し、封止後に前記基材を加熱手段によって加熱し
て剥離することを特徴とする半導体集積回路装置の製造
方法。1. A semiconductor chip is adhered to the upper surface of a base material to which leads are attached, the semiconductor chip and the leads are electrically connected, and the upper part of the base material is sealed with a sealing resin. A method for manufacturing a semiconductor integrated circuit device, characterized in that the base material is heated and peeled off by a heating means after sealing.
チップを接着し、前記半導体チップと前記リードとを電
気的に接続した後、前記基材より上部を封止樹脂によっ
て封止し、前記リードおよび前記半導体チップと前記基
材との粘着力を、前記リードおよび前記半導体チップと
前記封止樹脂との粘着力よりも弱くすることによって、
封止後に前記基材を剥離することを特徴とする半導体集
積回路装置の製造方法。2. A semiconductor chip is adhered to the upper surface of a base material to which leads are attached, the semiconductor chip and the leads are electrically connected, and then the upper part of the base material is sealed with a sealing resin. , By making the adhesive force between the lead and the semiconductor chip and the base material weaker than the adhesive force between the lead and the semiconductor chip and the sealing resin,
A method of manufacturing a semiconductor integrated circuit device, characterized in that the base material is peeled off after sealing.
らなる基材の上面に半導体チップを接着し、前記半導体
チップと前記リードとを電気的に接続した後、前記基材
より上部を封止樹脂によって封止し、封止後に前記基材
に紫外線を照射して剥離することを特徴とする半導体集
積回路装置の製造方法。3. A lead is attached, a semiconductor chip is adhered to the upper surface of a base material made of transparent polyimide, the semiconductor chip and the lead are electrically connected, and then the upper part of the base material is sealed. A method of manufacturing a semiconductor integrated circuit device, comprising encapsulating with a resin, and irradiating the substrate with ultraviolet rays after the encapsulation to separate the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5167238A JPH0729927A (en) | 1993-07-07 | 1993-07-07 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5167238A JPH0729927A (en) | 1993-07-07 | 1993-07-07 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0729927A true JPH0729927A (en) | 1995-01-31 |
Family
ID=15846026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5167238A Pending JPH0729927A (en) | 1993-07-07 | 1993-07-07 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0729927A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11274194A (en) * | 1998-03-25 | 1999-10-08 | Matsushita Electron Corp | Manufacture of resin encapsulated semiconductor device and apparatus for feeding encapsulating tape |
| EP0977251A1 (en) * | 1997-02-10 | 2000-02-02 | Matsushita Electronics Corporation | Resin sealed semiconductor device and method for manufacturing the same |
| WO2000025359A1 (en) * | 1998-10-27 | 2000-05-04 | Mci Computer Gmbh | Method for manufacturing an ic component |
| US6333212B1 (en) | 1995-08-25 | 2001-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| US6426091B1 (en) | 1997-09-30 | 2002-07-30 | Nikken Chemicals Co., Ltd. | Sustained-release theophylline tablet |
| JP2003017644A (en) * | 2001-06-28 | 2003-01-17 | Matsushita Electric Ind Co Ltd | Method of fabricating resin-sealed semiconductor device |
| KR100414479B1 (en) * | 2000-08-09 | 2004-01-07 | 주식회사 코스타트반도체 | Implantable circuit tapes for implanted semiconductor package and method for manufacturing thereof |
| KR100595094B1 (en) * | 1999-12-27 | 2006-07-03 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device and method for the fabrication there of |
| US7134198B2 (en) | 2000-03-17 | 2006-11-14 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electric element built-in module with sealed electric element |
| JP4703842B2 (en) * | 2000-11-30 | 2011-06-15 | 日東電工株式会社 | Weir material and manufacturing method of sealed electronic component using the weir material |
-
1993
- 1993-07-07 JP JP5167238A patent/JPH0729927A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6333212B1 (en) | 1995-08-25 | 2001-12-25 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
| EP0977251A1 (en) * | 1997-02-10 | 2000-02-02 | Matsushita Electronics Corporation | Resin sealed semiconductor device and method for manufacturing the same |
| EP0977251A4 (en) * | 1997-02-10 | 2005-09-28 | Matsushita Electric Ind Co Ltd | Resin sealed semiconductor device and method for manufacturing the same |
| US6426091B1 (en) | 1997-09-30 | 2002-07-30 | Nikken Chemicals Co., Ltd. | Sustained-release theophylline tablet |
| JPH11274194A (en) * | 1998-03-25 | 1999-10-08 | Matsushita Electron Corp | Manufacture of resin encapsulated semiconductor device and apparatus for feeding encapsulating tape |
| WO2000025359A1 (en) * | 1998-10-27 | 2000-05-04 | Mci Computer Gmbh | Method for manufacturing an ic component |
| KR100595094B1 (en) * | 1999-12-27 | 2006-07-03 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device and method for the fabrication there of |
| US7134198B2 (en) | 2000-03-17 | 2006-11-14 | Matsushita Electric Industrial Co., Ltd. | Method for manufacturing electric element built-in module with sealed electric element |
| KR100414479B1 (en) * | 2000-08-09 | 2004-01-07 | 주식회사 코스타트반도체 | Implantable circuit tapes for implanted semiconductor package and method for manufacturing thereof |
| JP4703842B2 (en) * | 2000-11-30 | 2011-06-15 | 日東電工株式会社 | Weir material and manufacturing method of sealed electronic component using the weir material |
| JP2003017644A (en) * | 2001-06-28 | 2003-01-17 | Matsushita Electric Ind Co Ltd | Method of fabricating resin-sealed semiconductor device |
| JP4590788B2 (en) * | 2001-06-28 | 2010-12-01 | パナソニック株式会社 | Manufacturing method of resin-encapsulated semiconductor device |
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