JPS6151933A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6151933A JPS6151933A JP17332284A JP17332284A JPS6151933A JP S6151933 A JPS6151933 A JP S6151933A JP 17332284 A JP17332284 A JP 17332284A JP 17332284 A JP17332284 A JP 17332284A JP S6151933 A JPS6151933 A JP S6151933A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- resin
- tape
- lead frame
- dam
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000011347 resin Substances 0.000 claims abstract description 38
- 229920005989 resin Polymers 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims abstract description 5
- 238000007789 sealing Methods 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 8
- 238000001721 transfer moulding Methods 0.000 abstract description 6
- 239000000126 substance Substances 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 3
- 239000000725 suspension Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は樹脂封止型半導体装置の製法に関し、特に、レ
ジンモールド後にレジンパリの切断やダム切断工程を要
しないで、樹脂封止型半導体装置を得ろことを可能とす
る技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a method for manufacturing a resin-sealed semiconductor device, and in particular, to a method for producing a resin-sealed semiconductor device without requiring a process of cutting a resin pad or cutting a dam after resin molding. Regarding the technology that makes it possible.
樹脂封止型半導体装置は、一般に多連のリードフレーム
に半導体素子（半導体チップ）を搭載（マウント）シ、
ワイヤボンディングにより半導体チップと外部リード端
子とを電気的に接続した後に、モールド金型に入れてエ
ポキシ樹脂などの合成樹脂でトランスファーモールドし
、個別に切断分離する工程を含んで製造される。Resin-encapsulated semiconductor devices generally have semiconductor elements (semiconductor chips) mounted on multiple lead frames.
After the semiconductor chip and external lead terminals are electrically connected by wire bonding, the semiconductor chip is placed in a mold, transfer-molded with a synthetic resin such as epoxy resin, and manufactured by cutting and separating the chips individually.
トランスファーモールドによりレジンモールドする際に
レジンの流れを止めるために、金属製ダム（タイバー）
が設けられているのでレジンバリができる。このパリは
、不要なものであり、樹脂封止体が形成された点線から
外部に引出された外部リードを折曲げする際に障害とな
るので、除去する必要がある。A metal dam (tie bar) is used to stop the flow of resin when performing resin molding using transfer molding.
is provided, so resin burrs can be created. This dot is unnecessary and must be removed because it becomes an obstacle when bending the external lead drawn out from the dotted line where the resin sealing body is formed.
しかるに、このパリ取りにより、樹脂封止体の一部が欠
けるという現象が生じ、この微小なレジン欠け（マイク
ロクランク）により、バ、７ケージの信頼性試験の一つ
である温度サイクル試験後に、樹脂封止体にクランクを
生じろ原因となり、半導体装置の信頼性を欠如すること
が本発明者により明らか【された。However, this deburring process caused a phenomenon in which a part of the resin molding body was chipped, and due to this minute resin chipping (microcrank), after the temperature cycle test, which is one of the reliability tests for the 7-cage, The inventors have found that this causes cranking in the resin molded body, resulting in a lack of reliability of the semiconductor device.
又、上記ダムの各リード間を接続しているタイバーは、
パリと同様に切断除去する必裂がある。In addition, the tie bar connecting each lead of the dam above is
As with Paris, it is necessary to cut and remove it.
このタイバーの切断時、リードにストレス（応力）が加
わり、これによりリードとレジンとの界面にストレスを
与え、リードとレジンとの接着界面の剥離を引き起こし
、その間隙から水が侵入し易くなり、耐湿性劣化を起こ
す原因となる。樹脂封止の半導体装置の耐湿性不良はか
かるモールド後のリードの切断及び成形工程で生じるリ
ード／レジン界面の隙間によって発生することが多いこ
とが本発明者により明らかにされた。When the tie bar is cut, stress is applied to the lead, which applies stress to the interface between the lead and resin, causing separation of the adhesive interface between the lead and resin, making it easier for water to enter through the gap. This may cause deterioration of moisture resistance. The present inventors have revealed that poor moisture resistance of resin-sealed semiconductor devices is often caused by gaps at the lead/resin interface that occur during the lead cutting and molding process after molding.
なお、トランスファーモールド法において、パリのない
半導体装置を得ようとした技術が、たとえば、特開昭５
１−４７３６９号公報に示されている。In addition, in the transfer molding method, a technique for obtaining a semiconductor device without Paris was developed, for example, in Japanese Patent Application Laid-open No. 5
1-47369.
〔発明の目的〕
本発明の目的は、レジンバリ除去工程およびダムを提供
することにある。[Object of the Invention] An object of the present invention is to provide a resin burr removal process and a dam.
本発明の前記ならびｒそのほかの目的と新規な特徴は１
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention are 1.
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
即ち、本発明では従来のダムを有するリードフレームに
おいて、当該ダムに代えてテープにより各リードを接続
固定するようにしたもので、具体的には、例えば、ダム
を有しないリードフレームのリードに樹脂テープを貼付
しておき、このリードフレームをモールド金型に接着し
、上下の金型間で圧締して、テープを各リードの間隙に
充填し、各リードを接続固定した後洗、レジンをトラン
スファーモールドするようにし、その際特に、テープを
レジンバリが生ずる第１図斜線７で示す位置に貼付、充
填するよ５にすれば、レジンバリが生ぜずかつ、各リー
ド間に充填したテープは従来の金属製ダムのごとくプレ
ス等による切断工程は不要で、各リード間隙に単に埋込
まれているだけなので、簡単に除去できる。That is, in the present invention, in a conventional lead frame having a dam, each lead is connected and fixed with tape instead of the dam. Specifically, for example, resin is attached to the leads of a lead frame without a dam. Tape is pasted, this lead frame is adhered to the mold, and the upper and lower molds are pressed together, the tape is filled into the gap between each lead, each lead is connected and fixed, and then washed and resin is applied. If transfer molding is performed, in particular, if the tape is pasted and filled in the position shown by diagonal lines 7 in Figure 1 where resin burrs occur, as shown in step 5, resin burrs will not occur and the tape filled between each lead will be the same as the conventional one. Unlike metal dams, there is no need for a cutting process using a press or the like, and since the dams are simply embedded in the gaps between the leads, they can be easily removed.
次に、本発明の実施例を第１図〜第５図により説明する
。Next, embodiments of the present invention will be described with reference to FIGS. 1 to 5.
第１１図は本発明を適用したリードフレームの平面図で
あり、本発明では第３図に示すように、リード４に対し
横方向に適宜幅のテープ１１を貼付する。第１図にて、
１はタブで、このタブ１に半導体チップ（図示せず）が
搭載される。２は、このタブ１を支持しているタブ吊り
リードで、このタブ吊りリード２は外枠部３に連結され
ている。FIG. 11 is a plan view of a lead frame to which the present invention is applied. In the present invention, as shown in FIG. 3, a tape 11 of an appropriate width is pasted to the leads 4 in the lateral direction. In Figure 1,
1 is a tab, and a semiconductor chip (not shown) is mounted on this tab 1. Reference numeral 2 denotes a tab suspension lead that supports this tab 1, and this tab suspension lead 2 is connected to an outer frame portion 3.
４は、タブ１の周辺部に複数適宜間隔をおいて配列され
た金属製リードで、第１図では二方向に配列されたデュ
アルインライン（ＤＩＬ）タイプのリードを例示してお
り、半導体チップの周辺部に多数配列された電極とこの
リード４の先端ボンディングポスト部とがボンディング
ワイヤ例えばＡｕ線等を用いて周知の超音波ボンディン
グ法等によりワイヤボンディングされ、電気的接続がと
られる。Reference numeral 4 denotes a plurality of metal leads arranged at appropriate intervals around the periphery of the tab 1. FIG. A large number of electrodes arranged around the periphery and the bonding post at the tip of the lead 4 are wire-bonded using a bonding wire such as an Au wire by a well-known ultrasonic bonding method or the like to establish an electrical connection.
前述のごと（、かかる電気的接続後に、第１図点線５で
囲まれた部分にレジンをモールドして、半導体素子やボ
ンディングワイヤやそのボンディング部やリードの一部
を樹脂封止する。第１図に示すリードフレームは、例え
ば、通常のリードフレームからダムを除いたものにテー
プ１１を貼付することにより得ることができる。As described above (after such electrical connection, resin is molded in the area surrounded by the dotted line 5 in FIG. The lead frame shown in the figure can be obtained, for example, by attaching tape 11 to a normal lead frame with the dam removed.
又、第１図に示すリードフレームは多連のＩＪ ＋＋ド
フレームであり、タブ１２、タブ吊りリード１３、リー
ド１４（インナーリード１５、アウターリード１６）で
−ブロックを構成したリードフレームが外枠部１７を介
して多数連結されている。The lead frame shown in FIG. 1 is a multiple IJ++ dome frame, and the lead frame, in which the tab 12, tab hanging lead 13, and lead 14 (inner lead 15, outer lead 16) constitute a block, serves as the outer frame. A large number of them are connected via portions 17.
第２図はり−ド４上にテープ１１が貼付されている状態
を示す側面図である。FIG. 2 is a side view showing a state in which the tape 11 is pasted on the beam board 4.
次に、第３図及び第４図により、上記テープ１１をリー
ド間に充填し、各リードを接続固定した後に、レジンを
トランスファーモールドする工程を説明する。Next, referring to FIGS. 3 and 4, a process of filling the tape 11 between the leads, connecting and fixing each lead, and then transfer molding a resin will be described.
第３図に示すように、タブ１上に半導体チップ１６をマ
ウントし、このチップ１６とインナーリード１５とをボ
ンディングワイヤ１８によりワイヤボンディング後、モ
ールド金型内にリードフレームを装着する。そして上金
型１９、下金型２０により、リード１４を圧締すると、
第４図に示すように、各リード１４０間隙に、テープ１
１が充填され、各リード１４を接続固定する。次に、金
型の空間２２にレジンを周知のトランスファーモールド
法によりモールドする。As shown in FIG. 3, a semiconductor chip 16 is mounted on the tab 1, and the chip 16 and the inner leads 15 are wire-bonded using bonding wires 18, and then a lead frame is mounted in a mold. Then, when the lead 14 is pressed by the upper mold 19 and the lower mold 20,
As shown in FIG. 4, tape 1 is placed between each lead 140.
1 is filled, and each lead 14 is connected and fixed. Next, resin is molded into the mold space 22 by a well-known transfer molding method.
第５図は本発明製法により得られた樹脂封止型半導体装
置の一例を示す断面図で、第７図にて、２３は例えばエ
ポキシ樹脂により構成された樹脂封止体を示す。FIG. 5 is a sectional view showing an example of a resin-sealed semiconductor device obtained by the manufacturing method of the present invention. In FIG. 7, 23 indicates a resin-sealed body made of, for example, epoxy resin.
本発明に使用されるテープは、例えば合成樹脂により構
成される。樹脂製テープの好ましい例としては耐熱性の
あるボＩＪイミド系樹脂製テープが挙げられる。The tape used in the present invention is made of, for example, synthetic resin. A preferable example of the resin tape is a heat-resistant IJ imide resin tape.
このテープは、ベレット付の際の温度条件や例えば２０
０℃前後に加熱された金型にクランクされろ際の温度条
件などに耐え得ろものであることが好ましく、耐熱性を
備えていることが好ましい、又テープはリードよりも厚
味が同程度ないし厚いものが好ましい。This tape can be used depending on the temperature conditions when attaching the beret, for example 20
It is preferable that the tape can withstand the temperature conditions such as being cranked into a mold heated to around 0°C, and it is preferable that the tape has heat resistance, and the tape is not as thick as the lead. Thick ones are preferred.
本発明でいうテープには、フィルム等のテープ状物も含
む。The tape referred to in the present invention also includes tape-like materials such as films.
（１）従来のダムに代えてテープを使用するようにした
ので、従来のダム切断工程を不要とし、ダム切断に伴な
うストレスの問題も回避でき、耐湿性の向上した信頼度
の高い樹脂封止型半導体装着を提供することができた。(1) Since tape is used instead of a conventional dam, the conventional dam cutting process is not required, stress problems associated with dam cutting can be avoided, and highly reliable resin with improved moisture resistance is used. We were able to provide sealed semiconductor mounting.
（２）使用するテープの位置や幅を自由に変更すること
ができる。例えば、テープを従来のダムの位置よりも内
側にし、レジンバリ発生部に第３図に示すように、テー
ピングし、各リード間隙にテープを充填しておくことに
より、レジンバリを発生しないようにしてお（ことがで
きる。同様にテープの幅を広くしてもよい。これにより
、レジンバリも生ぜず、かつ、ダム切断工程も要しない
。従ってレジンバリが生じないので、従来のどと（、レ
ジンバリ除去によるパッケージクランクを生じｔ
ない・
（３） ポリイミド樹脂からなるテープをレジンとリ
ードとの間に挿入して両者を一体にモールドしているの
で、耐湿性を向上できる。すなわち、リードとポリイミ
ド、ポリイミドとレジンの接着性が良いのでこれらの剥
れはなく、これらの界面からの水分の侵入はない。また
リードの折り曲げ成形時のレジンとリードとの間の応力
をポリイミドが吸収スるのでレジンにクラット等が入る
ことがない。(2) The position and width of the tape used can be changed freely. For example, by placing the tape inside the conventional dam position, taping the area where resin burrs occur as shown in Figure 3, and filling each lead gap with tape, resin burrs can be prevented from occurring. Similarly, the width of the tape may be widened. This does not generate resin burrs and does not require a dam cutting process. Therefore, since resin burrs do not occur, it is possible to causing a crank
(3) A tape made of polyimide resin is inserted between the resin and the lead and both are molded together, improving moisture resistance. That is, since the lead and polyimide and the polyimide and resin have good adhesion, there is no peeling of these, and there is no intrusion of moisture from these interfaces. Furthermore, since the polyimide absorbs the stress between the resin and the lead when the lead is bent and formed, no cracks or the like enter the resin.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定されろ
ものではなく、その要旨を逸脱しない範囲で踵々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on examples, it is to be understood that the present invention is not limited to the above-mentioned examples, and can be modified without departing from the gist thereof. Not even.
たとえば、モールド後、各リード間に充填されたテープ
１１を除去することもできる。For example, after molding, the tape 11 filled between the leads can be removed.
〔利用分野１
本発明はフラットパックタイプのパッケージ等信の樹脂
封止型半導体装置にも適用することができる。[Field of Application 1 The present invention can also be applied to resin-sealed semiconductor devices such as flat pack type packages.
第１図は本発明実施例を示す平面図、
第２図は本発明実施例を示す要部側面図、第３図は本発
明において金型にリードフレームをクランプする様子の
説明図、
第４図はクランプ後裔リードが接続固定された様子を説
明する側断面図、
第５図は本発明に孫る半導体装置の一例を示す断面図で
ある、
１・・・タブ、２・・・タブ吊りリード、３・・・外枠
部、４・・・金属製リード、５・・・モールド部分、６
・・・金属製ダム（タイバー）、７・・・レジンバリ、
８・・・樹脂封止体、９・・・クランク、１０・・・ダ
ム、１１・・・テープ、１２・・・タブ、１３・・・タ
ブ吊りリード、１４・・・リード、１５・・・インナー
リード、１６・・・アクタ−リード、１７・・・外枠部
、１８・・・ボンディングワイヤ、１９・・・上金型、
２０・・・下金型、２１・・・テープ、２２・・・金型
の空間、２３・・・樹脂封止体。
第 １ 図
第 ２ 図
２０ ｚ／
第 ４ 図
第 ５ 図Fig. 1 is a plan view showing an embodiment of the present invention, Fig. 2 is a side view of essential parts showing an embodiment of the invention, Fig. 3 is an explanatory diagram of how a lead frame is clamped to a mold in the present invention, and Fig. 4 The figure is a side cross-sectional view illustrating how the clamp descendant lead is connected and fixed, and FIG. 5 is a cross-sectional view showing an example of a semiconductor device derived from the present invention. 1...Tab, 2...Tab suspension Lead, 3...Outer frame part, 4...Metal lead, 5...Mold part, 6
...Metal dam (tie bar), 7...Resin burr,
8... Resin sealing body, 9... Crank, 10... Dam, 11... Tape, 12... Tab, 13... Tab hanging lead, 14... Lead, 15... - Inner lead, 16... Actor lead, 17... Outer frame portion, 18... Bonding wire, 19... Upper mold,
20... Lower mold, 21... Tape, 22... Mold space, 23... Resin sealing body. Figure 1 Figure 2 Figure 20 z/ Figure 4 Figure 5
Claims (1)
を行った後に、樹脂封止を行う工程を含む樹脂封止型半
導体装置の製法において、ダムを有しないリードフレー
ムの各リード間隙にテープ又はテープ状物を充填して各
リードを接続固定した後に、樹脂封止を行うことを特徴
とする樹脂封止型半導体装置の製法。 ２、上記リードフレームはテープ又はテープ状物により
各リードを接続固定して成るダムを有しないリードフレ
ームであることを特徴とする特許請求の範囲第１項記載
の樹脂封止型半導体装置の製法。[Claims] 1. In a method for manufacturing a resin-sealed semiconductor device, which includes a step of mounting a semiconductor element on a lead frame and performing electrical connection, the resin-sealed semiconductor device is manufactured using a lead frame that does not have a dam. A method for manufacturing a resin-sealed semiconductor device, characterized in that resin sealing is performed after each lead gap is filled with tape or a tape-like material to connect and fix each lead. 2. The method for manufacturing a resin-sealed semiconductor device according to claim 1, wherein the lead frame is a dam-free lead frame in which each lead is connected and fixed by a tape or a tape-like material. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17332284A JPS6151933A (en) | 1984-08-22 | 1984-08-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17332284A JPS6151933A (en) | 1984-08-22 | 1984-08-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6151933A true JPS6151933A (en) | 1986-03-14 |
Family
ID=15958281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17332284A Pending JPS6151933A (en) | 1984-08-22 | 1984-08-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151933A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63258051A (en) * | 1987-04-15 | 1988-10-25 | Fuji Plant Kogyo Kk | Leadframe with pin holding structure and pin holding method of leadframe |
| JPS63283054A (en) * | 1987-03-11 | 1988-11-18 | Fuji Plant Kogyo Kk | Lead frame with pin-holding structure and holding method for pin of lead frame |
| JPS6472549A (en) * | 1987-09-11 | 1989-03-17 | Sony Corp | Lead frame |
| JPS6481260A (en) * | 1987-09-22 | 1989-03-27 | Fuji Plant Kogyo Kk | Manufacture of lead frame having pin-retention structure |
| JPH01105564A (en) * | 1987-10-19 | 1989-04-24 | Toppan Printing Co Ltd | Lead frame |
| JPH01241852A (en) * | 1988-03-24 | 1989-09-26 | Mitsubishi Electric Corp | Lead frame |
| JPH0275747U (en) * | 1988-11-29 | 1990-06-11 | ||
| JPH03108746A (en) * | 1989-05-25 | 1991-05-08 | Toowa Kk | Film carrier and molding using it |
| US5258331A (en) * | 1989-10-20 | 1993-11-02 | Texas Instruments Incorporated | Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars |
| JPH05347376A (en) * | 1991-12-03 | 1993-12-27 | Nec Corp | Lead frame for resin-sealed semiconductor device and manufacture of resin-sealed semiconductor device |
| EP0657922A1 (en) * | 1993-12-10 | 1995-06-14 | Hitachi, Ltd. | A packaged semiconductor device and method of its manufacture |
| JPH07193178A (en) * | 1993-11-30 | 1995-07-28 | Anam Ind Co Ltd | Method and equipment for molding package of integrated circuit |
| FR2741191A1 (en) * | 1995-11-14 | 1997-05-16 | Sgs Thomson Microelectronics | PROCESS FOR MANUFACTURING A MICROMODULE, PARTICULARLY FOR CHIP CARDS |
-
1984
- 1984-08-22 JP JP17332284A patent/JPS6151933A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0464468B2 (en) * | 1987-03-11 | 1992-10-15 | Fuji Plant Kogyo Kk | |
| JPS63283054A (en) * | 1987-03-11 | 1988-11-18 | Fuji Plant Kogyo Kk | Lead frame with pin-holding structure and holding method for pin of lead frame |
| JPS63258051A (en) * | 1987-04-15 | 1988-10-25 | Fuji Plant Kogyo Kk | Leadframe with pin holding structure and pin holding method of leadframe |
| JPS6472549A (en) * | 1987-09-11 | 1989-03-17 | Sony Corp | Lead frame |
| JPS6481260A (en) * | 1987-09-22 | 1989-03-27 | Fuji Plant Kogyo Kk | Manufacture of lead frame having pin-retention structure |
| JPH01105564A (en) * | 1987-10-19 | 1989-04-24 | Toppan Printing Co Ltd | Lead frame |
| JPH01241852A (en) * | 1988-03-24 | 1989-09-26 | Mitsubishi Electric Corp | Lead frame |
| JPH0275747U (en) * | 1988-11-29 | 1990-06-11 | ||
| JPH03108746A (en) * | 1989-05-25 | 1991-05-08 | Toowa Kk | Film carrier and molding using it |
| US5258331A (en) * | 1989-10-20 | 1993-11-02 | Texas Instruments Incorporated | Method of manufacturing resin-encapsulated semiconductor device package using photoresist or pre-peg lead frame dam bars |
| JPH05347376A (en) * | 1991-12-03 | 1993-12-27 | Nec Corp | Lead frame for resin-sealed semiconductor device and manufacture of resin-sealed semiconductor device |
| JPH07193178A (en) * | 1993-11-30 | 1995-07-28 | Anam Ind Co Ltd | Method and equipment for molding package of integrated circuit |
| EP0657922A1 (en) * | 1993-12-10 | 1995-06-14 | Hitachi, Ltd. | A packaged semiconductor device and method of its manufacture |
| US5885852A (en) * | 1993-12-10 | 1999-03-23 | Hitachi, Ltd. | Packaged semiconductor device having a flange at its side surface and its manufacturing method |
| FR2741191A1 (en) * | 1995-11-14 | 1997-05-16 | Sgs Thomson Microelectronics | PROCESS FOR MANUFACTURING A MICROMODULE, PARTICULARLY FOR CHIP CARDS |
| EP0774779A1 (en) * | 1995-11-14 | 1997-05-21 | STMicroelectronics S.A. | Method of fabricating a micromodule, particularly for chip cards |
| US5898216A (en) * | 1995-11-14 | 1999-04-27 | Sgs-Thomson Microelectronics S.A. | Micromodule with protection barriers and a method for manufacturing the same |
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