JPH0455341B2 - - Google Patents

Info

Publication number
JPH0455341B2
JPH0455341B2 JP60221832A JP22183285A JPH0455341B2 JP H0455341 B2 JPH0455341 B2 JP H0455341B2 JP 60221832 A JP60221832 A JP 60221832A JP 22183285 A JP22183285 A JP 22183285A JP H0455341 B2 JPH0455341 B2 JP H0455341B2
Authority
JP
Japan
Prior art keywords
lead
tab
wire
bonding
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60221832A
Other languages
Japanese (ja)
Other versions
JPS6281738A (en
Inventor
Yasuhisa Hagiwara
Masachika Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Microcomputer System Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Microcomputer System Ltd, Hitachi Ltd filed Critical Hitachi Microcomputer System Ltd
Priority to JP60221832A priority Critical patent/JPS6281738A/en
Priority to KR1019860007396A priority patent/KR950000205B1/en
Publication of JPS6281738A publication Critical patent/JPS6281738A/en
Priority to US07/283,842 priority patent/US4951120A/en
Publication of JPH0455341B2 publication Critical patent/JPH0455341B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49177—Combinations of different arrangements
    • H01L2224/49179—Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85043—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a flame torch, e.g. hydrogen torch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/8503—Reshaping, e.g. forming the ball or the wedge of the wire connector
    • H01L2224/85035—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball"
    • H01L2224/85045—Reshaping, e.g. forming the ball or the wedge of the wire connector by heating means, e.g. "free-air-ball" using a corona discharge, e.g. electronic flame off [EFO]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ［技術分野］ 本発明はリードフレーム、特に半導体装置の製
造工程におけるワイヤボンデイングの作業性向上
に適用して有効な技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a technique that is effective when applied to improve the workability of wire bonding in the manufacturing process of lead frames, particularly semiconductor devices.

［背景技術］ ペレツトとインナーリードとの電気的導通を図
る技術のひとつとして、いわゆるワイヤボンデイ
ング法がある。このワイヤボンデイング法では、
たとえばまず金（Au）のような金属からなるワ
イヤの先端部分を加熱して溶融ボールを形成し
て、該ボール部分をペレツトのボンデイングパツ
ド電極に押圧して第一ボンデイングを行う。次に
前記ワイヤがループを描くようにしてボンデイン
グ用キヤピラリをインナーリード上の所定部位に
位置させて、ワイヤをインナーリードに押圧する
ことによつて第二ボンデイングを行う。最後にそ
の余線部分を切断してボンデイングを完了するも
のである。[Background Art] One of the techniques for establishing electrical continuity between pellets and inner leads is the so-called wire bonding method. In this wire bonding method,
For example, first, the tip of a wire made of a metal such as gold (Au) is heated to form a molten ball, and the ball is pressed against a bonding pad electrode of a pellet to perform first bonding. Next, a bonding capillary is positioned at a predetermined position on the inner lead so that the wire forms a loop, and second bonding is performed by pressing the wire against the inner lead. Finally, the extra line portion is cut to complete the bonding.

ところで、フラツトパツケージ型の半導体装置
に用いられるリードフレームのようにインナーリ
ードが多ピン化したものではタブの隅部近傍すな
わちタブ吊りリードに隣設されているインナーリ
ードとパツド電極との距離が大きく離れることと
なるため、これにともないワイヤの張設距離も長
くなる。そのためにワイヤにたるみを生じ易く、
ワイヤと他のインナーリードあるいはタブ吊りリ
ード等との電気的短絡を生じやすいことが本発明
者によつて見い出された。 By the way, in a lead frame used in a flat package type semiconductor device that has many inner leads, the distance between the inner lead near the corner of the tab, that is, adjacent to the tab hanging lead, and the pad electrode is small. Since the wires are separated by a large distance, the length of the wire is also increased. Therefore, the wire tends to become slack,
The inventor has discovered that electrical short circuits between the wire and other inner leads or tab suspension leads are likely to occur.

また、タブ吊りリードに隣設されたインナーリ
ードが、他のインナーリードと同じリード幅およ
び同じリード長しか有していない場合、ワイヤボ
ンデイングの際には前記インナーリード上方から
ワイヤが外れるときが生ずる。このために第二ボ
ンデイングによるワイヤの支えが不十分となり、
これがワイヤのたるみの一因となることも合わせ
て本発明者によつて明らかにされた。 Furthermore, if the inner lead adjacent to the tab suspension lead has the same lead width and lead length as the other inner leads, the wire may come off from above the inner lead during wire bonding. . For this reason, the support of the wire by the second bonding is insufficient,
The inventor has also revealed that this is a cause of wire sagging.

なお、ワイヤボンデイングの技術として詳しく
述べてある例としては、株式会社工業調査会、
1980年１月15日発行「IC化実装技術」（日本マイ
クロエレクトロニクス協会編）、P99〜P103があ
る。 Examples of wire bonding technology that are described in detail include Kogyo Kenkyukai Co., Ltd.
"IC Mounting Technology" (edited by Japan Microelectronics Association), published January 15, 1980, pages 99-103.

［発明の目的］ 本発明の目的は、ワイヤボンデイングに際して
ワイヤのシヨートを防止して信頼性を高めること
ができるリードフレームを提供することにある。[Object of the Invention] An object of the present invention is to provide a lead frame that can prevent wire shorting during wire bonding and improve reliability.

本発明の他の目的は、電気的に信頼性の高い半
導体装置を提供することができる。 Another object of the present invention is to provide a semiconductor device with high electrical reliability.

本発明の前記ならびにその他の目的と新規な特
徴は、本明細書の記述および添付図面から明らか
になるであろう。 The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち代表的なも
のの概要を簡単に説明すれば、次の通りである。[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、タブの隅部から外方に延在するタブ
吊りリードに隣設されたインナーリードの幅が他
のインナーリードよりも大となるように形成され
たリードフレーム構造とすることにより、第二ボ
ンデイングに際してワイヤの支えが充分となるた
め、ボンデイングを確実に行うことができ、ワイ
ヤのシヨートの発生を防止することができる。 That is, by adopting a lead frame structure in which the width of the inner lead adjacent to the tab suspension lead extending outward from the corner of the tab is larger than that of the other inner leads, the second Since the wire is sufficiently supported during bonding, bonding can be performed reliably and the occurrence of wire shoots can be prevented.

また、上記技術により電気的に信頼性の高い半
導体装置を提供することができる。 Further, the above technique can provide a semiconductor device with high electrical reliability.

実施例 １ 第１図は本発明の一実施例であるリードフレー
ムを示す拡大部分平面図、第２図はリードフレー
ムの全体を示す平面図、第３図はこのリードフレ
ームを用いた半導体装置を示す全体断面図、第４
図はボンデイング時のリードフレームおよびその
周辺部分の断面図である。Embodiment 1 FIG. 1 is an enlarged partial plan view showing a lead frame which is an embodiment of the present invention, FIG. 2 is a plan view showing the entire lead frame, and FIG. 3 is a diagram showing a semiconductor device using this lead frame. Overall sectional view shown, No. 4
The figure is a sectional view of the lead frame and its surrounding portion during bonding.

本実施例１のリードフレーム１は、特に制限さ
れないが、第３図に示すような樹脂封止型のフラ
ツトパツケージ、いわゆるFPP型の半導体装置
２１に用いられるリードフレームであり、第２図
に示す形状のものを一単位として、左右両方向に
複数単位を連結した形状からなるものである。 The lead frame 1 of the first embodiment is a lead frame used in a resin-sealed flat package, a so-called FPP type semiconductor device 21 as shown in FIG. 3, although it is not particularly limited. The shape shown is one unit, and a plurality of units are connected in both left and right directions.

リードフレーム１は四角形状の枠部２と、該枠
部２の各辺から中央方向にそれぞれ延設された複
数本のリード３と、その各リードの途中部分を互
いに連結するタイバー４を有している。またリー
ドフレーム１の中央部分には、四角形状のタブ５
が形成されており、このタブ５はその四隅と前記
枠部２の四隅とを各々連結するタブ吊りリード６
によつて支持されている。前記タイバー４に囲ま
れたリード３の部分はインナーリード７を形成し
ており、このインナーリード７の少なくともその
先端部分の表面にはボンデイングを良好に行うた
めに金（Au）等の図示しないめつき層が形成さ
れている。本実施例１に従うと、前記タブ吊りリ
ード６に隣設されるインナーリード７ａは第１図
のように他のインナーリード７よりも幅広に形成
されている。 The lead frame 1 has a rectangular frame portion 2, a plurality of leads 3 extending from each side of the frame portion 2 toward the center, and a tie bar 4 that connects intermediate portions of the leads to each other. ing. In addition, a rectangular tab 5 is located in the center of the lead frame 1.
This tab 5 has tab suspension leads 6 that connect its four corners to the four corners of the frame 2, respectively.
Supported by. The portion of the lead 3 surrounded by the tie bar 4 forms an inner lead 7, and the surface of at least the tip portion of the inner lead 7 is coated with a material (not shown) such as gold (Au) for good bonding. A sticky layer is formed. According to the first embodiment, the inner lead 7a adjacent to the tab suspension lead 6 is formed wider than the other inner leads 7 as shown in FIG.

このようなリードフレーム１は例えば、銅
（Cu）、42アロイ、もしくはコバール等からなる
薄板状の金属板にエツチング処理あるいはプレス
処理等を施して所定形状に加工することによつて
得られるものである。 Such a lead frame 1 is obtained by etching or pressing a thin metal plate made of copper (Cu), 42 alloy, Kovar, etc. into a predetermined shape. be.

このようにして得られたリードフレーム１に
は、まずそのタブ５上にシリコン半導体からなる
ペレツト８が接着材９によつて取付けられる。 First, a pellet 8 made of silicon semiconductor is attached to the tab 5 of the lead frame 1 thus obtained using an adhesive 9.

このようにしてペレツト付けされたリードフレ
ームが、次に図示しないワイヤボンデイング装置
のボンデイングステージ上に載置され、金（Au）
等からなる細線状のワイヤ１０によりペレツト８
のボンデイングパツド電極１１とインナーリード
７との結線すなわちワイヤボンデイングが行われ
る。このワイヤボンデイング工程では、まず前記
ワイヤ１０の一端を加熱溶融することによつてボ
ールが形成される。次に、ワイヤを支持するボン
デイング用キヤピラリ６０が半導体ペレツトのボ
ンデイングパツド１１上に移動され、第４図の矢
印ａのように降下される。これによつて、ボール
１０ａ部分がパツド１０ａに圧着され、第一ボン
デイングが行われる。 The lead frame pelletized in this way is then placed on a bonding stage of a wire bonding machine (not shown), and gold (Au) is attached to the lead frame.
Pellets 8 are formed by a thin wire 10 made of
Connection between the bonding pad electrode 11 and the inner lead 7, that is, wire bonding is performed. In this wire bonding process, first, one end of the wire 10 is heated and melted to form a ball. Next, the bonding capillary 60 supporting the wire is moved onto the bonding pad 11 of the semiconductor pellet and lowered as indicated by arrow a in FIG. As a result, the ball 10a portion is pressed onto the pad 10a, and first bonding is performed.

次に、ワイヤ１０がループを描くようにしてキ
ヤピラリ６０が移動され、第二ボンデイングが行
われる。すなわち、第一ボンデイングの後にキヤ
ピラリ６０が、第４図の矢印ｂに示されたように
上昇され、矢印ｃに示すようにインナーリード７
ａのボンデイングエリアに向けて水平移動され、
次いで矢印ｄに示すように下降される。キヤピラ
リ６０によつて、ワイヤ１０をインナーリード７
ａに熱圧着させる押圧力がワイヤ１０に加えら
れ、その結果、ワイヤボンデイングが行われる。
その後、キヤピラリ６０が第４図の矢印ｅのよう
に上昇される。このとき、キヤピラリ６０側のワ
イヤ１０′は、ワイヤボンデイング装置における
図示しないワイヤクランプ機構が動作され、その
ワイヤクランプ機構によつて引つ張り応力が作用
されることによつて、第４図のように剪断され
る。 Next, the capillary 60 is moved so that the wire 10 draws a loop, and second bonding is performed. That is, after the first bonding, the capillary 60 is raised as shown by arrow b in FIG. 4, and the inner lead 7 is raised as shown by arrow c in FIG.
horizontally moved toward the bonding area of a,
It is then lowered as shown by arrow d. The wire 10 is connected to the inner lead 7 by the capillary 60.
A pressing force is applied to the wire 10 to thermally press the wire 10, thereby performing wire bonding.
Thereafter, the capillary 60 is raised as indicated by arrow e in FIG. At this time, the wire 10' on the side of the capillary 60 is actuated by a wire clamp mechanism (not shown) in the wire bonding device, and a tensile stress is applied by the wire clamp mechanism, as shown in FIG. Sheared to

これによつて、１サイクルのボンデイング工程
が完了される。以上の工程を所定回数分繰り返し
て必要とされる全てのパツド１１とインナーリー
ド７が結線されることになる。 This completes one cycle of the bonding process. By repeating the above steps a predetermined number of times, all the necessary pads 11 and inner leads 7 are connected.

本実施例１によればタブ吊りリード６と隣設さ
れたインナーリード７ａが前述のように他のリー
ド３よりも幅広に形成されている。したがつて、
第二ボンデイングの際に、該インナーリード７ａ
に対してループを描いて着地されるワイヤ１０に
対して十分な接触幅を確保することができる。し
たがつて、タブ吊りリード６に隣設されたインナ
ーリード７ａに結合されるワイヤに生じ易いワイ
ヤ１０の垂れ下がりを効果的に防止することがで
き、ワイヤ１０のシヨートの発生を防止できる。 According to the first embodiment, the inner lead 7a adjacent to the tab suspension lead 6 is formed wider than the other leads 3 as described above. Therefore,
During the second bonding, the inner lead 7a
A sufficient contact width can be secured for the wire 10 that lands in a loop. Therefore, it is possible to effectively prevent the wire 10 from sagging, which tends to occur in the wire connected to the inner lead 7a adjacent to the tab suspension lead 6, and to prevent the wire 10 from sagging.

ワイヤ１０のシヨート防止について、第４図の
断面図および第５図の平面図に基づいて更に詳し
く説明すると、以下のようになる。 Preventing the wire 10 from shooting will be explained in more detail as follows based on the sectional view of FIG. 4 and the plan view of FIG. 5.

すなわち、インナーリード７ａの先端７tpから
インナーリード７ａのボンデイング位置BDPま
での平面部分ｌは、ワイヤ１０のループ形状の不
所望な変形を防止する上で有効な部分となる。本
実施例のようにタブ吊りリード６に隣設するイン
ナーリード７ａの幅が広くされている場合、ワイ
ヤ１０は、半導体ペレツト８のボンデイングされ
るべきパツド１１の位置が多少変更されても、第
５図に実線で示すように、インナーリードの先端
上を通過することになる。この場合は、ワイヤ１
０のボンデイング時のリード側へのループが、部
分ｌよつて良好に制限される。その結果、ワイヤ
１０は第４図に実線によつて示すように、実質的
にリードの平面より上の部分のみに位置すること
となり、不所望なシヨートを生じない。 That is, the plane portion l from the tip 7tp of the inner lead 7a to the bonding position BDP of the inner lead 7a is an effective portion in preventing undesired deformation of the loop shape of the wire 10. When the width of the inner lead 7a adjacent to the tab suspension lead 6 is widened as in this embodiment, the wire 10 can be attached to the pad 11 to which the semiconductor pellet 8 is bonded even if the position of the pad 11 to which the semiconductor pellet 8 is to be bonded is slightly changed. As shown by the solid line in Figure 5, it passes over the tip of the inner lead. In this case, wire 1
The loop to the lead side during bonding of 0 is well restricted by the portion l. As a result, the wire 10 is located substantially only above the plane of the lead, as shown by the solid line in FIG. 4, and undesired shoots do not occur.

これに対して、インナーリード７ａが第５図に
２点鎖線と実線との組み合わせによつて示したよ
うに、狭い幅を持つようにされた場合、そのとき
に設けられるワイヤ１０′は、第５図に破線によ
つて示したように、パツド１１の位置の若干の変
更によつても、インナーリードの先端部上を外れ
て延長されることになる。この場合は、インナー
リードの部分ｌは、ワイヤ１０′のループの望ま
しくない変形を充分防止することができなくなつ
てくる。これに応じて、ワイヤ１０′は、第４図
に２点鎖線によつて示されたように、リードの主
面よりも下方に延長するループを形成する恐れが
生ずる。 On the other hand, when the inner lead 7a is made to have a narrow width as shown by the combination of the two-dot chain line and the solid line in FIG. As shown by the broken line in FIG. 5, even a slight change in the position of the pad 11 causes it to extend beyond the tip of the inner lead. In this case, the inner lead portion l will no longer be able to sufficiently prevent undesired deformation of the loop of wire 10'. Correspondingly, the wire 10' may form a loop extending below the main surface of the lead, as indicated by the two-dot chain line in FIG.

なお、ワイヤボンデイング時に、インナーリー
ドの先端とタブ５の周縁との空間に突起物を配置
することは、ワイヤのループの不所望な変形を防
止する上で、意味がある。第４図において、破線
５０は、ワイヤボンデイング装置におけるワーク
ステーシヨンもしくは、リードフレーム用テーブ
ルとしてのヒートブロツクの示している。この場
合のヒートブロツクは、上述の目的の突起５１を
持つ。タブ吊りリード６から離れたインナーリー
ドとパツドとを結合するワイヤは、インナーリー
ドの幅がたとえ狭くても、そのループ形状が突起
５１によつて良好にされる。この場合、タブ吊り
リード６に隣接するインナーリードとパツドとを
結合するワイヤに対する突起５１の効果は、次の
理由によつて実質的に期待できない。 Note that, during wire bonding, it is meaningful to arrange a protrusion in the space between the tip of the inner lead and the periphery of the tab 5 in order to prevent undesired deformation of the wire loop. In FIG. 4, a broken line 50 indicates a work station in a wire bonding apparatus or a heat block as a lead frame table. The heat block in this case has a protrusion 51 for the above-mentioned purpose. Even if the width of the inner lead is narrow, the wire connecting the inner lead separated from the tab suspension lead 6 and the pad can have a good loop shape by the protrusion 51. In this case, the effect of the protrusion 51 on the wire connecting the inner lead adjacent to the tab suspension lead 6 and the pad cannot be expected to be substantial for the following reason.

すなわち、突起５１に対するタブ吊りリード６
の位置は、たとえばワークステーシヨンに対する
リードフレームの位置合わせ精度によつて影響さ
れることになる。タブ吊りリード６の位置の多少
の変動にかかわらずにタブ吊りリード６が突起５
１にひつかからないようにするために、突起５１
は、それとタブ吊りリード６との間に比較的大き
い空間が生ずるような大きさとされる。その結果
として、タブ吊りリード６に隣接するインナーリ
ード７ａとタブ５との間に突起５１を延長させる
ことが困難となるので、そのリード７ａに結合さ
れるワイヤの形状を突起５１によつて制限するこ
とは困難となる。 That is, the tab suspension lead 6 relative to the protrusion 51
The position of will be affected by, for example, the alignment accuracy of the lead frame relative to the workstation. Regardless of slight variations in the position of the tab suspension lead 6, the tab suspension lead 6 is attached to the protrusion 5.
In order to prevent it from getting hit by 1, the protrusion 51
is sized such that a relatively large space is created between it and the tab suspension lead 6. As a result, it becomes difficult to extend the protrusion 51 between the inner lead 7a adjacent to the tab suspension lead 6 and the tab 5, so the shape of the wire coupled to the lead 7a is limited by the protrusion 51. It becomes difficult to do so.

このようにしてワイヤボンデイングの終了した
リードフレーム１は、トランスフアモールド法に
よりエポキシ樹脂１２でパツケージ成形が行われ
た後、各リード３が独立状態に切断・成形されて
第３図に示すFPP型の半導体装置２１を得るこ
とができる。 The lead frame 1 which has undergone wire bonding in this way is packaged with epoxy resin 12 by the transfer molding method, and then each lead 3 is cut and molded into an independent state to form an FPP type as shown in FIG. A semiconductor device 21 can be obtained.

実施例 ２ 第６図は本発明の他の実施例であるリードフレ
ームを示す拡大部分平面図である。Embodiment 2 FIG. 6 is an enlarged partial plan view showing a lead frame according to another embodiment of the present invention.

本実施例２のリードフレーム４１は実施例１で
説明したリードフレーム１とほぼ同様のものであ
るが、タブ吊りリード６に隣接されたインナーリ
ード４７ａの形状が異なるものである。 The lead frame 41 of the second embodiment is almost the same as the lead frame 1 described in the first embodiment, but the shape of the inner lead 47a adjacent to the tab suspension lead 6 is different.

すなわち、このリードフレーム４１ではタブ吊
りリード６に隣接されたインナーリード４７ａは
他のインナーリード４７よりも軸方向に対して長
めに形成され、そのリード先端はタブ５の直近に
まで延設されている。このため、ワイヤボンデイ
ングの際には、ワイヤ１０の張設距離を短くする
ことができる。したがつて、タブ吊りリード６に
隣接されたインナーリード４７ａに生じやすいワ
イヤ１０の垂れ下がりを防止でき、ワイヤのシヨ
ートを防止して電気的に信頼性の高い半導体装置
を提供することができる。 That is, in this lead frame 41, the inner lead 47a adjacent to the tab suspension lead 6 is formed to be longer in the axial direction than the other inner leads 47, and the tip of the lead extends to the immediate vicinity of the tab 5. There is. Therefore, during wire bonding, the length of the wire 10 can be shortened. Therefore, it is possible to prevent the wire 10 from sagging, which tends to occur on the inner lead 47a adjacent to the tab suspension lead 6, and to prevent the wire from shorting, thereby providing an electrically reliable semiconductor device.

［効果］ (1) タブ吊りリードに隣接されたインナーリード
が他のインナーリードよりもワイヤとのボンデ
イング面積が大となるように形成されたリード
フレーム構造とすることにより、第二ボンデイ
ングに際してワイヤの着地時に十分な滑走距離
を確保することができるため、ボンデイングを
確実に行うことができ、ワイヤのシヨートを防
止することができる。[Effects] (1) By adopting a lead frame structure in which the inner lead adjacent to the tab suspension lead has a larger bonding area with the wire than other inner leads, the wire bonding area is reduced during the second bonding. Since a sufficient sliding distance can be ensured upon landing, bonding can be performed reliably and shorting of the wire can be prevented.

(2) 上記(1)により、電気的に信頼性の高い半導体
装置を提供することができる。(2) According to (1) above, it is possible to provide a semiconductor device with high electrical reliability.

(3) 上記(1)により、インナーリードが微細化した
場合であつても、タブ吊りリードに隣設された
インナーリードでのワイヤの垂れ下がりを防止
できるため、ワイヤボンデイングの信頼性を向
上させて半導体装置の高集積化を促進すること
ができる。(3) With (1) above, even if the inner leads are miniaturized, it is possible to prevent the wire from hanging on the inner leads installed next to the tab suspension leads, improving the reliability of wire bonding. High integration of semiconductor devices can be promoted.

以上本発明者によつてなされた発明を実施例に
基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しな
い範囲で種々変更可能であることはいうまでもな
い。 Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples described above, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

たとえば、タブ吊りリードに隣設されたインナ
ーリードの形状としては、幅あるいは軸方向長さ
を大きくした場合についてのみ説明したが、これ
らの形状に限られず、如何なる形状で面積を大き
くしたものであつてもよい。 For example, the shape of the inner lead adjacent to the tab suspension lead has been explained only when the width or axial length is increased, but the shape is not limited to these shapes, and any shape with increased area can be used. It's okay.

また、実施例ではFPP型の半導体装置に用い
られるリードフレームについてのみ説明したが、
これに限らず外部リードをＪ字状に成形するいわ
ゆるPLCC型の半導体装置に用いられるリードフ
レームであつてもよい。 In addition, in the example, only the lead frame used in the FPP type semiconductor device was explained.
The lead frame is not limited to this, and may be a lead frame used in a so-called PLCC type semiconductor device in which external leads are formed into a J-shape.

さらに、ボンデイング方法についても超音波振
動のみでワイヤの接合を行う、いわゆるウエツジ
ボンデイングであつてもよい。 Furthermore, the bonding method may be so-called wedge bonding, in which wires are bonded only by ultrasonic vibration.

実施例のように、タブ吊りリード６に隣接する
インナーリード７ａの幅を増大させる場合には、
それに応じてインナーリード７ａに対するボンデ
イング可能範囲を広く設定できるようになる。こ
れによつて、半導体ペレツトのボンデイングされ
るべきパツド電極の位置が変更された場合でも、
それに応じてインナーリード７ａのボンデイング
位置を変更することができるようになり、ワイヤ
がインナーリード７ａの先端部上を通過するよう
にすることができる。 When increasing the width of the inner lead 7a adjacent to the tab suspension lead 6 as in the embodiment,
Accordingly, it becomes possible to set a wider bonding range for the inner lead 7a. As a result, even if the position of the pad electrode to which the semiconductor pellet is bonded is changed,
The bonding position of the inner lead 7a can be changed accordingly, and the wire can be made to pass over the tip of the inner lead 7a.

しかしながら、かかるインナーリード７ａは、
たとえば扇形、Ｔ字形の平面パターンのように、
実質的にその先端部のみが幅広にされても良い。
この場合でも、ワイヤループの不所望な形状を無
くすることができる。 However, such inner lead 7a is
For example, fan-shaped, T-shaped plane patterns, etc.
Substantially only the tip portion thereof may be widened.
Even in this case, undesirable shapes of the wire loop can be eliminated.

［利用分野］ 以上の説明では主として本発明者によつてなさ
れた発明をその利用分野である、いわゆる樹脂封
止型の半導体装置に適用した場合について説明し
たが、これに限定されるものではなく、たとえば
低融点ガラス等を封止材として用いた気密封止型
の半導体装置に適用しても有効な技術である。[Field of Application] In the above description, the invention made by the present inventor was mainly applied to the field of application, which is a so-called resin-sealed semiconductor device, but the present invention is not limited to this. This technique is also effective when applied to hermetically sealed semiconductor devices using, for example, low melting point glass as a sealing material.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の実施例１であるリードフレー
ムを示す拡大部分平面図、第２図は実施例１のリ
ードフレームの全体を示す平面図、第３図は実施
例１のリードフレームを用いた半導体装置を示す
全体断面図、第４図はボンデイング時のリードフ
レームおよびその周辺の断面図、第５図はボンデ
イング時のリードフレームの平面図、第６図は本
発明の実施例２であるリードフレームを示す拡大
部分平面図である。 １……リードフレーム、２……枠部、３……リ
ード、４……タイバー、５……タブ、６……タブ
吊りリード、７，７ａ……インナーリード、８…
…ペレツト、９……結合材、１０……ワイヤ、１
０ａ……溶融ボール部、１０ｂ……ワイヤ他端部
分、１１……パツド、１２……エポキシ樹脂、２
１……半導体装置、４１……リードフレーム、４
７，４７ａ……インナーリード。 FIG. 1 is an enlarged partial plan view showing a lead frame according to Example 1 of the present invention, FIG. 2 is a plan view showing the entire lead frame according to Example 1, and FIG. FIG. 4 is a cross-sectional view of the lead frame and its surroundings during bonding, FIG. 5 is a plan view of the lead frame during bonding, and FIG. 6 is a second embodiment of the present invention. FIG. 3 is an enlarged partial plan view showing the lead frame. 1... Lead frame, 2... Frame, 3... Lead, 4... Tie bar, 5... Tab, 6... Tab suspension lead, 7, 7a... Inner lead, 8...
...Pellet, 9...Binding material, 10...Wire, 1
0a... Molten ball part, 10b... Wire other end part, 11... Pad, 12... Epoxy resin, 2
1...Semiconductor device, 41...Lead frame, 4
7,47a...Inner lead.

Claims (1)

【特許請求の範囲】 １ 四角形状のペレツト装着用タブと、前記四角
形状のペレツト装着用タブの周縁部を取り囲むよ
うに、該ペレツト装着用タブの周縁部から離間さ
れて設けられた枠部と、前記四角形状のペレツト
装着用タブの実質的な隅部と前記枠部との間を接
続するタブ吊りリードと、前記枠部からタブの近
傍に延設された複数のインナーリードとを有する
リードフレームであつて、前記タブ吊りリードに
隣設されたインナーリードが他のインナーリード
よりも少なくともその先端の幅が大となるように
形成されていることを特徴とするリードフレー
ム。 ２ 前記タブ吊りリードに隣設されたインナーリ
ードが他のインナーリードよりもさらに前記タブ
に近接する位置まで延設されていることを特徴と
する特許請求の範囲第１項記載のリードフレー
ム。 ３ 四角形状のタブと、該タブの実質的な隅部か
ら外方に延在するタブ吊りリードと、前記タブに
装着された半導体ペレツトと、前記タブの近傍ま
で延設されたインナーリードとを有し、前記半導
体ペレツトにおけるパツド電極と前記タブの近傍
まで延設されたインナーリードとがボンデイング
ワイヤにより電気的に接続された状態で樹脂封止
されてなる半導体装置であつて、前記タブ吊りリ
ードに隣設されたインナーリードが他のインナー
リードよりも少なくともその先端の幅が大となる
ように形成されていることを特徴とする半導体装
置。 ４ 前記タブ吊りリードに隣設されたインナーリ
ードが他のインナーリードよりもさらに前記タブ
に近接する位置まで延設されていることを特徴と
する特許請求の範囲第３項記載の半導体装置。[Scope of Claims] 1. A square pellet mounting tab; and a frame portion provided at a distance from the peripheral edge of the pellet mounting tab so as to surround the peripheral edge of the square pellet mounting tab. , a lead having a tab suspension lead connecting a substantial corner of the square pellet mounting tab and the frame, and a plurality of inner leads extending from the frame to the vicinity of the tab. What is claimed is: 1. A lead frame, characterized in that an inner lead adjacent to the tab suspension lead is formed to have at least a wider width at its tip than other inner leads. 2. The lead frame according to claim 1, wherein the inner lead adjacent to the tab suspension lead extends to a position closer to the tab than other inner leads. 3. A square tab, a tab suspension lead extending outward from a substantial corner of the tab, a semiconductor pellet attached to the tab, and an inner lead extending close to the tab. A semiconductor device comprising a pad electrode in the semiconductor pellet and an inner lead extending close to the tab, which are electrically connected to each other by a bonding wire and sealed with resin, wherein the tab suspension lead A semiconductor device characterized in that an inner lead adjacent to the inner lead is formed so that at least the width of the tip thereof is larger than that of the other inner leads. 4. The semiconductor device according to claim 3, wherein the inner lead adjacent to the tab suspension lead extends to a position closer to the tab than other inner leads.
JP60221832A 1985-10-07 1985-10-07 Lead frame and semiconductor device using said lead frame Granted JPS6281738A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP60221832A JPS6281738A (en) 1985-10-07 1985-10-07 Lead frame and semiconductor device using said lead frame
KR1019860007396A KR950000205B1 (en) 1985-10-07 1986-09-04 Lead frame and semiconductor device using the same
US07/283,842 US4951120A (en) 1985-10-07 1988-12-13 Lead frame and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60221832A JPS6281738A (en) 1985-10-07 1985-10-07 Lead frame and semiconductor device using said lead frame

Publications (2)

Publication Number Publication Date
JPS6281738A JPS6281738A (en) 1987-04-15
JPH0455341B2 true JPH0455341B2 (en) 1992-09-03

Family

ID=16772889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60221832A Granted JPS6281738A (en) 1985-10-07 1985-10-07 Lead frame and semiconductor device using said lead frame

Country Status (3)

Country Link
US (1) US4951120A (en)
JP (1) JPS6281738A (en)
KR (1) KR950000205B1 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281738A (en) * 1985-10-07 1987-04-15 Hitachi Micro Comput Eng Ltd Lead frame and semiconductor device using said lead frame
DE69033400T2 (en) * 1990-03-13 2000-05-11 Sumitomo Electric Industries Optical module and method for its production
US5053852A (en) * 1990-07-05 1991-10-01 At&T Bell Laboratories Molded hybrid IC package and lead frame therefore
US5061988A (en) * 1990-07-30 1991-10-29 Mcdonnell Douglas Corporation Integrated circuit chip interconnect
JPH04213867A (en) * 1990-11-27 1992-08-04 Ibiden Co Ltd Electronic component mounting board frame
JPH05218233A (en) * 1992-02-06 1993-08-27 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JP2714335B2 (en) * 1992-12-16 1998-02-16 株式会社東芝 Semiconductor device
US5322207A (en) * 1993-05-03 1994-06-21 Micron Semiconductor Inc. Method and apparatus for wire bonding semiconductor dice to a leadframe
US5350106A (en) 1993-05-07 1994-09-27 Micron Semiconductor, Inc. Semiconductor wire bonding method
JP2542795B2 (en) * 1994-09-22 1996-10-09 九州日本電気株式会社 Resin-sealed semiconductor device
US5781682A (en) * 1996-02-01 1998-07-14 International Business Machines Corporation Low-cost packaging for parallel optical computer link
US5611478A (en) * 1996-03-11 1997-03-18 National Semiconductor Corporation Lead frame clamp for ultrasonic bonding
JP3638750B2 (en) * 1997-03-25 2005-04-13 株式会社ルネサステクノロジ Semiconductor device
JP2000082717A (en) * 1998-09-07 2000-03-21 Shinkawa Ltd Wire bonding method
US6847099B1 (en) * 2003-02-05 2005-01-25 Amkor Technology Inc. Offset etched corner leads for semiconductor package
JP2006210862A (en) * 2004-12-27 2006-08-10 Toshiba Corp Semiconductor lead frame, memory card, and semiconductor device
US7466516B2 (en) * 2005-01-28 2008-12-16 Hitachi Global Storage Technologies Netherlands B.V. Lead configuration for reduced capacitive interference in a magnetic read/write head

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5431470B2 (en) * 1971-12-15 1979-10-06
JPS5521128A (en) * 1978-08-02 1980-02-15 Hitachi Ltd Lead frame used for semiconductor device and its assembling
JPS5648161A (en) * 1979-09-26 1981-05-01 Nec Kyushu Ltd Lead frame for semiconductor device
JPS5674948A (en) * 1979-11-22 1981-06-20 Hitachi Ltd Lead structure of semiconductor device
JPS56116654A (en) * 1980-02-20 1981-09-12 Nec Corp Manufacturing of lead frame for semiconductor device
JPS5758777U (en) * 1980-09-24 1982-04-07
JPS5861654A (en) * 1981-10-09 1983-04-12 Toshiba Corp Semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7018378A (en) * 1970-12-17 1972-06-20
JPS5431470U (en) * 1977-08-05 1979-03-01
JPS58142554A (en) * 1982-02-19 1983-08-24 Hitachi Ltd Lead frame
JPS61269345A (en) * 1985-05-24 1986-11-28 Hitachi Ltd Semiconductor device
JP2559364B2 (en) * 1985-07-12 1996-12-04 株式会社日立製作所 Lead frame for semiconductor device
JPS6281738A (en) * 1985-10-07 1987-04-15 Hitachi Micro Comput Eng Ltd Lead frame and semiconductor device using said lead frame

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5431470B2 (en) * 1971-12-15 1979-10-06
JPS5521128A (en) * 1978-08-02 1980-02-15 Hitachi Ltd Lead frame used for semiconductor device and its assembling
JPS5648161A (en) * 1979-09-26 1981-05-01 Nec Kyushu Ltd Lead frame for semiconductor device
JPS5674948A (en) * 1979-11-22 1981-06-20 Hitachi Ltd Lead structure of semiconductor device
JPS56116654A (en) * 1980-02-20 1981-09-12 Nec Corp Manufacturing of lead frame for semiconductor device
JPS5758777U (en) * 1980-09-24 1982-04-07
JPS5861654A (en) * 1981-10-09 1983-04-12 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
KR870004509A (en) 1987-05-11
KR950000205B1 (en) 1995-01-11
US4951120A (en) 1990-08-21
JPS6281738A (en) 1987-04-15

Similar Documents

Publication Publication Date Title
US6222258B1 (en) Semiconductor device and method for producing a semiconductor device
KR930004246B1 (en) Resin seal type semiconductor device
JP2972096B2 (en) Resin-sealed semiconductor device
JP2001313363A (en) Resin-encapsulated semiconductor device
JPH0455341B2 (en)
JPH08306853A (en) Semiconductor device, manufacture thereof and manufacture of lead frame
JPH0321047A (en) Semiconductor package sealed in capsule
JPS62259450A (en) Assembled unit in which integrated circuit die and lead frame are mutually connected and method of mutual connection
JPH11312706A (en) Resin encapsulating semiconductor device and its manufacture, and lead frame
JPH08111491A (en) Semiconductor device
JP2000188366A (en) Semiconductor device
JPH09312375A (en) Lead frame, semiconductor device and manufacture thereof
JP3150253B2 (en) Semiconductor device, its manufacturing method and mounting method
JP2677632B2 (en) Ultra-thin surface mount resin-sealed semiconductor device
JP3638750B2 (en) Semiconductor device
JPS60167454A (en) Semiconductor device
JP2586835B2 (en) Semiconductor integrated circuit
JP2954110B2 (en) CSP type semiconductor device and manufacturing method thereof
JPH07161876A (en) Semiconductor integrated circuit device and its manufacture, and mold used for its manufacture
JP2569400B2 (en) Method for manufacturing resin-encapsulated semiconductor device
JPH0817870A (en) Semiconductor device
JP3454192B2 (en) Lead frame, resin-sealed semiconductor device using the same, and method of manufacturing the same
JPH0855856A (en) Semiconductor device and its manufacture
JPH0525236Y2 (en)
JP2871575B2 (en) Lead frame, method of manufacturing the same, resin-sealed semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313117

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term