JP2006210862A - Semiconductor lead frame, memory card, and semiconductor device - Google Patents

Semiconductor lead frame, memory card, and semiconductor device Download PDF

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JP2006210862A
JP2006210862A JP2005077451A JP2005077451A JP2006210862A JP 2006210862 A JP2006210862 A JP 2006210862A JP 2005077451 A JP2005077451 A JP 2005077451A JP 2005077451 A JP2005077451 A JP 2005077451A JP 2006210862 A JP2006210862 A JP 2006210862A
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frame
frames
bed frame
suspension pin
lead frame
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Isao Ozawa
澤 勲 小
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Toshiba Corp
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Toshiba Corp
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Priority to JP2005077451A priority Critical patent/JP2006210862A/en
Priority to US11/297,457 priority patent/US20060145329A1/en
Priority to KR1020050129526A priority patent/KR100681994B1/en
Publication of JP2006210862A publication Critical patent/JP2006210862A/en
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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor lead frame with good twisting strength, a memory card, and a semiconductor device. <P>SOLUTION: This memory IC comprises the first and second bed frames 2 and 3 separately placed in X direction to support a chip 11, the first and second hang pin frames 42, 43 placed in Y direction, sandwiching the first bed frame 2 to support the first bed frame 2, the third and fourth hang pin frames placed in Y direction, sandwiching the second bed frame 3 to support the second bed frame 3, the first beam frame 8 for connecting the first and third hang pin frames 4 and 6, the second beam frame 9 for connecting the second and fourth hang pin frames 5 and 7, the inner leads 10 respectively placed outside of the first and second bed frames 2 and 3 and an outer lead 11 connected to the inner leads 10 and placed outside of the package. Owing to this structure, this IC has improved twisting strength and has larger resistance for damage. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、チップを実装するリードフレームの形状に特徴がある半導体用リードフレーム、メモリカードおよび半導体装置に関する。   The present invention relates to a semiconductor lead frame, a memory card, and a semiconductor device that are characterized by the shape of a lead frame on which a chip is mounted.

フラッシュメモリ等を薄型プラスチックパッケージに収納した携帯可能なメモリカードが普及している。この種の薄型プラスチックパッケージは、パッケージの外側に配置されるアウターリードとアウターリードに接続されるインナーリードを備えている。チップのパッドとインナーリードは、ボンディングワイヤにより接続される。チップとインナーリードは、エポキシ系の樹脂により封止される（特許文献１参照）。   Portable memory cards in which a flash memory or the like is housed in a thin plastic package have become widespread. This type of thin plastic package includes an outer lead disposed outside the package and an inner lead connected to the outer lead. The chip pads and the inner leads are connected by bonding wires. The chip and the inner lead are sealed with an epoxy resin (see Patent Document 1).

最近では、PCや携帯電話等の各種電子機器にメモリカードスロットが設けられている。メモリカードの着脱方向は予め決まっているが、メモリカードを着脱する際にユーザが意図せずに着脱方向とは異なる方向にメモリカードをねじる場合がありうる。   Recently, memory card slots are provided in various electronic devices such as PCs and mobile phones. The memory card attachment / detachment direction is determined in advance, but when the memory card is attached / detached, the user may unintentionally twist the memory card in a direction different from the attachment / detachment direction.

大抵のメモリカードは、薄型プラスチップパッケージを採用しているため、ねじり強度があまり強くなく、メモリカードにある一定以上のねじり強度を与えると、メモリカードにひび割れが起きて、内部のチップが壊れるおそれがある。
特許第1994757号公報 Most memory cards use a thin plus chip package, so the torsional strength is not very strong, and if the memory card is given a certain level of torsional strength, the memory card will crack and the internal chip will break There is a fear.
Japanese Patent No. 1994757

本発明は、ねじり強度に優れた半導体用リードフレーム、メモリカードおよび半導体装置を提供するものである。   The present invention provides a lead frame for a semiconductor, a memory card, and a semiconductor device having excellent torsional strength.

本発明の一態様によれば、デュアルピン構造のチップを支持可能なベッドフレームと、前記ベッドフレームから第１方向にそれぞれ伸び、互いに分離された複数の吊りピンフレームと、前記複数の吊りピンフレームから第２方向に伸び、前記チップを挟んで両側で前記複数の吊りピンフレーム同士を接続する少なくとも二本の梁フレームと、を備えることを特徴とする半導体用リードフレームを提供する。   According to one aspect of the present invention, a bed frame capable of supporting a chip having a dual pin structure, a plurality of suspension pin frames extending in a first direction from the bed frame and separated from each other, and the plurality of suspension pin frames And at least two beam frames that extend in the second direction and connect the plurality of suspension pin frames on both sides of the chip. The semiconductor lead frame is provided.

また、本発明の一態様によれば、第１方向に互いに分離して配置されデュアルピン構造のチップを載置する第１および第２のベッドフレームと、前記第１のベッドフレームを挟んで第２方向に配置され前記第１のベッドフレームを支持する第１および第２の吊りピンフレームと、前記第２のベッドフレームを挟んで第２方向に配置され前記第２のベッドフレームを支持する第３および第４の吊りピンフレームと、前記第１および第３の吊りピンフレームを接続する第１の梁フレームと、前記第２および第４の吊りピンフレームを接続する第２の梁フレームと、を備えることを特徴とする半導体用リードフレームを提供する。   In addition, according to one aspect of the present invention, the first and second bed frames that are arranged separately from each other in the first direction and on which the dual-pin structure chip is placed, and the first bed frame are sandwiched between the first and second bed frames. First and second suspension pin frames that are arranged in two directions and support the first bed frame, and first and second suspension pin frames that are arranged in the second direction across the second bed frame and support the second bed frame 3 and 4 suspension pin frames; a first beam frame connecting the first and third suspension pin frames; a second beam frame connecting the second and fourth suspension pin frames; A lead frame for semiconductors is provided.

また、本発明の一態様によれば、チップの底面全体を支持可能で、底面側に複数の凹部が形成されたフラットベッドフレームと、前記フラットベッドフレームに一体に形成され、前記フラットベッドフレームの対向する２辺に沿って外側に伸び、一部に切り欠き部がそれぞれ形成された第１および第２の吊りピンフレームと、を備えることを特徴とすることを特徴とする半導体用リードフレームを提供する。   Further, according to one aspect of the present invention, the flat bed frame capable of supporting the entire bottom surface of the chip and having a plurality of recesses formed on the bottom surface side is formed integrally with the flat bed frame. A semiconductor lead frame comprising: first and second suspension pin frames extending outward along two opposing sides and partially formed with cutout portions. provide.

本発明によれば、吊りピンフレームと一体に形成される梁フレームを設けるため、ねじり強度に優れた半導体用リードフレーム、メモリカードおよび半導体装置を得ることができる。   According to the present invention, since the beam frame formed integrally with the hanging pin frame is provided, it is possible to obtain a semiconductor lead frame, a memory card, and a semiconductor device having excellent torsional strength.

以下、図面を参照しながら、本発明の一実施形態について説明する。   Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

（第１の実施形態）
図１は本発明の第１の実施形態に係る半導体装置のパッケージの透視図であり、リードフレームの構造を示している。図１の半導体装置は、デュアルピン構造のチップ１をエポキシ系樹脂でモールドして形成される。チップ１の具体的な種類は特に問わないが、例えばフラッシュメモリチップ１等が考えられる。以下では、チップ１としてフラッシュメモリを用いたメモリICを例に取って本発明の半導体装置を説明する。なお、図１では、チップ１の実装位置を点線で表している。 (First embodiment)
FIG. 1 is a perspective view of a package of a semiconductor device according to the first embodiment of the present invention, and shows the structure of a lead frame. The semiconductor device of FIG. 1 is formed by molding a chip 1 having a dual pin structure with an epoxy resin. The specific type of the chip 1 is not particularly limited. For example, the flash memory chip 1 can be considered. Hereinafter, the semiconductor device of the present invention will be described by taking a memory IC using a flash memory as an example of the chip 1. In FIG. 1, the mounting position of the chip 1 is indicated by a dotted line.

図１のメモリICは、Ｘ方向に互いに分離して配置されてチップ１を支持する第１および第２のベッドフレーム２，３と、第１のベッドフレーム２を挟んでＹ方向に配置され第１のベッドフレーム２を支持する第１および第２の吊りピンフレーム４，５と、第２のベッドフレーム３を挟んでＹ方向に配置され第２のベッドフレーム３を支持する第３および第４の吊りピンフレーム６，７と、第１および第３の吊りピンフレーム４，６を接続する第１の梁フレーム８と、第２および第４の吊りピンフレーム５，７を接続する第２の梁フレーム９と、第１および第２のベッドフレーム２，３の外側にそれぞれ配置されるインナーリード１０と、インナーリード１０に接続されてパッケージの外側に配置されるアウターリード１１とを備えている。   The memory IC in FIG. 1 is arranged in the Y direction with the first bed frame 2 sandwiched between the first and second bed frames 2 and 3 that are arranged separately from each other in the X direction and support the chip 1. First and second suspension pin frames 4 and 5 that support one bed frame 2, and third and fourth frames that are arranged in the Y direction across the second bed frame 3 and support the second bed frame 3. , The first beam frame 8 connecting the first and third suspension pin frames 4, 6, and the second connecting the second and fourth suspension pin frames 5, 7. A beam frame 9, inner leads 10 disposed on the outer sides of the first and second bed frames 2 and 3, and outer leads 11 connected to the inner leads 10 and disposed on the outer side of the package are provided. .

第１および第２のベッドフレーム２，３は、例えば合金材で形成される。チップ１と第１および第２のベッドフレーム２，３とは、例えばエポキシ系の樹脂からなるマウント材で接合される。インナーリード１０のボンディングワイヤの接続箇所には導電性をよくするために銀メッキが施されている。ボンディングワイヤは、例えば金合金で形成されている。アウターリード１１は、例えば合金材で形成され、その表面には錫鉛もしくは錫銅や錫銀のメッキが施されている。   The first and second bed frames 2 and 3 are made of, for example, an alloy material. The chip 1 and the first and second bed frames 2 and 3 are joined by a mount material made of, for example, an epoxy resin. Silver plating is applied to the connecting portion of the inner lead 10 for bonding wire to improve conductivity. The bonding wire is made of, for example, a gold alloy. The outer lead 11 is formed of, for example, an alloy material, and the surface thereof is plated with tin lead, tin copper, or tin silver.

図２は図１のA-A線断面図、図３は図１のB-B線断面図である。図２に示すように、第１のベッドフレーム２、第１の吊りピンフレーム４および第２の吊りピンフレーム５は同一の導体板で形成されており、第１のベッドフレーム２が第１および第２の吊りピンフレーム４，５よりも低くなるように段差が形成されている。同様に、第２のベッドフレーム３、第３の吊りピンフレーム６および第４の吊りピンフレーム７は同一の導体板で形成されており、第２のベッドフレーム３が第３および第４の吊りピンフレーム６，７よりも低くなるように段差が形成されている。また、図示のように、チップ１はモールド樹脂２２によりモールドされている。第１のベッドフレーム２と第１および第２の吊りピンフレーム４，５との段差（第２のベッドフレーム３と第３および第４の吊りピンフレーム６，７との段差）は、チップ１を第１および第２のベッドフレーム２，３にマウントした状態で、チップ１の上面とエポキシ系樹脂２２の上面との間の距離がチップ１の下面とエポキシ系樹脂２２の下面との間の距離に等しくなるように設定されている。   2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG. As shown in FIG. 2, the first bed frame 2, the first suspension pin frame 4 and the second suspension pin frame 5 are formed of the same conductor plate, and the first bed frame 2 includes the first and second suspension pin frames 4 and 5. A step is formed so as to be lower than the second suspension pin frames 4 and 5. Similarly, the second bed frame 3, the third suspension pin frame 6, and the fourth suspension pin frame 7 are formed of the same conductive plate, and the second bed frame 3 is formed by the third and fourth suspension frames. A step is formed so as to be lower than the pin frames 6 and 7. Further, as shown in the figure, the chip 1 is molded with a mold resin 22. The step between the first bed frame 2 and the first and second suspension pin frames 4, 5 (the step between the second bed frame 3 and the third and fourth suspension pin frames 6, 7) is the chip 1. Is mounted on the first and second bed frames 2 and 3, the distance between the upper surface of the chip 1 and the upper surface of the epoxy resin 22 is between the lower surface of the chip 1 and the lower surface of the epoxy resin 22. It is set to be equal to the distance.

本実施形態は、分割された第１および第２のベッドフレーム２，３にてチップ１を支持し、チップ１の中央付近は図３に示すようにベッドフレームは設けられていない。   In the present embodiment, the chip 1 is supported by the divided first and second bed frames 2 and 3, and no bed frame is provided near the center of the chip 1 as shown in FIG.

図４は本実施形態のメモリIC２０の断面構造を示す図である。図示のように、チップ１とインナーリード１０はボンディングワイヤ２１で接続された後、エポキシ系樹脂２２でモールドされる。   FIG. 4 is a diagram showing a cross-sectional structure of the memory IC 20 of the present embodiment. As shown in the figure, the chip 1 and the inner lead 10 are connected by a bonding wire 21 and then molded with an epoxy resin 22.

エポキシ系樹脂２２でモールドする際、インナーリード１０の上方と下方で樹脂２２の成形速度が異なると、インナーリード１０やベッドフレーム２，３に負荷がかかって、ベッドフレーム２，３の位置が変化したり、インナーリード１０が変形したりする。また、インナーリード１０の上方の樹脂２２と下方の樹脂２２とが物理的に分離されるため、樹脂２２の接合性が弱くなり、剥がれやすくなる。   When molding with the epoxy resin 22, if the molding speed of the resin 22 is different between the upper side and the lower side of the inner lead 10, a load is applied to the inner lead 10 and the bed frames 2 and 3, and the position of the bed frames 2 and 3 changes. Or the inner lead 10 is deformed. Further, since the resin 22 above and the resin 22 below the inner lead 10 are physically separated, the bondability of the resin 22 is weakened and easily peeled off.

そこで、本実施形態では、第１〜第４の吊りピンフレーム４〜７のそれぞれに、図１に示すようなパンチ孔２３を複数設けている。モールド用の樹脂２２は、注入時に、これらパンチ孔２３を介してインナーリード１０の上下方向に均等に広がるため、インナーリード１０の上下で成形速度をほぼ均一化できる。また、インナーリード１０の上方の樹脂２２と下方の樹脂２２がパンチ孔２３を介して直接接合されるため、モールドの強度が増し、剥がれ等の不具合が起きにくくなる。   Therefore, in this embodiment, a plurality of punch holes 23 as shown in FIG. 1 are provided in each of the first to fourth suspension pin frames 4 to 7. Since the molding resin 22 spreads evenly in the vertical direction of the inner lead 10 through the punch holes 23 at the time of injection, the molding speed can be made substantially uniform above and below the inner lead 10. Further, since the resin 22 above the inner lead 10 and the resin 22 below the inner lead 10 are directly joined via the punch holes 23, the strength of the mold increases and problems such as peeling are less likely to occur.

また、本実施形態では、チップ１の上面とエポキシ系樹脂２２の上面との間の距離がチップ１の下面とエポキシ系樹脂２２の下面との間の距離に等しくなるように、ベッドフレーム２，３と吊りピンフレーム４〜７との段差を設定している。このため、チップ１の上方と下方で樹脂２２の成形速度が均等になり、ベッドフレーム２，３の位置変化などを防止することができる。   Further, in the present embodiment, the bed frame 2, the distance between the upper surface of the chip 1 and the upper surface of the epoxy resin 22 is equal to the distance between the lower surface of the chip 1 and the lower surface of the epoxy resin 22. 3 and the suspension pin frames 4 to 7 are set. For this reason, the molding speed of the resin 22 is equalized above and below the chip 1, and the position change of the bed frames 2 and 3 can be prevented.

本発明者は、図１のような第１および第２の梁フレーム８，９を設けた場合と設けない場合について、ねじり強度の測定を行った。この測定では、図５に示すように、メモリIC２０のピンの配設方向とは略90度異なる方向を軸として、ねじりを与えた。その結果、梁フレームを設けた場合のねじり強度は2.71kgfで、設けない場合は2.28kgfになり、20％近くねじり強度が増大することがわかった。   The inventor measured the torsional strength when the first and second beam frames 8 and 9 as shown in FIG. 1 were provided and when they were not provided. In this measurement, as shown in FIG. 5, the twist was given about the direction different from the pin arrangement direction of the memory IC 20 by about 90 degrees. As a result, the torsional strength when the beam frame was provided was 2.71 kgf, and 2.28 kgf when it was not provided, indicating that the torsional strength increased by nearly 20%.

図６はパンチ孔２３をインナーリード１０に複数列にわたって形成した例を示す図である。図示のように、パンチ孔２３を複数列に設けることにより、インナーリード１０の上方の樹脂２２と下方の樹脂２２との密着性がより向上する。なお、パンチ孔２３の数やサイズは、特に制限はなく、吊りピンフレームの材質やサイズ等により決定すればよい。   FIG. 6 is a view showing an example in which punch holes 23 are formed in the inner lead 10 over a plurality of rows. As shown in the figure, by providing the punch holes 23 in a plurality of rows, the adhesion between the resin 22 above the inner lead 10 and the resin 22 below is further improved. The number and size of the punch holes 23 are not particularly limited, and may be determined depending on the material and size of the hanging pin frame.

本実施形態のメモリIC２０は、プリント基板や各種のメモリカード等に実装可能である。図７は本実施形態のメモリIC２０を内蔵したメモリカード３０の外形形状を示す三面図であり、図７（ａ）は上面、図７（ｂ）は下面、図７（ｃ）は側面の外形形状をそれぞれ示している。メモリカード３０の下面には外部端子２５が設けられている。   The memory IC 20 of this embodiment can be mounted on a printed circuit board or various memory cards. FIG. 7 is a three-sided view showing the outer shape of the memory card 30 incorporating the memory IC 20 of this embodiment. FIG. 7 (a) is the upper surface, FIG. 7 (b) is the lower surface, and FIG. Each shape is shown. An external terminal 25 is provided on the lower surface of the memory card 30.

図８はメモリカード３０の実装図、図９は図８のA-A線断面図である。図８に示すように、実装基板３１上に、NAND型フラッシュメモリからなる本実施形態のメモリIC２０と、このメモリIC２０の読み書きを制御するメモリコントローラ３２とを備えている。実装基板３１はカードケース３３により覆われている。   8 is a mounting diagram of the memory card 30, and FIG. 9 is a cross-sectional view taken along line AA of FIG. As shown in FIG. 8, on the mounting substrate 31, the memory IC 20 of the present embodiment formed of a NAND flash memory and a memory controller 32 that controls reading and writing of the memory IC 20 are provided. The mounting substrate 31 is covered with a card case 33.

図８のメモリカード３０の場合、不図示のカードスロットに対して図示の矢印の向きに挿脱を行う。挿脱の際、ユーザは意図せずに挿脱方向を軸としてメモリカード３０をねじる可能性がある。ところが、上述したように、本実施形態のメモリIC２０は梁フレームを有するため、ねじり強度が大きく、ユーザが多少ねじってもメモリIC２０の破壊を防止できる。   In the case of the memory card 30 shown in FIG. 8, the card slot (not shown) is inserted and removed in the direction of the arrow shown. During insertion / removal, the user may unintentionally twist the memory card 30 about the insertion / removal direction. However, as described above, since the memory IC 20 of this embodiment has a beam frame, the torsional strength is large, and even if the user twists a little, the memory IC 20 can be prevented from being broken.

このように、第１の実施形態では、互いに分割された第１および第２のベッドフレーム２，３間をチップ１の両側で梁フレーム８，９により接続するため、メモリIC２０のねじり強度が向上し、メモリICが壊れにくくなる。   As described above, in the first embodiment, the first and second bed frames 2 and 3 divided from each other are connected by the beam frames 8 and 9 on both sides of the chip 1, so that the torsional strength of the memory IC 20 is improved. However, the memory IC is hard to break.

（第２の実施形態）
第１の実施形態では、互いに分割された第１および第２のベッドフレーム２，３にてチップ１を支持する例を説明したが、ベッドフレームは必ずしも分割されていなくてもよい。 (Second Embodiment)
In the first embodiment, the example in which the chip 1 is supported by the first and second bed frames 2 and 3 divided from each other has been described, but the bed frame does not necessarily have to be divided.

図１０は本発明の第２の実施形態に係るメモリIC２０のパッケージの透視図である。図１０のメモリIC２０は、チップ１の下面全体を支持する分割されないベッドフレーム３４と、ベッドフレーム３４の両端部からＹ方向にそれぞれ伸びる四本の吊りピンフレーム３５と、対向配置された２本の吊りピンフレーム３５同士を接続するＸ方向に伸びる二本の梁フレーム３６とを備えている。   FIG. 10 is a perspective view of the package of the memory IC 20 according to the second embodiment of the present invention. The memory IC 20 of FIG. 10 includes an undivided bed frame 34 that supports the entire lower surface of the chip 1, four suspension pin frames 35 that respectively extend in the Y direction from both ends of the bed frame 34, and two opposingly arranged two. And two beam frames 36 extending in the X direction for connecting the suspension pin frames 35 to each other.

吊りピンフレーム３５には、図１と同様のパンチ孔２３が形成されている。ベッドフレーム３４および吊りピンフレーム３５の外側にはインナーリード１０が配置されており、インナーリード１０とチップ１のパッドはボンディングワイヤ２１により接続される。   A punch hole 23 similar to that shown in FIG. 1 is formed in the suspension pin frame 35. Inner leads 10 are arranged outside the bed frame 34 and the suspension pin frame 35, and the inner leads 10 and the pads of the chip 1 are connected by bonding wires 21.

チップ１は、その全面でベッドフレーム３４に接合される。チップ１とベッドフレーム３４との接合には、例えばエポキシ系樹脂２２からなるマウント材が用いられる。   The chip 1 is bonded to the bed frame 34 on the entire surface thereof. For joining the chip 1 and the bed frame 34, for example, a mount material made of an epoxy resin 22 is used.

図１１は図１０のA-A線断面図である。図１１に示すように、ベッドフレーム３４の下面には、凹凸が設けられている。このような凹凸を設けることにより、モールドの際に用いる樹脂２２とベッドフレーム３４との接合性がよくなり、樹脂２２の剥がれ等の不具合が起きにくくなる。   11 is a cross-sectional view taken along line AA in FIG. As shown in FIG. 11, unevenness is provided on the lower surface of the bed frame 34. By providing such irregularities, the bondability between the resin 22 used in molding and the bed frame 34 is improved, and problems such as peeling of the resin 22 are less likely to occur.

このように、第２の実施形態では、チップ１の下面全体をベッドフレーム３４と接合するため、チップ１をベッドフレーム３４により安定に接合させることができる。また、吊りピンフレーム３５により、第１の実施形態と同様にメモリIC２０のねじり強度を増大させることができる。   Thus, in the second embodiment, since the entire lower surface of the chip 1 is bonded to the bed frame 34, the chip 1 can be bonded to the bed frame 34 stably. Further, the torsional strength of the memory IC 20 can be increased by the suspension pin frame 35 as in the first embodiment.

（第３の実施形態）
第３の実施形態は、第２の実施形態の変形例である。チップのサイズがあまり大きくない場合は、第１の実施形態のような分割されたベッドフレーム（以下、分割ベッドフレーム）で問題なくチップを支持できるが、チップのサイズが大きくなると、分割ベッドフレームでは強度が不足し、フレームがたわむ等の不具合が生じるおそれがある。 (Third embodiment)
The third embodiment is a modification of the second embodiment. If the chip size is not so large, the divided bed frame (hereinafter referred to as a divided bed frame) as in the first embodiment can support the chip without any problem. However, if the chip size is increased, Insufficient strength may cause problems such as frame deflection.

このため、チップサイズが大きい場合には、チップの底面全体を支持するフラットベッドフレームを採用するのが望ましい。フラットベッドフレームは、分割ベッドフレームよりもひねり強度も高いため、上述した梁フレームを設けなくても、十分なひねり強度が得られる。   For this reason, when the chip size is large, it is desirable to employ a flat bed frame that supports the entire bottom surface of the chip. Since the flat bed frame has a higher twisting strength than the split bed frame, a sufficient twisting strength can be obtained without providing the beam frame described above.

ところが、フラットベッドフレームは、モールド用の樹脂を注入する際、同フレームの上側と下側とで樹脂の注入速度に差が生じやすく、同フレームが傾いたり、ボンディングワイヤに無理な力がかかって断線する等の不具合が生じるおそれがある。   However, when injecting mold resin, the flatbed frame tends to cause a difference in the resin injection speed between the upper and lower sides of the frame, and the frame tilts or an excessive force is applied to the bonding wire. There is a risk of problems such as disconnection.

また、フラットベッドフレームとモールド用の樹脂とは密着性があまりよくないため、完成したチップを基板に実装する目的でリフロー処理等を行ったときに、パッケージ内で剥離現象が起きるおそれがある。   Further, since the adhesion between the flat bed frame and the resin for molding is not so good, there is a possibility that a peeling phenomenon may occur in the package when a reflow process or the like is performed for the purpose of mounting the completed chip on the substrate.

以下に説明する第３の実施形態は、フラットベッドフレームを使用しながら、これらの不具合が起きないことを特徴とする。図１２は本発明の第３の実施形態に係るメモリIC20のパッケージの透視図である。図１２では、チップ１の実装位置を点線で図示している。図１３は図１２のA-A線断面図である。   The third embodiment described below is characterized in that these problems do not occur while using a flat bed frame. FIG. 12 is a perspective view of the package of the memory IC 20 according to the third embodiment of the present invention. In FIG. 12, the mounting position of the chip 1 is indicated by a dotted line. 13 is a cross-sectional view taken along line AA in FIG.

図１２に示すように、本実施形態は、大サイズのチップ１を実装することを念頭に置いている。図１２のメモリICは、チップ１の底面全体を支持可能なフラットベッドフレーム４１と、フラットベッドフレーム４１の対向する２辺に沿ってその外側に対向配置される第１および第２の吊りピンフレーム４２，４３とを備えている。   As shown in FIG. 12, the present embodiment takes into account that a large-sized chip 1 is mounted. The memory IC of FIG. 12 includes a flat bed frame 41 that can support the entire bottom surface of the chip 1, and first and second suspension pin frames that are disposed opposite to each other along two opposing sides of the flat bed frame 41. 42, 43.

第１および第２の吊りピンフレーム４２，４３は、フラットベッドフレーム４１と同一材料により一体に形成されている。第１および第２の吊りピンフレーム４２，４３とフラットベッドフレーム４１との間には、図１３に示すように段差があり、第１および第２の吊りピンフレーム４２，４３は、フラットベッドフレーム４１よりも高い位置に形成されている。   The first and second suspension pin frames 42 and 43 are integrally formed of the same material as the flat bed frame 41. As shown in FIG. 13, there is a step between the first and second suspension pin frames 42 and 43 and the flat bed frame 41, and the first and second suspension pin frames 42 and 43 are flat bed frames. It is formed at a position higher than 41.

第１および第２の吊りピンフレーム４２，４３にはともに、切り欠き部４４が形成されている。これら切り欠き部４４は、フラットベッドフレーム４１を挟んで互いに対向する位置に形成されている。これら切り欠き部４４は、図１２に矢印で示すように、モールド用の樹脂注入口の位置に合わせて設けられている。   A cutout portion 44 is formed in each of the first and second suspension pin frames 42 and 43. These notches 44 are formed at positions facing each other across the flat bed frame 41. These notches 44 are provided in accordance with the position of the mold resin injection port, as indicated by arrows in FIG.

このような切り欠き部４４を設けることにより、第１および第２の吊りピンフレーム４２，４３が樹脂の注入を妨げるおそれがなくなり、フラットベッドフレーム４１の上下方向に均等に樹脂を注入することができる。   By providing such a notch 44, there is no possibility that the first and second suspension pin frames 42, 43 prevent resin injection, and the resin can be injected evenly in the vertical direction of the flat bed frame 41. it can.

また、片側だけでなく、フラットベッドフレーム４１を挟んで両側に切り欠き部４４を設ける理由は、樹脂の注入方向に沿って、複数のリードフレームを配置して、これらフレームを連続してモールドする場合があるためである。このようなフレームは、多列フレームと呼ばれている。   The reason for providing the notches 44 on both sides of the flat bed frame 41 as well as on one side is to arrange a plurality of lead frames along the resin injection direction and mold these frames continuously. This is because there are cases. Such a frame is called a multi-row frame.

図１４は多列フレーム４０を説明する概略図である。図１４の各フレームは、図１２と同様の構造を持つ。各フレームにチップ１を実装してワイヤボンディングを行った後、図１４の矢印の向きに樹脂を注入し、その後に、個々のチップ１ごとにカッティングを行う。   FIG. 14 is a schematic diagram for explaining the multi-row frame 40. Each frame in FIG. 14 has the same structure as in FIG. After chip 1 is mounted on each frame and wire bonding is performed, resin is injected in the direction of the arrow in FIG. 14, and then cutting is performed for each individual chip 1.

図１４のような多列フレーム４０を用いた場合であっても、本実施形態の吊りピンフレーム４２，４３は、樹脂の注入方向に沿って切り欠き部４４を有するため、吊りピンフレーム４２，４３によって樹脂の流れが変わるような不具合が起きなくなる。   Even when the multi-row frame 40 as shown in FIG. 14 is used, the suspension pin frames 42 and 43 of the present embodiment have the cutout portions 44 along the resin injection direction. The trouble that the flow of resin changes by 43 does not occur.

第１および第２の吊りピンフレーム４２，４３には、第１および第２の実施形態と同様のパンチ孔４５が複数形成されている。これらパンチ孔４５を介して、第１および第２の吊りピンフレーム４２，４３の上下に樹脂が移動できるようになる。   A plurality of punch holes 45 similar to those in the first and second embodiments are formed in the first and second suspension pin frames 42 and 43. The resin can move up and down the first and second suspension pin frames 42 and 43 via the punch holes 45.

図１５および図１６はフラットベッドフレーム４１の裏面側の概略形状を示す平面図である。図示のように、フラットベッドフレーム４１の裏面には、多数の凹部４６が形成されている。これら凹部４６の形状は特に問わない。図１５は円形状の凹部４６を形成した例、図１６は楕円状の凹部４６を形成した例、図１７および図１８は矩形状の凹部４６を形成した例を示している。   15 and 16 are plan views showing a schematic shape of the back surface side of the flat bed frame 41. FIG. As shown in the figure, a large number of recesses 46 are formed on the back surface of the flat bed frame 41. The shape of the recess 46 is not particularly limited. 15 shows an example in which a circular recess 46 is formed, FIG. 16 shows an example in which an elliptical recess 46 is formed, and FIGS. 17 and 18 show an example in which a rectangular recess 46 is formed.

凹部４６を形成する理由は、フラットベッドフレーム４１と樹脂との密着性をよくするためである。樹脂は、個々の凹部４６内に充填されるため、フラットベッドフレーム４１と樹脂との接触面積が増えて、両者の密着性がよくなる。これにより、パッケージングが終わった後にリフロー処理等を行っても、パッケージ内部で剥離が起きにくくなる。   The reason for forming the recess 46 is to improve the adhesion between the flat bed frame 41 and the resin. Since the resin is filled in the individual recesses 46, the contact area between the flat bed frame 41 and the resin is increased, and the adhesion between the two is improved. As a result, even if a reflow process or the like is performed after packaging is completed, peeling is less likely to occur inside the package.

図１６のように細長形状の凹部４６を形成する場合、凹部４６の長手方向を樹脂の注入方向に一致させるのが望ましい。これにより、凹部４６に沿って樹脂が流れやすくなり、フラットベッドフレーム４１の上下での樹脂の成形速度に差が生じなくなる。   When the elongated recess 46 is formed as shown in FIG. 16, it is desirable to match the longitudinal direction of the recess 46 with the resin injection direction. As a result, the resin easily flows along the recess 46, and the difference in resin molding speed between the top and bottom of the flat bed frame 41 does not occur.

なお、凹部４６を細長形状にする場合、その形状は必ずしも楕円でなくてもよい。例えば、図１８のように長方形状の凹部４６を形成してもよい。   In addition, when making the recessed part 46 into an elongate shape, the shape does not necessarily need to be an ellipse. For example, you may form the rectangular recessed part 46 like FIG.

図１９は樹脂の注入が終わった後のパッケージの断面構造の一例を示す図であり、図１２のB-B線断面構造を示している。図示のように、第１の実施形態と同様に、チップ１とインナーリード１０とはボンディングワイヤ２１で接続された状態で樹脂２２の注入が行われる。樹脂は、フラットベッドフレームの上下に均等の厚さで形成されている。   FIG. 19 is a view showing an example of the cross-sectional structure of the package after the resin injection is finished, and shows the cross-sectional structure taken along the line BB of FIG. Like illustration, resin 22 is inject | poured in the state which connected the chip | tip 1 and the inner lead 10 with the bonding wire 21 like 1st Embodiment. The resin is formed with a uniform thickness above and below the flat bed frame.

このように、第３の実施形態では、大サイズのチップ１を全面で支持可能なフラットベッドフレーム４１と、このフラットベッドフレーム４１に一体成形された吊りピンフレーム４２，４３とを備え、樹脂の注入口に合わせて吊りピンフレーム４２，４３に切り欠き部４４を形成するため、吊りピンフレーム４２，４３が樹脂の注入を妨げるおそれがなくなる。また、フラットベッドフレーム４１の裏面に凹部４６を形成するため、フラットベッドフレーム４１と樹脂との密着性がよくなり、フラットベッドフレーム４１の上下で樹脂の成形速度にばらつきが生じなくなり、剥離等の不具合がおきくくなる。また、フラットベッドフレーム４１は、分割ベッドフレームよりもひねり強度が高いため、ひねりによるメモリICの破壊を防止できる。   As described above, the third embodiment includes the flat bed frame 41 capable of supporting the large-sized chip 1 over the entire surface, and the suspension pin frames 42 and 43 formed integrally with the flat bed frame 41, and is made of resin. Since the cutout portion 44 is formed in the suspension pin frames 42 and 43 in accordance with the injection port, there is no possibility that the suspension pin frames 42 and 43 prevent the injection of the resin. In addition, since the concave portion 46 is formed on the back surface of the flat bed frame 41, the adhesion between the flat bed frame 41 and the resin is improved, and the molding speed of the resin does not vary between the upper and lower sides of the flat bed frame 41. The trouble becomes more frequent. Further, since the flat bed frame 41 has higher twisting strength than the split bed frame, it is possible to prevent the memory IC from being damaged by the twisting.

本発明の第１の実施形態に係る半導体装置のパッケージの透視図。1 is a perspective view of a package of a semiconductor device according to a first embodiment of the present invention. 図１のA-A線断面図。FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. 図１のB-B線断面図。FIG. 2 is a sectional view taken along line BB in FIG. 1. 本実施形態のメモリIC２０の断面構造を示す図。The figure which shows the cross-section of memory IC20 of this embodiment. ねじり強度の測定の際にメモリIC２０をねじる方向を示す図。The figure which shows the direction which twists memory IC20 in the case of measurement of torsional strength. パンチ孔４５２３をインナーリード１０の複数列に形成した例を示す図。FIG. 6 is a view showing an example in which punch holes 4523 are formed in a plurality of rows of inner leads 10. 本実施形態のメモリIC２０を内蔵したメモリカード３０の外形形状を示す三面図。FIG. 3 is a three-sided view illustrating an outer shape of a memory card 30 including the memory IC 20 according to the present embodiment. メモリカード３０の実装図。FIG. 図８のA-A線断面図。AA line sectional view of FIG. 本発明の第２の実施形態に係るメモリIC２０のパッケージの透視図。The perspective view of the package of memory IC20 concerning the 2nd Embodiment of this invention. 図１０のA-A線断面図。FIG. 11 is a sectional view taken along line AA in FIG. 10. 本発明の第３の実施形態に係るメモリIC20のパッケージの透視図。The perspective view of the package of memory IC20 concerning the 3rd Embodiment of this invention. 図１２のA-A線断面図。AA line sectional view of FIG. 多列フレーム４０を説明する概略図。Schematic explaining the multi-row frame 40. FIG. フラットベッドフレーム４１の裏面側の概略形状を示す平面図。FIG. 3 is a plan view showing a schematic shape on the back side of the flat bed frame 41. フラットベッドフレーム４１の裏面側の概略形状を示す他の平面図。The other top view which shows the schematic shape of the back surface side of the flat bed frame 41. FIG. フラットベッドフレーム４１の裏面側の概略形状を示す他の平面図。The other top view which shows the schematic shape of the back surface side of the flat bed frame 41. FIG. フラットベッドフレーム４１の裏面側の概略形状を示す他の平面図。The other top view which shows the schematic shape of the back surface side of the flat bed frame 41. FIG. 樹脂の注入が終わった後のパッケージの断面構造の一例を示す図。The figure which shows an example of the cross-sectional structure of the package after injection | pouring of resin is finished.

符号の説明Explanation of symbols

１ チップ１
２ 第１のベッドフレーム
３ 第２のベッドフレーム
４ 第１の吊りピンフレーム
５ 第２の吊りピンフレーム
６ 第３の吊りピンフレーム
７ 第４の吊りピンフレーム
８ 第１の梁フレーム
９ 第２の梁フレーム
１０ インナーリード
１１ アウターリード
２０ メモリIC
２３ パンチ孔４５
３０ メモリカード
４１ フラットベッドフレーム
４２ 第１の吊りピンフレーム
４３ 第２の吊りピンフレーム
４４ 切り欠き部
４５ パンチ孔
４６ 凹部 1 Chip 1
2 1st bed frame 3 2nd bed frame 4 1st suspension pin frame 5 2nd suspension pin frame 6 3rd suspension pin frame 7 4th suspension pin frame 8 1st beam frame 9 2nd Beam frame 10 Inner lead 11 Outer lead 20 Memory IC
23 Punch hole 45
30 Memory Card 41 Flat Bed Frame 42 First Hanging Pin Frame 43 Second Hanging Pin Frame 44 Notch 45 Punch Hole 46 Recess

Claims (10)

デュアルピン構造のチップを支持可能なベッドフレームと、
前記ベッドフレームから第１方向にそれぞれ伸び、互いに分離された複数の吊りピンフレームと、
前記複数の吊りピンフレームから第２方向に伸び、前記チップを挟んで両側で前記複数の吊りピンフレーム同士を接続する少なくとも二本の梁フレームと、を備えることを特徴とする半導体用リードフレーム。 A bed frame capable of supporting a dual pin structure chip;
A plurality of suspension pin frames each extending in a first direction from the bed frame and separated from each other;
A semiconductor lead frame comprising: at least two beam frames extending in a second direction from the plurality of suspension pin frames and connecting the plurality of suspension pin frames on both sides of the chip. 第１方向に互いに分離して配置されデュアルピン構造のチップを載置する第１および第２のベッドフレームと、
前記第１のベッドフレームを挟んで第２方向に配置され前記第１のベッドフレームを支持する第１および第２の吊りピンフレームと、
前記第２のベッドフレームを挟んで第２方向に配置され前記第２のベッドフレームを支持する第３および第４の吊りピンフレームと、
前記第１および第３の吊りピンフレームを接続する第１の梁フレームと、
前記第２および第４の吊りピンフレームを接続する第２の梁フレームと、を備えることを特徴とする半導体用リードフレーム。 A first bed frame and a second bed frame on which chips of a dual pin structure are disposed separately from each other in a first direction;
First and second suspension pin frames arranged in a second direction across the first bed frame and supporting the first bed frame;
Third and fourth suspension pin frames arranged in a second direction across the second bed frame and supporting the second bed frame;
A first beam frame connecting the first and third suspension pin frames;
A semiconductor lead frame comprising: a second beam frame connecting the second and fourth suspension pin frames. 前記第１および第２のベッドフレームと、前記第１および第２の吊りピンフレームと、前記第３および第４の吊りピンフレームと、前記第１および第２の梁フレームとは、同一金属板で形成され、
前記第１のベッドフレームは、前記第１および第２の吊りピンフレームよりも低い位置に形成され、
前記第２のベッドフレームは、前記第３および第４の吊りピンフレームよりも低い位置に形成されることを特徴とする請求項２に記載の半導体用リードフレーム。 The first and second bed frames, the first and second suspension pin frames, the third and fourth suspension pin frames, and the first and second beam frames are the same metal plate. Formed with
The first bed frame is formed at a position lower than the first and second suspension pin frames,
3. The semiconductor lead frame according to claim 2, wherein the second bed frame is formed at a position lower than the third and fourth suspension pin frames. 4. チップの底面全体を支持可能で、底面側に複数の凹部が形成されたフラットベッドフレームと、
前記フラットベッドフレームに一体に形成され、前記フラットベッドフレームの対向する２辺に沿って外側に伸び、一部に切り欠き部がそれぞれ形成された第１および第２の吊りピンフレームと、を備えることを特徴とすることを特徴とする半導体用リードフレーム。 A flat bed frame capable of supporting the entire bottom surface of the chip and having a plurality of recesses formed on the bottom surface side;
A first suspension pin frame formed integrally with the flat bed frame, extending outward along two opposing sides of the flat bed frame, and partially formed with a notch; A semiconductor lead frame characterized by the above. 前記切り欠き部は、モールド用の樹脂注入口付近に形成されることを特徴とする請求項４に記載の半導体用リードフレーム。   5. The semiconductor lead frame according to claim 4, wherein the notch is formed in the vicinity of a resin injection port for molding. 前記切り欠き部は、前記フラットベッドフレームを挟んで両側に対向配置されることを特徴とする請求項４または５に記載の半導体用リードフレーム。   6. The semiconductor lead frame according to claim 4, wherein the notch portions are arranged opposite to each other across the flat bed frame. 前記凹部は細長形状であり、前記凹部の長手方向は、前記切り欠き部の対向配置された方向に一致することを特徴とする請求項６に記載の半導体用リードフレーム。   The semiconductor lead frame according to claim 6, wherein the concave portion has an elongated shape, and a longitudinal direction of the concave portion coincides with a direction in which the notch portion is opposed to the concave portion. 前記第１および第２の吊りピンフレームと前記フラットベッドフレームとは段差状に形成され、前記第１および第２の吊りピンフレームは、前記フラットベッドフレームよりも高い位置に形成されることを特徴とすることを特徴とする請求項４乃至７のいずれかに記載の半導体用リードフレーム。   The first and second suspension pin frames and the flat bed frame are formed in a step shape, and the first and second suspension pin frames are formed at a position higher than the flat bed frame. The lead frame for semiconductor according to claim 4, wherein the lead frame is a semiconductor lead frame. 前記第１および第２の吊りピンフレームには、パンチ孔が形成されることを特徴とする請求項１乃至８のいずれかに記載の半導体用リードフレーム。   9. The semiconductor lead frame according to claim 1, wherein punch holes are formed in the first and second suspension pin frames. 請求項１乃至９のいずれかに記載の半導体用リードフレームを備えることを特徴とする半導体装置。   A semiconductor device comprising the semiconductor lead frame according to claim 1.
JP2005077451A 2004-12-27 2005-03-17 Semiconductor lead frame, memory card, and semiconductor device Pending JP2006210862A (en)

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KR1020050129526A KR100681994B1 (en) 2004-12-27 2005-12-26 Lead frame for semiconductor, memory card and semiconductor device

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