JPH02239651A - Semiconductor device and mounting method thereof - Google Patents
Semiconductor device and mounting method thereofInfo
- Publication number
- JPH02239651A JPH02239651A JP1060436A JP6043689A JPH02239651A JP H02239651 A JPH02239651 A JP H02239651A JP 1060436 A JP1060436 A JP 1060436A JP 6043689 A JP6043689 A JP 6043689A JP H02239651 A JPH02239651 A JP H02239651A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- semiconductor
- wiring board
- semiconductor devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 101
- 238000000034 method Methods 0.000 title claims description 12
- 238000004904 shortening Methods 0.000 abstract description 2
- 230000006870 function Effects 0.000 description 7
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 238000003860 storage Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 239000007767 bonding agent Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置技術に関し、特に、半導体チップ
を収容するパッケージ構造技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor device technology, and particularly to package structure technology for accommodating semiconductor chips.
近年、電子装置の小形化、高機能化の観点から、配線基
板上に実装されるＬＳＩパッケージの高密度実装化が進
められている。そして、ＬＳＩパッケージの高密度実装
化に伴い、ＬＳＩパッケージには、ＬＳＩチップを外部
環境から保謹したり、ＬＳＩチップのハンドリングを可
能にしたりするという基本的な機能の他に高密度実装化
のための様々な機能が要求されている。In recent years, from the viewpoint of downsizing and increasing functionality of electronic devices, high-density packaging of LSI packages mounted on wiring boards has been progressing. In addition to the basic functions of protecting the LSI chip from the external environment and making it possible to handle the LSI chip, as LSI packages become more densely packaged, Various functions are required for this purpose.
ＬＳＩパッケージ構造については、日経マグロウヒル社
発行、「日経エレクトロニクス別冊Ｎα２．マイクロデ
バイセズ、１９８４年６月ｌ１日」Ｐ１２９〜１６８に
記載があり、ＤＩＰに代表されるビン挿入形のパッケー
ジやＱＦＰやＳＯＪに代表される面実装形のパッケージ
について、それらの構造やそれらを構成するパフケージ
材料等、様々な角度から多様化するパッケージ構造につ
いて説明されている。The LSI package structure is described in "Nikkei Electronics Separate Volume Nα2. Micro Devices, June 11, 1984," published by Nikkei McGraw-Hill, pp. 129-168. The book describes the diversifying package structures of typical surface-mount packages from various angles, such as their structures and the puff cage materials that make them up.
ところで、従来、このようなＬＳＩパッケージを配線基
板上に実装するには、片面、両面いずれの実装方式でも
、複数のＬＳＩパッケージを配線基板の平面上、水平方
向に実装していた。Incidentally, conventionally, in order to mount such LSI packages on a wiring board, a plurality of LSI packages have been mounted horizontally on the plane of the wiring board, regardless of whether the mounting method is one-sided or double-sided.
ところが、複数のＬＳＩパッケージを配線基板の平面上
、水平方向に実装する従来の技術においては、実装が水
平方向に展開されるため、ＬＳＩパッケージの大面積化
、配線基板に構成される回路機能の拡張、あるいは記憶
容量の増加に伴って、配線基板の面積も大面積化しなけ
ればならなかった。However, in the conventional technology in which multiple LSI packages are mounted horizontally on the plane of a wiring board, the mounting is carried out horizontally, resulting in an increase in the area of the LSI package and an increase in circuit functions configured on the wiring board. With the expansion or increase in storage capacity, the area of the wiring board also had to increase.
また、配線基板上に回路が構成された後、その配線基板
の回路機能を拡張したり、あるいはメモリ製品であれば
記憶容量を増加させたりすることはできなかった。した
がって、例えばメモリ製品の場合、記憶容量を増加させ
るには、複数の配線基板を用意しなければならず、配線
基板を組み込む電子装置も大形化していた。Further, after a circuit is configured on a wiring board, it is not possible to expand the circuit function of the wiring board or increase the storage capacity in the case of a memory product. Therefore, for example, in the case of memory products, in order to increase the storage capacity, it is necessary to prepare a plurality of wiring boards, and the size of the electronic device incorporating the wiring boards has also increased.
本発明は上記課題に着目してなされたものであり、その
目的は、ＬＳＩパッケージの実装密度を向上させること
のできる技術を提供することにある。The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that can improve the packaging density of LSI packages.
本発明の前記ならびにその他の目的と新規な特徴は、明
細書の記述および添付図面から明らかになるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、以下のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体チップを収容するパッケージの一面に
凸部を形成し、かつ他面に凹部を形成するとともに、前
記凸部、および凹部の形成されたパッケージ面に前記半
導体チップと導通ずる外部端子を配匿することによって
、一のパッケージの前記凸部と、他のパッケージの前記
凹部とを嵌め合わせ、これらパッケージの同一信号、お
よび同一電源電圧用の外部端子同士を導通させるパッケ
ージ構造を備える半導体装匿である。That is, a convex portion is formed on one side of a package that accommodates a semiconductor chip, and a concave portion is formed on the other side, and external terminals that are electrically connected to the semiconductor chip are arranged on the package surface where the convex portion and the concave portion are formed. A semiconductor device comprising a package structure in which the convex portion of one package and the concave portion of another package are fitted into each other and the external terminals of the packages for the same signal and the same power supply voltage are electrically connected to each other. It is.
また、半導体装置を配線基板上に複数実装する際、前記
一のパッケージの凸部と他のパッケージの凹部とを嵌合
することによって、これらパッケージを備える半導体装
置同士を着脱自在に接合する半導体装置の実装方法であ
る。Further, when a plurality of semiconductor devices are mounted on a wiring board, the semiconductor devices including these packages are removably joined to each other by fitting the convex portion of the one package to the concave portion of another package. This is the implementation method.
さらに、半導体装置を配線基板上に複数実装する際、前
記パッケージ同士を嵌合することによって、これらパッ
ケージを備える半導体装置を配線基板の実装面に対して
垂直な方向に積み重ねる半導体装置の実装方法である。Furthermore, when a plurality of semiconductor devices are mounted on a wiring board, the semiconductor devices including the packages are stacked in a direction perpendicular to the mounting surface of the wiring board by fitting the packages together. be.
上記した第１の手段によれば、複数の半導体装置を、各
半導体装置を構成するパッケージ同士が密着した状態で
導通させることができるため、半導体装置間の間隔が短
くなり、実装密度を向上させることが可能となる。According to the first means described above, a plurality of semiconductor devices can be electrically connected with the packages constituting each semiconductor device being in close contact with each other, thereby shortening the distance between the semiconductor devices and improving the packaging density. becomes possible.
第２の手段によれば、半導体装置の着脱が可能になるた
め、故障した半導体装置のみを取り替えたり、半導体装
置の着脱により回路機能や記憶容量等を適宜変えたりす
ることが可能となる。According to the second means, since the semiconductor device can be attached and detached, it is possible to replace only a failed semiconductor device, or to change the circuit function, storage capacity, etc. as appropriate by attaching and detaching the semiconductor device.
第３の手段によれば、半導体装置の実装が、配線基板の
実装面に対して水平方向に展開されるのみならず、実装
面に対して垂直な方向にも展開されるため、従来と同じ
実装面積であっても従来よりも実装数を増加させること
が可能である。According to the third means, the semiconductor device is mounted not only horizontally to the mounting surface of the wiring board but also perpendicularly to the mounting surface, which is the same as in the conventional method. Even in terms of mounting area, it is possible to increase the number of mountings compared to the conventional method.
〔実施例１〕
第１図は本発明の一実施例である半導体装置のパフケー
ジ外観を示す斜視図、第２図は第１図の■一■線断面図
、第３図はこの半導体装置を複数積み重ねた状態を示す
断面図、第４図はこの半導体装置を配線基板上に実装し
た状態を示す斜視図、第５図は配線基板上における半導
体装置の積み重ね状態を示す斜視図である。[Example 1] Fig. 1 is a perspective view showing the appearance of a puff cage of a semiconductor device according to an embodiment of the present invention, Fig. 2 is a cross-sectional view taken along the line FIG. 4 is a cross-sectional view showing a state in which a plurality of semiconductor devices are stacked, FIG. 4 is a perspective view showing a state in which the semiconductor devices are mounted on a wiring board, and FIG. 5 is a perspective view showing a state in which semiconductor devices are stacked on a wiring board.
まず、本実施例ｌの半導体装置の構造を第１図〜第３図
により説明する。First, the structure of the semiconductor device of Example 1 will be explained with reference to FIGS. 1 to 3.
本実施例１の半導体装置１ａは、第１図に示すように、
パッケージ２ａの上面の中央部に、例えば四角柱状の凸
部３ａが形成され、かつ第２ｒ！！Ｊに示すように、パ
ッケージ２ａの裏面に凹部４ａが形成された樹脂モール
ド型のパッケージ構造となっている。As shown in FIG. 1, the semiconductor device 1a of the first embodiment has the following features:
For example, a rectangular prism-shaped convex portion 3a is formed in the center of the upper surface of the package 2a, and a second r! ! As shown in J, the package has a resin mold type package structure in which a recess 4a is formed on the back surface of the package 2a.
凸１３ａの形成されたパッケージ２ａの上面には、４２
アロイ等からなる複数の外部リード（外郎端子＞５３が
パッケージ２ａの周辺方向に沿って並設されている。そ
して、これら外部リード５ａは、パッケージ２ａの側面
に沿って垂直に折曲し、さらに凹部４ａの形成されたパ
ッケージ２ａの裏面にＪ字状に回り込み、その先端がパ
ッケージ２ａの裏面に形成された溝部６ａに保持されて
いる。On the top surface of the package 2a on which the protrusion 13a is formed, there are 42
A plurality of external leads (Uiro terminals >53) made of alloy or the like are arranged in parallel along the peripheral direction of the package 2a.These external leads 5a are bent vertically along the side surface of the package 2a, and It wraps around in a J-shape around the back surface of the package 2a where the recess 4a is formed, and its tip is held in a groove 6a formed on the back surface of the package 2a.
一方、第２図に示すように、外部リード５ａと一体成型
されてなる内部リード７は、パッケージ２ａの内部に埋
設されており、その一端は、金、あるいは銅等からなる
ボンディングワイヤ８を介して所定の集積回路が構成さ
れた半導体チップ９の図示しないボンディングパッドと
電気的に接続されている。この半導体チップ９は、例え
ばエポヰシ樹脂からなる接合剤１０により、４２１ロイ
等からなるグイパッドｌｌ上に接合されている。On the other hand, as shown in FIG. 2, an internal lead 7 integrally molded with an external lead 5a is buried inside the package 2a, and one end of the internal lead 7 is connected via a bonding wire 8 made of gold or copper. The semiconductor chip 9 is electrically connected to bonding pads (not shown) of a semiconductor chip 9 on which a predetermined integrated circuit is constructed. This semiconductor chip 9 is bonded onto a pad 11 made of 421 roy or the like using a bonding agent 10 made of, for example, epoxy resin.
パノケージ２ａの上記した凹部４ａは、このパッケージ
２ａと同一形状の他のパッケージ２ａのの凸部３ａを嵌
め合わせた際、その凸部３ａを保持できる形状、および
寸法となっているため、第３図に示すように、各パッケ
ージ２ａの凸ｆｌ’ｔｓ３ａと凹部４ａとを嵌合して固
定し、複数の半導体装置１ａ，ｌａ同士を積み重ねるこ
とが可能な構造となっている。The above-mentioned recess 4a of the pano cage 2a has a shape and size that can hold the protrusion 3a of another package 2a having the same shape as this package 2a when the convex part 3a is fitted. As shown in the figure, the convex fl'ts 3a of each package 2a and the concave portion 4a are fitted and fixed, so that a plurality of semiconductor devices 1a, la can be stacked on top of each other.
そして、本実施例１の半導体装置１ａは、同一信号、お
よび同一電源電圧用の外部リード５ａの一部がパッケー
ジ２ａの上面と、パッケージ２ａの裏面とに配置されて
いるため、複数の半導体装ｌｆｌａ．ｌａをパッケージ
２ａの高さ方向に積み重ねた際、各半導体装！１１ａの
同一の外部リード５ａ，５ａ同士が電気的に接続される
構造となっている。In the semiconductor device 1a of the first embodiment, a part of the external lead 5a for the same signal and the same power supply voltage is arranged on the top surface of the package 2a and the back surface of the package 2a, so that a plurality of semiconductor devices lfla. When la is stacked in the height direction of package 2a, each semiconductor device! The structure is such that the same external leads 5a, 5a of 11a are electrically connected to each other.
なお、パッケージ２ａの上面の一隅には、複数のパッケ
ージ２ａ，２ａ同士を積み重ねる際、極性や接続する外
部リード５ａ，５ａ同士を間違えないように、目印Ｍが
刻設されている。Note that a mark M is engraved on one corner of the upper surface of the package 2a so that when stacking a plurality of packages 2a, 2a, the polarity and the external leads 5a, 5a to be connected are not mistaken.
このようなパッケージ構造の半導体装置を製造するには
、例えば次のようにする。To manufacture a semiconductor device having such a package structure, for example, the following procedure is performed.
すなわち、まず、リードフレームにおけるグイバッド１
１上に半導体チップ９を接合し、半導体チップ９のボン
ディングパッドとリードフレームの内部リード７とをワ
イヤボンディング８によって接合した後、このリードフ
レームを所定の金型に収めて半導体チップ９を樹脂によ
ってモールドしパッケージ２ａを形成する。That is, first, Guibad 1 in the lead frame
After bonding the semiconductor chip 9 onto the semiconductor chip 1 and bonding the bonding pads of the semiconductor chip 9 and the internal leads 7 of the lead frame by wire bonding 8, the lead frame is placed in a predetermined mold and the semiconductor chip 9 is bonded with resin. A package 2a is formed by molding.
次いで、樹脂が硬化した後、樹脂から露出する外部リー
ド５ａを所定長で切断し、パッケージ２ａを上記リード
フレームの外枠から分離した後、外部リード５ａをパッ
ケージ２ａの側面に沿って垂直に折曲し、さらにパッケ
ージ２ａの裏面に形成された溝Ｎ６ａで保持させる。Next, after the resin has hardened, the external leads 5a exposed from the resin are cut to a predetermined length, the package 2a is separated from the outer frame of the lead frame, and the external leads 5a are vertically folded along the side surfaces of the package 2a. The package 2a is bent and held in a groove N6a formed on the back surface of the package 2a.
次に、本実施例ｌの半導体装Ｉｔ１の実装方法を第４図
、および第５図により説明する。なお、配線基板のラン
ド上に半導体装置１ａを実装する方法（第４図により説
明）は従来技術と同じである。Next, a method for mounting the semiconductor device It1 of Example 1 will be explained with reference to FIGS. 4 and 5. Note that the method for mounting the semiconductor device 1a on the land of the wiring board (explained with reference to FIG. 4) is the same as the conventional technique.
まず、配線基板１２上にメタルマスクを用いた印刷方式
等によりクリームはんだ（図示せず）を塗布し、その後
、半導体装置１ａをバキューム・ピックアップ（図示せ
ず）等により吸着し、この半導体装置１ａの外部リード
５ａと配線基板１２のランドｌ３とを位置合わせした状
態で、この半導体装置１ａを上記したクリームはんだに
軽く押し込む。なお、半導体装置１ａの吸着、およびク
リームはんだへの押し込み等は、例えば全てプログラム
・コントロールにより自動的に行われる。First, cream solder (not shown) is applied onto the wiring board 12 by a printing method using a metal mask, etc., and then the semiconductor device 1a is picked up by a vacuum pickup (not shown) or the like, and the semiconductor device 1a is With the external leads 5a and the lands 13 of the wiring board 12 aligned, the semiconductor device 1a is lightly pushed into the cream solder described above. Incidentally, the suction of the semiconductor device 1a, the pressing into the cream solder, etc. are all performed automatically under program control, for example.
その後、リフローはんだ付け法、あるいはＶＰＳ （Ｖ
ａｐｏｒ Ｐｈａｓｅ ｒｅｆｌｏｗ Ｓｏｌｄｅｒｉ
ｎｇ） 法等により、はんだを溶かしはんだ付けを行
い、配線基板１２上に半導体装置ｌａを実装する（第４
図）。After that, reflow soldering method or VPS (V
apor Phase reflow
ng) melt the solder and perform soldering to mount the semiconductor device la on the wiring board 12 (4th step).
figure).
次に、配線基板ｌ２に実装された半導体装置ｌａのパッ
ケージ２ａの目印Ｍ《第４図参照》と、その上に積み重
ねて実装する半導体装置１ａのパッケージ２ａの目印Ｍ
とを合わせた状態で、下方のパッケージ２ａの凸部３ａ
と、その上に積み重ねて実装するパッケージ２ａの凹部
４ａ（第２図参照》とを嵌め合わせる。Next, the mark M of the package 2a of the semiconductor device la mounted on the wiring board l2 (see FIG. 4), and the mark M of the package 2a of the semiconductor device 1a stacked and mounted thereon.
The convex portion 3a of the lower package 2a
and the recess 4a (see FIG. 2) of the package 2a to be stacked and mounted thereon.
そして、下方のパッケージ２ａの上面に位置する外部リ
ード５ａとその上方に積み重ねるパッケージ２ａの裏面
に位置する外部リード５ａとが確実に導通状態となるよ
うに上方のパッケージ２ａを押し込み、半導体装置１ａ
を配線基板ｌ２の実装面Ａに対して垂直な方向に積み重
ねる（第５図）。Then, the upper package 2a is pushed in so that the external lead 5a located on the upper surface of the lower package 2a and the external lead 5a located on the back surface of the package 2a stacked above it are in a conductive state.
are stacked in a direction perpendicular to the mounting surface A of the wiring board l2 (FIG. 5).
この際、本実施例ｌでは、半導体装置１ａ．１ａ同士を
着脱自在の状態にしておくが、パッケージ２ａの凸部３
ａｓまたは凸部３ａを嵌め込む凹部４ａにエポキシ樹脂
等の接着剤を塗布し、これらパッケージ２ａ，２ａ同士
を接着し、半導体装置１ａ，ｌａ同士を確実に固定して
も良い。At this time, in this embodiment 1, the semiconductor device 1a. 1a are made detachable from each other, but the protrusion 3 of the package 2a
An adhesive such as epoxy resin may be applied to the concave portion 4a into which the as or convex portion 3a is fitted, and the packages 2a, 2a may be adhered to each other to securely fix the semiconductor devices 1a, la.
このように本実施例１によれば、以下の効果を得ること
ができる。As described above, according to the first embodiment, the following effects can be obtained.
（１）．パッケージ２ａ，２ａを密着した状態で半導体
装置１ａ，ｌａ同士を導通することができるため、半導
体装置１ａ，ｌａ間の間隔が短《なり、実装密度を高密
度化することができる。(1). Since the semiconductor devices 1a, la can be electrically connected to each other while the packages 2a, 2a are in close contact with each other, the distance between the semiconductor devices 1a, la can be shortened, and the packaging density can be increased.
（２）．半導体装置１ａを配線基板ｌ２の実装面Ａに対
して水平な方向に実装するのみならず、実装面Ａに対し
て垂直な方向に積み重ね実装することができるため、従
来と同じ実装面積であっても、従来よりも多くの半導体
装置１ａを実装することが可能となる。(2). The semiconductor device 1a can be not only mounted horizontally to the mounting surface A of the wiring board l2, but also stacked and mounted in a direction perpendicular to the mounting surface A. Also, it becomes possible to mount more semiconductor devices 1a than before.
（３）．積み重ねた複数の半導体装置１ａ同士を着脱自
在の状態に固定しておけば、故障した半導体装置１ａの
みを取り替えたり、半導体装置１ａの着脱により回路機
能や記憶容量等を適宜変えたりすることが可能となる。(3). By fixing a plurality of stacked semiconductor devices 1a in a removable state, it is possible to replace only the failed semiconductor device 1a, or change the circuit function, storage capacity, etc. as appropriate by attaching and detaching the semiconductor devices 1a. becomes.
（４）．上記（１）により、各パッケージ２ａ，２ａ間
の配線長が従来技術に比べて短くなるため、信号の伝達
速度を高速にすることが可能となる。(4). Due to the above (1), the wiring length between each package 2a, 2a is shorter than that in the prior art, so it is possible to increase the signal transmission speed.
（５）．上記（１）． （４）により、配線長が短くな
るため、外来ノイズの影響を受けにくくなり、信頼性の
高い信号の授受が可能となる。(5). Above (1). Due to (4), the wiring length is shortened, which makes it less susceptible to external noise and enables highly reliable signal transmission and reception.
〔実施例２〕
第６図は本発明の他の実施例を示す半導体装置のパッケ
ージ外観を示す斜視図、第７図は第６図で示した半導体
装置の積み重ね状態を示す斜視図、第８図は第６図で示
した半導体装置を配線基板上に実装した状態を示す斜視
図である。[Embodiment 2] FIG. 6 is a perspective view showing the external appearance of a package of a semiconductor device showing another embodiment of the present invention, FIG. 7 is a perspective view showing a stacked state of the semiconductor devices shown in FIG. 6, and FIG. This figure is a perspective view showing a state in which the semiconductor device shown in FIG. 6 is mounted on a wiring board.
第６図に示すように、本実施例２の半導体装置１ｂは、
パフケージ２ｂの上面の一部に四角柱状の凸部３ｂが形
成され、かつパッケージ２ｂの裏面に凹部４ｂが形成さ
れた樹脂モールド形のパッケージ構造となっている。As shown in FIG. 6, the semiconductor device 1b of the second embodiment is as follows:
It has a resin molded package structure in which a rectangular prism-shaped convex portion 3b is formed on a part of the upper surface of the puff cage 2b, and a recessed portion 4b is formed on the back surface of the package 2b.
凸部３ｂには、コ字状に折曲した複数の外部リード５ｂ
が、パッケージ２ｂの長手力向に並設されている。そし
て、外部リード５ｂの一端は、パッケージ２ｂの上面に
形成された溝ａｔｓ６ｂにより保持されている。The convex portion 3b has a plurality of external leads 5b bent in a U-shape.
are arranged in parallel in the longitudinal direction of the package 2b. One end of the external lead 5b is held by a groove ats6b formed on the upper surface of the package 2b.
パッケージ２ｂの上面の四隅には、小凸部３Ｃが形成さ
れており、これと同一形状のパッケージ構造の他の半導
体装置１ｂを積み重ねた際、その固定度を高め、かつ接
続される外部リード５ｂの位置がずれてしまうことを防
止する構造となっている。Small convex portions 3C are formed at the four corners of the upper surface of the package 2b, which improves the degree of fixation when other semiconductor devices 1b having the same package structure are stacked together, and provides external leads 5b to be connected. It has a structure that prevents the position from shifting.
一方、凹部４ｂにおける一側面には、複数の外部リード
５ｂが、パッケージ２ｂの長手力向に沿って並設されて
いる。On the other hand, on one side of the recess 4b, a plurality of external leads 5b are arranged in parallel along the longitudinal direction of the package 2b.
また、パフケージ２ｂの裏面の四隅には、パッケージ２
ｂ，２ｂを嵌め合わせた際、上記した小凸部３Ｃを嵌め
込むための小凹部４Ｃ（第１０図）が形成されている。In addition, the package 2 is placed in the four corners of the back of the puff cage 2b.
When b and 2b are fitted together, a small recess 4C (FIG. 10) is formed into which the above-mentioned small protrusion 3C is fitted.
なお、凸１１’ｌｓ３ｂの一端には、複数の半導体装置
１ｂ，１ｂ同士を積み重ねる際、極性等を間違えないよ
うにするために目印Ｍが刻設されている。Note that a mark M is engraved on one end of the protrusion 11'ls3b in order to avoid mistakes in polarity, etc. when stacking a plurality of semiconductor devices 1b, 1b on top of each other.
本実施例２においても第７図に示すようにパッケージ２
ｂ，２ｂの凸部３ｂと凹部４ｂとを嵌合し、これらパフ
ケージ２ｂ，２ｂを固定して半導体装置１ｂ，ｌｂ同士
を積み重ねることが可能な構造となっている。そして、
凸部３ｂと凹部４ｂに形成された外部リード５ｂ，５ｂ
が電気的に接続される構造となっている。In this second embodiment as well, the package 2
The structure is such that the semiconductor devices 1b, 1b can be stacked together by fitting the protrusions 3b and the recesses 4b of the puff cages 2b, 2b and fixing the puff cages 2b, 2b. and,
External leads 5b, 5b formed in the convex portion 3b and the concave portion 4b
The structure is such that they are electrically connected.
ところで、このようなパッケージ構造の半導体装置１ｂ
を配線基板上に実装するには、第８図に示すように、例
えば予め配線基板ｌ２上にソケット１４ａを接続してお
き、このソケット１４ａに半導体装置１ｂを実装する。By the way, the semiconductor device 1b having such a package structure
To mount the semiconductor device 1b on a wiring board, for example, a socket 14a is connected in advance onto the wiring board 12, and the semiconductor device 1b is mounted on this socket 14a, as shown in FIG.
ソケッ｝１４ａは、断面凸状となっており、その凸状部
１５の形状や寸法は、上記したパフケージ２ｂの凹部４
ｂと嵌合した際、パッケージ２ｂを固定できるように設
計されている。ソケット■４ａの凸状部１５の一側面に
は、パッケージ２ｂを嵌合した際、パッケージ２ｂの凹
部４ｂに形成された外部リード５ｂと電気的な導通を取
るための複数の接触子１６が並設されている。接触子１
６は、パッケージ２ｂを嵌合した際、窪みＩｌｆＳ１７
の方向に押されるため、凹部４ｂに形成された外部リー
ド５ｂ（第６図参照）を押さえる方向に付勢される。な
お、接触子ｌ６は、４２７ロイ等からなりその表面に金
等のメッキが施されている。The socket 14a has a convex cross section, and the shape and dimensions of the convex portion 15 are similar to the concave portion 4 of the puff cage 2b described above.
The package 2b is designed to be fixed when the package 2b is fitted with the package 2b. A plurality of contacts 16 are lined up on one side of the convex portion 15 of the socket 4a for establishing electrical continuity with the external lead 5b formed in the recess 4b of the package 2b when the package 2b is fitted. It is set up. contact 1
6 is a recess IlfS17 when the package 2b is fitted.
Since it is pushed in the direction of , it is urged in the direction of pressing the external lead 5b (see FIG. 6) formed in the recess 4b. The contact 16 is made of 427 Roy or the like, and its surface is plated with gold or the like.
また、ソケッ｝１４ａの肩邪に形成された小凸状部１８
は、パッケージ２ｂの裏面の四隅に形成された小凹部４
ｃ（第１０図》に嵌め合わせるための突起部である。In addition, a small convex portion 18 formed at the shoulder of the socket 14a
are small recesses 4 formed at the four corners of the back surface of the package 2b.
c (Fig. 10) is a protrusion for fitting.
なお、半導体装置１ｂの積み重ね方法は、実施例１と同
じである。Note that the method of stacking the semiconductor devices 1b is the same as in the first embodiment.
本実施例２によれば、実施例ｌの（１）〜（５）の効果
の他に、複数の半導体装置１ｂを配線基板１２の実装面
に対して垂直な方向に実装した際、最下方の半導体装置
１ｂも自由に取り替えることができる効果がある。According to the second embodiment, in addition to the effects (1) to (5) of the first embodiment, when a plurality of semiconductor devices 1b are mounted in a direction perpendicular to the mounting surface of the wiring board 12, the lowermost There is an advantage that the semiconductor device 1b can also be replaced freely.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例１，２に限定
されるものではなく、その要旨を逸脱しない範囲で種々
変更可能であることはいうまでもない。The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to Examples 1 and 2, and can be modified in various ways without departing from the gist thereof. Needless to say.
例えば、前記実施例ｌにおいては、一つのパッケージの
面に一つの凸部を形成した場合について説明したが、こ
れに限定されるものではなく、例えば一つのパッケージ
面に複数の凸部を形成するとともに、これと嵌合するパ
ッケージ面に凸部に対応する複数の凹部を形成しても良
い。For example, in the above-mentioned Example 1, the case where one convex portion is formed on the surface of one package is described, but the present invention is not limited to this. For example, a plurality of convex portions may be formed on the surface of one package. At the same time, a plurality of recesses corresponding to the projections may be formed on the surface of the package to be fitted thereto.
また、前記実施例１，２においては、凸部を四角柱状と
した場合について説明したが、これに限定されるもので
はなく、例えば第９図に示すように半導体装置１ｃを構
成するパッケージ２Ｃの上面の一部にテーバ状の凸部３
ｄを形成しても良い。Further, in the first and second embodiments, the case where the convex portion is shaped like a square prism has been described, but the convex portion is not limited to this. For example, as shown in FIG. A tapered convex portion 3 on a part of the upper surface
d may also be formed.
また、前記実施例２においては、半導体装置を配線基板
に実装する際、予め配線基板にパッケージの凹部用のソ
ケットを実装した場合について説明したが、これに限定
されるものではな《、例えば第ｌＯ図に示すように、ソ
ケッｌ−１４ｂに凹状の挿入部１９を設け、この挿入部
１９にパッケージ２ｂの凸１ｍ３ｂを嵌合し、半導体装
置１ｂを配線基板１２上に実装しても良い。Further, in the second embodiment, a case has been described in which a socket for a concave portion of a package is mounted on a wiring board in advance when a semiconductor device is mounted on a wiring board, but the present invention is not limited to this. As shown in FIG. 1O, a concave insertion portion 19 may be provided in the socket l-14b, the protrusion 1m3b of the package 2b may be fitted into the insertion portion 19, and the semiconductor device 1b may be mounted on the wiring board 12.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野である樹脂モールド形のパ
ッケージを備える半導体装置に適用した場合について説
明したが、これに限定されず種々適用可能であり、例え
ばセラミック形のパッケージを備える半導体装置に適用
しても良い。In the above explanation, the invention made by the present inventor is mainly applied to a semiconductor device equipped with a resin molded package, which is the field of application in which the invention was made by the present inventor, but the invention is not limited to this, and various other applications are possible. For example, the present invention may be applied to a semiconductor device equipped with a ceramic package.
本願において開示される発明のうち、代表的なものによ
って得られる効果を簡単に説明すれば、下記のとおりで
ある。Among the inventions disclosed in this application, the effects obtained by typical inventions are briefly described below.
すなわち、第１に、複数の半導体装置を、各半導体装置
を構成するパッケージ同士を密着した状態で導通するこ
とができるため、半導体装置間の間隔が短くなり、実装
密度を向上させることが可能となる。First, it is possible to connect a plurality of semiconductor devices with the packages that make up each semiconductor device in close contact with each other, which shortens the distance between the semiconductor devices and improves packaging density. Become.
第２に、半導体ｉ置の着脱が可能になるため、故障した
半導体装置のみを取り替えたり、半導体装置の着脱によ
り回路機能や記憶容量等を適宜変えたりすることが可能
となる。Second, since it becomes possible to attach and detach every semiconductor device, it becomes possible to replace only a failed semiconductor device, or to change the circuit function, storage capacity, etc. as appropriate by attaching and detaching the semiconductor device.
第３に、半導体装置の実装が配線基板の実装面に対して
水平な方向のみならず、実装面に対して垂直な方向に展
開されるため、従来と同じ実装面積であっても従来より
多くの半導体装置を実装することが可能となる。Third, because semiconductor devices are mounted not only horizontally to the mounting surface of the wiring board but also perpendicularly to the mounting surface, the mounting area is the same as before, but the mounting area is larger than before. It becomes possible to mount several semiconductor devices.
第１図は゛本発明の一実施例である半導体装筐のパフケ
ージ外観を示す斜視図、
第２図は第，１図の■−■線断面図、
第３図はこの半導体装置を複数積み重ねた状態を示す断
面図、
第４図はこの半導体装置を配線基板上に実装した状態を
示す斜視図、
第５図は配線基板上における半導体装置の積み重ね状態
を示す斜視図、
第６図は本発明の他の実施例を示す半導体装置のパッケ
ージ外観を示す斜視図、
第７図は第６図に示した半導体装置の積み重ね状態を示
す斜視図、
第８図は第６図に示した半導体装置を配線基板上に実装
した状態を示す斜視図、
第９図は実施例のさらに他の実施例である半導体装置の
パッケージ外観を示す斜視図、第１０図は実施例２で示
したコネクタの変形例を示す斜視図である。
ｌａ，ｌｂ，ｌｃ−・・半導体装胃、２ａ．２ｂ，２ｃ
−− ・パッケージ、３ａ，３ｂ，３ｄ・・・凸部、３
Ｃ・・・小凸部、４ａ，４ｂ・・・凹部、４Ｃ・・・小
凹部、５ａ，５ｂ・・・外部リード（外部端子）、６ａ
．６ｂ・・・溝部、７・・・内部リード、８・・・ボン
ディングワイヤ、９・・・半導体チップ、１０・・・接
合剤、１１・・・グイパッド、ｌ２・・・配線基板、ｌ
３・・・ランド、１４ａ．１４ｂ・・・ソケット、ｌ５
・・・凸状部、ｌ６・・・接触子、ｌ７・・・窪み部、
１８・・・小凸状部、１９・・・挿入部、Ａ・・・実装
面、Ｍ・・・目印。
代理人 弁理士 筒 井 大 和
第 １ 図
第２図
＃ ３ 図
第
図
第
図Fig. 1 is a perspective view showing the appearance of a puff cage of a semiconductor device according to an embodiment of the present invention, Fig. 2 is a sectional view taken along the line ■-■ in Figs. 4 is a perspective view showing the semiconductor device mounted on the wiring board; FIG. 5 is a perspective view showing the semiconductor device stacked on the wiring board; FIG. 6 is the invention of the present invention. 7 is a perspective view showing the stacked state of the semiconductor devices shown in FIG. 6, and FIG. 8 is a perspective view showing the semiconductor device shown in FIG. 6 in a stacked state. FIG. 9 is a perspective view showing the appearance of a package of a semiconductor device which is still another embodiment of the embodiment; FIG. 10 is a modification of the connector shown in Embodiment 2; FIG. FIG. la, lb, lc--semiconductor-packed stomach, 2a. 2b, 2c
-- ・Package, 3a, 3b, 3d...Protrusion, 3
C...Small convex part, 4a, 4b...Concave part, 4C...Small concave part, 5a, 5b...External lead (external terminal), 6a
．． 6b... Groove, 7... Internal lead, 8... Bonding wire, 9... Semiconductor chip, 10... Bonding agent, 11... Gui pad, l2... Wiring board, l
3... Land, 14a. 14b...Socket, l5
... Convex portion, l6... Contact, l7... Concave portion,
18... Small convex portion, 19... Insertion part, A... Mounting surface, M... Mark. Agent Patent Attorney Daiwa Tsutsui Figure 1 Figure 2 Figure 3 Figure Figure #3
Claims (1)
形成し、かつ他面に凹部を形成するとともに、前記凸部
、および凹部の形成されたパッケージ面に前記半導体チ
ップと導通する外部端子を配置することによって、一の
パッケージの前記凸部と、他のパッケージの前記凹部と
を嵌め合わせ、これらパッケージの同一信号、および同
一電源電圧用の外部端子同士を導通させるパッケージ構
造を備えることを特徴とする半導体装置。 ２、請求項１記載の半導体装置を配線基板上に複数実装
する際、前記一のパッケージの凸部と他のパッケージの
凹部とを嵌合することによって、これらパッケージを備
える半導体装置同士を着脱自在に接合することを特徴と
する半導体装置の実装方法。 ３、請求項１記載の半導体装置を配線基板上に複数実装
する際、前記パッケージ同士を嵌合することによって、
これらパッケージを備える半導体装置を配線基板の実装
面に対して垂直な方向に積み重ねることを特徴と半導体
装置の実装方法。[Claims] 1. A convex portion is formed on one side of a package that accommodates a semiconductor chip, and a concave portion is formed on the other side, and the semiconductor chip and the package surface on which the convex portion and the concave portion are formed are formed. A package structure in which the convex portion of one package and the concave portion of another package are fitted together by arranging conductive external terminals, and the external terminals of these packages for the same signal and the same power supply voltage are made conductive to each other. A semiconductor device comprising: 2. When a plurality of semiconductor devices according to claim 1 are mounted on a wiring board, the semiconductor devices including these packages can be freely attached and detached by fitting the convex part of the one package and the concave part of another package. A method for mounting a semiconductor device, characterized by bonding to a semiconductor device. 3. When mounting a plurality of semiconductor devices according to claim 1 on a wiring board, by fitting the packages together,
A semiconductor device mounting method characterized by stacking semiconductor devices including these packages in a direction perpendicular to the mounting surface of a wiring board.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6043689A JP2885414B2 (en) | 1989-03-13 | 1989-03-13 | Semiconductor device, mounting method thereof, and electronic device |
| KR1019900003253A KR0145696B1 (en) | 1989-03-13 | 1990-03-12 | Semiconductor device and an electronic device with the semiconductor device mounted thereon |
| US07/915,761 US5266834A (en) | 1989-03-13 | 1992-07-21 | Semiconductor device and an electronic device with the semiconductor devices mounted thereon |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6043689A JP2885414B2 (en) | 1989-03-13 | 1989-03-13 | Semiconductor device, mounting method thereof, and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02239651A true JPH02239651A (en) | 1990-09-21 |
| JP2885414B2 JP2885414B2 (en) | 1999-04-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6043689A Expired - Fee Related JP2885414B2 (en) | 1989-03-13 | 1989-03-13 | Semiconductor device, mounting method thereof, and electronic device |
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| Country | Link |
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Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5567653A (en) * | 1994-09-14 | 1996-10-22 | International Business Machines Corporation | Process for aligning etch masks on an integrated circuit surface using electromagnetic energy |
| US5616962A (en) * | 1992-01-24 | 1997-04-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit devices having particular terminal geometry |
| US5670429A (en) * | 1993-06-30 | 1997-09-23 | Rohm Co. Ltd. | Process of conveying an encapsulated electronic component by engaging an integral resin projection |
| US6163076A (en) * | 1999-06-04 | 2000-12-19 | Advanced Semiconductor Engineering, Inc. | Stacked structure of semiconductor package |
| KR20010058586A (en) * | 1999-12-30 | 2001-07-06 | 마이클 디. 오브라이언 | semiconductor package and mounting method using it |
| US6323060B1 (en) * | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
| US6404043B1 (en) | 2000-06-21 | 2002-06-11 | Dense-Pac Microsystems, Inc. | Panel stacking of BGA devices to form three-dimensional modules |
| US6424031B1 (en) | 2000-05-08 | 2002-07-23 | Amkor Technology, Inc. | Stackable package with heat sink |
| KR20030001032A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Mount structure of multi stack type package |
| US6518659B1 (en) | 2000-05-08 | 2003-02-11 | Amkor Technology, Inc. | Stackable package having a cavity and a lid for an electronic device |
| US6573460B2 (en) | 2001-09-20 | 2003-06-03 | Dpac Technologies Corp | Post in ring interconnect using for 3-D stacking |
| US6573461B2 (en) | 2001-09-20 | 2003-06-03 | Dpac Technologies Corp | Retaining ring interconnect used for 3-D stacking |
| US6667544B1 (en) | 2000-06-30 | 2003-12-23 | Amkor Technology, Inc. | Stackable package having clips for fastening package and tool for opening clips |
| JP2005167244A (en) * | 2003-12-04 | 2005-06-23 | Palo Alto Research Center Inc | Thin package used for stacked integrated circuit |
| US6977431B1 (en) | 2003-11-05 | 2005-12-20 | Amkor Technology, Inc. | Stackable semiconductor package and manufacturing method thereof |
| US7009296B1 (en) | 2004-01-15 | 2006-03-07 | Amkor Technology, Inc. | Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die |
| JP2009004622A (en) * | 2007-06-22 | 2009-01-08 | Sony Corp | Semiconductor device |
| JP2017504222A (en) * | 2014-12-23 | 2017-02-02 | インテル・コーポレーション | Integrated package design with multiple leads for package-on-package products |
| JP2021018912A (en) * | 2019-07-19 | 2021-02-15 | 株式会社ロゴスコーポレーション | Lighting device, combined structure of lighting device, mounting component, and mounting structure of lighting device and mounting component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49106276U (en) * | 1972-12-28 | 1974-09-11 | ||
| JPS5712754U (en) * | 1980-06-26 | 1982-01-22 |
-
1989
- 1989-03-13 JP JP6043689A patent/JP2885414B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49106276U (en) * | 1972-12-28 | 1974-09-11 | ||
| JPS5712754U (en) * | 1980-06-26 | 1982-01-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5616962A (en) * | 1992-01-24 | 1997-04-01 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit devices having particular terminal geometry |
| US5773321A (en) * | 1992-01-24 | 1998-06-30 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit devices having particular terminal geometry and mounting method |
| US5670429A (en) * | 1993-06-30 | 1997-09-23 | Rohm Co. Ltd. | Process of conveying an encapsulated electronic component by engaging an integral resin projection |
| US5739054A (en) * | 1993-06-30 | 1998-04-14 | Rohm Co., Ltd. | Process for forming an encapsulated electronic component having an integral resin projection |
| US5760481A (en) * | 1993-06-30 | 1998-06-02 | Rohm Co., Ltd. | Encapsulated electronic component containing a holding member |
| US5567653A (en) * | 1994-09-14 | 1996-10-22 | International Business Machines Corporation | Process for aligning etch masks on an integrated circuit surface using electromagnetic energy |
| US6514793B2 (en) | 1999-05-05 | 2003-02-04 | Dpac Technologies Corp. | Stackable flex circuit IC package and method of making same |
| US6323060B1 (en) * | 1999-05-05 | 2001-11-27 | Dense-Pac Microsystems, Inc. | Stackable flex circuit IC package and method of making same |
| USRE39628E1 (en) * | 1999-05-05 | 2007-05-15 | Stakick Group, L.P. | Stackable flex circuit IC package and method of making same |
| US6426549B1 (en) | 1999-05-05 | 2002-07-30 | Harlan R. Isaak | Stackable flex circuit IC package and method of making same |
| US6163076A (en) * | 1999-06-04 | 2000-12-19 | Advanced Semiconductor Engineering, Inc. | Stacked structure of semiconductor package |
| KR20010058586A (en) * | 1999-12-30 | 2001-07-06 | 마이클 디. 오브라이언 | semiconductor package and mounting method using it |
| US6518659B1 (en) | 2000-05-08 | 2003-02-11 | Amkor Technology, Inc. | Stackable package having a cavity and a lid for an electronic device |
| US6424031B1 (en) | 2000-05-08 | 2002-07-23 | Amkor Technology, Inc. | Stackable package with heat sink |
| US6404043B1 (en) | 2000-06-21 | 2002-06-11 | Dense-Pac Microsystems, Inc. | Panel stacking of BGA devices to form three-dimensional modules |
| US6544815B2 (en) | 2000-06-21 | 2003-04-08 | Harlan R. Isaak | Panel stacking of BGA devices to form three-dimensional modules |
| US6566746B2 (en) | 2000-06-21 | 2003-05-20 | Dpac Technologies, Corp. | Panel stacking of BGA devices to form three-dimensional modules |
| US6667544B1 (en) | 2000-06-30 | 2003-12-23 | Amkor Technology, Inc. | Stackable package having clips for fastening package and tool for opening clips |
| KR20030001032A (en) * | 2001-06-28 | 2003-01-06 | 동부전자 주식회사 | Mount structure of multi stack type package |
| US6573461B2 (en) | 2001-09-20 | 2003-06-03 | Dpac Technologies Corp | Retaining ring interconnect used for 3-D stacking |
| US6573460B2 (en) | 2001-09-20 | 2003-06-03 | Dpac Technologies Corp | Post in ring interconnect using for 3-D stacking |
| US6977431B1 (en) | 2003-11-05 | 2005-12-20 | Amkor Technology, Inc. | Stackable semiconductor package and manufacturing method thereof |
| JP2005167244A (en) * | 2003-12-04 | 2005-06-23 | Palo Alto Research Center Inc | Thin package used for stacked integrated circuit |
| US7009296B1 (en) | 2004-01-15 | 2006-03-07 | Amkor Technology, Inc. | Semiconductor package with substrate coupled to a peripheral side surface of a semiconductor die |
| JP2009004622A (en) * | 2007-06-22 | 2009-01-08 | Sony Corp | Semiconductor device |
| JP2017504222A (en) * | 2014-12-23 | 2017-02-02 | インテル・コーポレーション | Integrated package design with multiple leads for package-on-package products |
| US9960104B2 (en) | 2014-12-23 | 2018-05-01 | Intel Corporation | Integrated package design with wire leads for package-on-package product |
| JP2021018912A (en) * | 2019-07-19 | 2021-02-15 | 株式会社ロゴスコーポレーション | Lighting device, combined structure of lighting device, mounting component, and mounting structure of lighting device and mounting component |
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