JPS6379361A - Upright installation type semiconductor device - Google Patents
Upright installation type semiconductor deviceInfo
- Publication number
- JPS6379361A JPS6379361A JP61223581A JP22358186A JPS6379361A JP S6379361 A JPS6379361 A JP S6379361A JP 61223581 A JP61223581 A JP 61223581A JP 22358186 A JP22358186 A JP 22358186A JP S6379361 A JPS6379361 A JP S6379361A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- leads
- lead
- mounting board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000009434 installation Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000008188 pellet Substances 0.000 claims description 13
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000000034 method Methods 0.000 description 10
- 238000003780 insertion Methods 0.000 description 6
- 230000037431 insertion Effects 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置に適用して特に有効な技６ｆ：ｒ
に関するもので、たとえば、高密度実装が要求される立
設実装形半導体装置に適用して有効な技術に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention utilizes techniques 6f:r that are particularly effective when applied to semiconductor devices.
For example, it relates to a technique that is effective when applied to vertically mounted semiconductor devices that require high-density packaging.
ンングルインライパノケージ（Ｓ Ｉ Ｌ）形半導体装
置等の立設実装形半導体Ｂ ｇについて記載されている
例としては、たとえば昭和５５年１月ｌ０日、株式会社
工業調査会発行ｒＩＣ化実装技術」（日本マイクロエレ
クトロニクス協会１）Ｐｉ３６〜Ｐ１３７がある。ここ
では、パッケージ構造としてセラミックのものおよびプ
ラスチックのものについて各々のパッケージ構造の長短
について説明されている。An example of a vertically mounted semiconductor Bg such as a single-in-liber cage (SIL) type semiconductor device is described in ``RIC Mounting Technology'' published by Kogyo Kenkyukai Co., Ltd., January 10, 1981. ” (Japan Microelectronics Association 1) Pi36 to P137. Here, the merits and demerits of ceramic and plastic package structures are explained.
本発胡者は、立設実装形半導体装置のパッケージ構造に
ついて検討した。以下は、公知とされた技術ではないが
、本発明者によって検討された技術であり、その概要は
次の通りである。The authors studied the package structure of vertically mounted semiconductor devices. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.
すなわぢ、上記ＳＩＬ形の半導体装置ではパッケージの
一側面よりリードが突出されており、このリードの先端
を実装基板に設けられた挿入孔に挿入した状態で半田を
用いて固定する実装技術が知られている。ここで、上記
実装基板に穿孔される挿入孔としては、リード先端の加
工精度にともない直径が０．３ ＋ｎｍ程度の大きさの
ものが必要となる。In other words, in the SIL type semiconductor device mentioned above, a lead protrudes from one side of the package, and a mounting technique is used in which the tip of the lead is inserted into an insertion hole provided in the mounting board and fixed using solder. Are known. Here, the insertion hole to be drilled in the mounting board needs to have a diameter of about 0.3 + nm depending on the processing accuracy of the lead tip.
ところが、実装基板にこのような大きさの挿入孔を多数
穿孔した場合には、実装基板上の配線の引き回し面積が
制約されることとなり、たとえ半導体装置側で高集積化
が図れたとしても、対応する実装基板側で配線が困難な
ために高密度実装が実現できなくなる場合もある。However, if a large number of insertion holes of this size are drilled in the mounting board, the wiring area on the mounting board will be restricted, and even if high integration can be achieved on the semiconductor device side, In some cases, high-density packaging cannot be realized because wiring is difficult on the corresponding mounting board side.
また、上記の実装技術では、実装基板の挿入孔の周囲に
電極を形成して半田付けを行うため、リードと電極との
接触面積が小さく、良好な電気特性が得られない場合が
ある。Furthermore, in the above-mentioned mounting technique, since electrodes are formed around the insertion holes of the mounting board and soldered, the contact area between the leads and the electrodes is small, and good electrical characteristics may not be obtained.
本発明は、上記問題点に着目してなされたものであり、
その目的は高密度実装が可能でかつ実装信頼性の高い半
導体装置を提供することにある。The present invention has been made focusing on the above problems,
The purpose is to provide a semiconductor device that can be mounted at high density and has high mounting reliability.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、立設実装形半導体装置であって、パッケージ
から突出されるリードを実装基板の電極に対して面接触
状態で接合固定するものである。That is, the semiconductor device is an upright mounting type semiconductor device in which the leads protruding from the package are bonded and fixed to the electrodes of the mounting board in surface contact.
上記した手段によれば、実装基板の挿通孔を小さくある
いは皆無にすることができるため、実装基板上の配線の
自由度を確保でき、高密度実装が可能となる。また、リ
ードと電極とが面接触状態で実装されるため、電気的信
頼性および実装強度を確保できる。According to the above-mentioned means, the insertion hole of the mounting board can be made small or completely eliminated, so that the degree of freedom of wiring on the mounting board can be ensured, and high-density mounting is possible. Furthermore, since the leads and electrodes are mounted in surface contact, electrical reliability and mounting strength can be ensured.
〔実施例１〕
第１図は本発明の一実施例である半導体装置を実装状、
態で示す斜視図、第２図はこの半導体装置の実装状態を
示す断面図、第３図はこの半導体装置のパッケージ本体
内部を示す説明図である。[Embodiment 1] FIG. 1 shows a semiconductor device according to an embodiment of the present invention in a packaged state.
FIG. 2 is a cross-sectional view showing the mounted state of this semiconductor device, and FIG. 3 is an explanatory view showing the inside of the package body of this semiconductor device.
本実施例１の半導体装置ｌは、エポキシ樹脂等の合成樹
脂でモールド成形されたパッケージ本体２と、該パッケ
ージ本体２の一端面から突出された複数の外部リード３
とを有している。The semiconductor device 1 of the first embodiment includes a package body 2 molded with synthetic resin such as epoxy resin, and a plurality of external leads 3 protruding from one end surface of the package body 2.
It has
パッケージ本体２の内部のほぼ中央においては、第２図
および第３図に示すように、上記外部り−ド３と連設さ
れた内部リード４上にたとえばポリイミド樹脂等の絶縁
板５が図示しない接着剤等の接合手段により取付けられ
ており、該絶縁板５の表面には半導体ベレット６が取付
けられている。At approximately the center of the inside of the package body 2, as shown in FIGS. 2 and 3, an insulating plate 5 made of polyimide resin or the like (not shown) is placed on an internal lead 4 connected to the external lead 3. It is attached by bonding means such as adhesive, and a semiconductor pellet 6 is attached to the surface of the insulating plate 5.
このように、本実施例１の半導体装置１はいわゆるタブ
レス方式により半導体ベレット６が装着されているもの
であり、内部リード４はたとえば第３図に示すように、
その一部が半導体ベレット６の下方に入り込むようにし
て延設形成され、絶縁板５および半導体ベレット６を支
持する構過となっている。As described above, the semiconductor device 1 of the first embodiment is equipped with the semiconductor bullet 6 using the so-called tableless method, and the internal leads 4 are, for example, as shown in FIG.
A part of the semiconductor pellet 6 is extended so as to enter below the semiconductor pellet 6, and is configured to support the insulating plate 5 and the semiconductor pellet 6.
半導体ベレット６０表面にはアルミニウム（Ａ４２）等
で形成されたパッド７が設けられており、このバッド７
と上記内部リード４とは金等からなる導電性のワイヤ８
がループ状に接続されており、これにより半導体ベレッ
ト６と内部リード４および外部リード３との電気的導通
が行われている。A pad 7 made of aluminum (A42) or the like is provided on the surface of the semiconductor pellet 60.
The internal lead 4 is a conductive wire 8 made of gold or the like.
are connected in a loop, thereby establishing electrical continuity between the semiconductor pellet 6, the internal lead 4, and the external lead 3.
外部リード３は、たとえば第１図に示すように、パンケ
ージ本体２より突出されて該パッケージ本体２の立設延
長方向に沿って延設され、さらにその途中部分からこの
パッケージ本体２の立設方向に対して垂直方向に折曲成
形されているものである。ここで本実施例１では外部リ
ード３の先端は隣合う外部リード３同士が互いに反対方
向となるように、すなわち１本おきの外部リード３が同
方向となるように折曲されている。For example, as shown in FIG. 1, the external lead 3 protrudes from the pan cage body 2 and extends along the vertical extension direction of the package body 2, and further extends in the vertical direction of the package body 2 from an intermediate portion thereof. It is bent in a direction perpendicular to the In the first embodiment, the tips of the external leads 3 are bent so that adjacent external leads 3 are in opposite directions, that is, every other external lead 3 is bent in the same direction.
上記構造の半導体装置１は、たとえばまず所定のリード
フレーム（図示せず）を用意して、このリードフレーム
上の内部リード４を構成する所定位置に絶縁板５を取付
け、さらにこの絶縁板５の上に半導体ペレット６を接合
する。次に、半導体ペレット６のバッド７と内部リード
４とをワイヤボンディング法によりワイヤ８で接続した
後に、金型等で樹脂モールドによりパッケージ本体２を
形成し、さらに外１ｆｆｌ’Ｊ−ド３を上記の所定形状
に切断・成形して製造されるものである。In the semiconductor device 1 having the above structure, for example, a predetermined lead frame (not shown) is first prepared, an insulating plate 5 is attached to a predetermined position constituting the internal lead 4 on this lead frame, and then the insulating plate 5 is A semiconductor pellet 6 is bonded on top. Next, after connecting the pad 7 of the semiconductor pellet 6 and the internal lead 4 with the wire 8 by the wire bonding method, the package body 2 is formed by resin molding using a metal mold, etc., and the outer 1ffl'J-de 3 is then It is manufactured by cutting and molding into a predetermined shape.
この半導体装置１の実装基板９への装着は、たとえば以
下のようにして行われる。The mounting of the semiconductor device 1 onto the mounting board 9 is performed, for example, as follows.
まず、第２図に示すように裏面側に所定のプリント配線
１１の施された実装基板９が用意される。First, as shown in FIG. 2, a mounting board 9 having a predetermined printed wiring 11 on its back side is prepared.
ここでこの実装基板９について説明すると、実装基板９
の表面側すなわち半導体装置１の実装面側の所定位置に
は第１図に示すように、所定のプリント配線１２および
電極１３が形成されており、この電極１３から連設され
るプリント配線１２と裏面側のプリント配線１１とは実
装基板９０所定位置に設けられた貫通孔１４を経て半田
等によって電気的に接続されている。To explain the mounting board 9 here, the mounting board 9
As shown in FIG. 1, a predetermined printed wiring 12 and an electrode 13 are formed at a predetermined position on the surface side of the semiconductor device 1, that is, on the mounting surface side of the semiconductor device 1. It is electrically connected to the printed wiring 11 on the back side by solder or the like through a through hole 14 provided at a predetermined position on the mounting board 90.
ここで、本実施例１では上記貫通孔１４は実装基板９の
表裏面の導通を行うためのみに用いられるものである。Here, in the first embodiment, the through hole 14 is used only to provide electrical continuity between the front and back surfaces of the mounting board 9.
したがって、この貫通孔１４の直径はたとえば０．３
ｍｍ程度のもので十分である。したがって、実装基板９
の表裏面側に形成されるプリント配線１１．１２の引き
回しが複雑になったとしても、この貫通孔１４がプリン
ト配線１１あるいは１２の引き回しの障害となることが
なく、配線の自由度を向上させることができる。Therefore, the diameter of this through hole 14 is, for example, 0.3
A diameter of about mm is sufficient. Therefore, the mounting board 9
Even if the routing of the printed wiring 11 and 12 formed on the front and back sides of the board becomes complicated, the through hole 14 will not become an obstacle to the routing of the printed wiring 11 or 12, improving the degree of freedom in wiring. be able to.
次に、上記実装基板９の電極１３の部分にそれぞれ対応
する半導体装置１の番外Ｂ ＋Ｊ−ド３の先端部分のリ
ード面を当接した状態で載置しリフロー工程に移送する
。リフロー工程で所定の加熱が行われると、予め実装基
板９の電極１３の表面に被着されていた半田（図示せず
）が溶融して外部リード３と電極１３との接合が行われ
、この半田が冷却硬化されると半導体装置１の実装基板
９への実装が完了する。Next, the semiconductor device 1 is placed with the lead surfaces of the tips of the outer B+J- boards 3 corresponding to the electrodes 13 of the mounting board 9 in contact with each other, and transferred to a reflow process. When predetermined heating is performed in the reflow process, the solder (not shown) previously applied to the surface of the electrode 13 of the mounting board 9 is melted and the external lead 3 and the electrode 13 are bonded. When the solder is cooled and hardened, mounting of the semiconductor device 1 onto the mounting board 9 is completed.
このように、本実施例１によれば以下の効果を得ること
ができる。As described above, according to the first embodiment, the following effects can be obtained.
（１）、パッケージ本体２より突出された外部リード３
をその先端のリード面で実装基板９の電極１３に接合す
る半導体装置１のａ造とすることにより、実装基板９の
側に設けられる貫通孔１４を実装基板９の表裏面のプリ
ント配線１１．１２の導通を行うためのみに使用できる
ため、貫通孔１４の径を小径とすることが可能となり、
実装基板９の表裏面のプリント配線１１または１２の引
き回しの自由度を向上させることができる。(1) External leads 3 protruding from the package body 2
By forming the semiconductor device 1 into an a structure in which the leading end surface of the semiconductor device 1 is bonded to the electrode 13 of the mounting board 9, the through hole 14 provided on the mounting board 9 side is connected to the printed wiring 11. on the front and back surfaces of the mounting board 9. Since it can be used only to conduct the through hole 12, it is possible to make the diameter of the through hole 14 small.
The degree of freedom in routing the printed wiring 11 or 12 on the front and back surfaces of the mounting board 9 can be improved.
（２）、上記（１）により、高密度実装の可能な半導体
装置ｌを提供することができる。(2) According to (1) above, it is possible to provide a semiconductor device l that can be mounted at high density.
（３）、上記（１）により、実装基板９の電極１３と外
部リード３とが面接触状態で導通されるため、半導体装
置１の実装状態における電気的信頼性を高めることがで
きる。(3) According to (1) above, the electrodes 13 of the mounting board 9 and the external leads 3 are electrically connected in a surface contact state, so that the electrical reliability of the semiconductor device 1 in the mounted state can be improved.
（４）、パッケージ本体２より突出された外部リード３
を隣合う外部リード３とは反対方向に折曲することによ
り、各外部リード３の間隔を狭めることが可能となり、
半導体装置１の小形化を図ることができる。(4) External leads 3 protruding from the package body 2
By bending the external leads 3 in the opposite direction to the adjacent external leads 3, it is possible to narrow the distance between the external leads 3.
The semiconductor device 1 can be made smaller.
（５）、上記（４）により、半導体装置１の実装状態を
安定させることができ、実装信頼性を高めることができ
る。(5) According to (4) above, the mounting state of the semiconductor device 1 can be stabilized, and the mounting reliability can be improved.
〔実施例２〕
第４図は本発明の他の実施例である単導体装置を実装状
態で示す断面図である。[Embodiment 2] FIG. 4 is a sectional view showing a single conductor device according to another embodiment of the present invention in a mounted state.
本実施例２の半導体装置２１は、実施例１で説馴した半
導体装置１とほぼ同様の構造を有するものであるが、外
ＲＩＪ−ド２３の折曲形状のみが異なるものである。The semiconductor device 21 of the second embodiment has almost the same structure as the semiconductor device 1 described in the first embodiment, but differs only in the bent shape of the outer RIJ-domain 23.
すなわち、本実施例２ては、パンケージ本体２より突出
された外部リード２３は、その突出部よりパンケージ本
体２３の立設延長方向に対して−旦所定の角度θで折曲
され、さらにその途中部分でパッケージ本体２の立設延
長方向に対して垂直となるように折曲成形されている。That is, in the second embodiment, the external lead 23 protruding from the pan cage main body 2 is first bent at a predetermined angle θ from its protruding portion with respect to the vertical extension direction of the pan cage main body 23, and then The package body 2 is bent and formed perpendicularly to the direction in which the package main body 2 extends.
したがって、本実施例２の半導体装置２１を実装状態で
パッケージ本体２の側面方向からみた場合には、第４図
に示すように外部リード２３は実装基板９に対して開脚
されて取付けられた状態となり、実装基板９上において
各電極１３を互いに離した位置に設けることができる。Therefore, when the semiconductor device 21 of the second embodiment is viewed from the side surface of the package body 2 in a mounted state, the external leads 23 are attached to the mounting board 9 with their legs spread apart, as shown in FIG. In this state, the electrodes 13 can be provided at positions separated from each other on the mounting board 9.
このため、実装基板９上に半導体装置２１を実装した場
合に各電極１３間で半田ブリッヂ等（図示せず）が形成
され電気的短絡を生じることを防止でき、半導体装置２
１の実装における電気的信頼性をさらに向上させること
ができる。Therefore, when the semiconductor device 21 is mounted on the mounting board 9, it is possible to prevent a solder bridge or the like (not shown) from being formed between each electrode 13 and cause an electrical short circuit.
The electrical reliability in the implementation of No. 1 can be further improved.
また、外部リード２３の途中部分が第４図に示すように
、開脚状態で実装されているため、強度的に安定した立
設実装状態を維持することができる。Further, since the intermediate portion of the external lead 23 is mounted in an open state as shown in FIG. 4, it is possible to maintain a stable upright mounted state in terms of strength.
〔実施例３〕
第５図は本発明の他の実施例である半導体装置の実装状
態を示す断面図である。[Embodiment 3] FIG. 5 is a sectional view showing a mounted state of a semiconductor device according to another embodiment of the present invention.
本実施例３の半導体装置３１は、パッケージ本体２から
突出された外部リード３３が一部パッケージ本体２のリ
ード突出面に沿って折曲された後、所定部分でパッケー
ジ本体２の一側面側に略Ｊ字状に弯曲成形されたもので
ある。In the semiconductor device 31 of the third embodiment, the external leads 33 protruding from the package body 2 are partially bent along the lead protruding surface of the package body 2, and then bent at a predetermined portion on one side of the package body 2. It is curved into a roughly J-shape.
このように、本実施例３よれば、従来のＰＬＣＣ（プラ
スチックリーデツドチップキャリア）形の半導体装置の
パッケージ構造を大きく変更することなく、立設実装形
の高密度実装の可能な半導体装置３１を得ることができ
る。As described above, according to the third embodiment, the semiconductor device 31 that can be mounted vertically and with high density can be manufactured without significantly changing the package structure of the conventional PLCC (plastic leaded chip carrier) type semiconductor device. Obtainable.
〔実施例４〕
第６図は本発明の他の実施例である半導体装置の実装状
態を示す斜視図である。[Embodiment 4] FIG. 6 is a perspective view showing a mounted state of a semiconductor device according to another embodiment of the present invention.
本実施例４０半導体装置４１は、腹数の単体のリードレ
スチップキャリア形（ＬＣＣ）の半導体装置４２ａ、４
２ｂ、４２ｃ （以下ｒＬＣＣ４２ａ、４２ｂ、４２Ｃ
Ｊという）を装着した状態の基板４３が一つの七ジ二−
ルとして半導体装置４１を形成している、いわゆる集合
形半導体装置であり、各単体のＬＣＣ４２ａ、４２ｂ、
４２ｃは基板４３上の図示しないプリント配線により互
いに電気的に導通され、これらのプリント配線は、さら
に基板４３の一部より突出されるリード４４と電気的に
接続されている。Embodiment 40 The semiconductor device 41 is a single leadless chip carrier type (LCC) semiconductor device 42a, 4
2b, 42c (hereinafter referred to as rLCC42a, 42b, 42C
The board 43 with attached
This is a so-called collective semiconductor device in which the semiconductor device 41 is formed as a single LCC 42a, 42b,
42c are electrically connected to each other by printed wiring (not shown) on the substrate 43, and these printed wiring are further electrically connected to a lead 44 protruding from a part of the substrate 43.
ここで、本実施例４ではリード４４は基板４３の側面方
向からみてＬ字状に折曲成形されており、実装基板の電
極（第６図では図示せず）に対してリード４３の先端の
リード面を当接する状態で実装される。In the fourth embodiment, the leads 44 are bent into an L shape when viewed from the side surface of the board 43, and the tips of the leads 43 are bent against the electrodes (not shown in FIG. 6) of the mounting board. Mounted with the lead surfaces in contact.
このように、本実施例４によれば集合形半導体装置にお
いても実装基板に対してリード面による面付実装を行う
ことができるため、上述の実施例１および実施例２と同
様に、実装基板の配線の自由度を増すことができ、その
結果実装密度を向上させることが可能となる。In this way, according to the fourth embodiment, even in the aggregated semiconductor device, surface mounting can be performed on the mounting board using the lead surface. The degree of freedom in wiring can be increased, and as a result, the packaging density can be improved.
以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。たとえば、実施例４では
単体のＬＣＣ４２ａ。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the fourth embodiment, a single LCC 42a is used.
４２ｂ、４２ｃを基板４３に装着した半導体装置４１に
ついて説明したが、このようなＬＣＣ以外にＰＬＣＣ等
の他の単体の半導体装置、さらにはペレットを装着した
ものであってもよい。Although the semiconductor device 41 in which 42b and 42c are mounted on the substrate 43 has been described, in addition to such an LCC, other single semiconductor devices such as a PLCC, or even a semiconductor device in which a pellet is mounted may be used.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記の通りである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、パッケージ本体のリード突出面を実装基板面
に対向させるようにして立設実装され、該リードと実装
基板上の電極とが面接触状態で接合固定される立設実装
形半導体装置構造とすることにより、実装基板の挿通孔
を小さくあるいは皆無にすることができるため、実装基
板上の配線の自由度を確保でき、高密度実装が可能とな
る。また、リードと電極とが面接触状態で実装されるた
め、電気的信頼性および実装強度を確保できる。That is, the semiconductor device is mounted upright with the protruding lead surface of the package body facing the surface of the mounting board, and the leads and electrodes on the mounting board are bonded and fixed in surface contact. As a result, the insertion hole in the mounting board can be made small or completely eliminated, so that the degree of freedom in wiring on the mounting board can be ensured, and high-density mounting is possible. Furthermore, since the leads and electrodes are mounted in surface contact, electrical reliability and mounting strength can be ensured.
第１図は本発明の実施例１である半導体装置を実装状態
で示す斜視図、
第２図は実施例１の半導体装置の実装状態を示す断面図
、
第３図は実施例１の半導体装置のパッケージ本体内部を
示す説明図、
第４図は本発明の実施例２である半導体装ｌを示す断面
図、
第５図は本発明の実施例３である半導体装置の実装状態
を示す断面図、
第６図は本発明の実施例４である半導体装置の実装状態
を示す斜視図である。
１・・・半導体装置、２・・・パッケージ本体３ ・
・ ・外部リード、４ ・ ・ ・内部リード、５ ・
・・絶縁板、６・・・半導体ベレット、７・・・バンド
、８・・・ワイヤ、９・・・実装基板、１１．１２・・
・プリント配線、１３・・・電極、１４・・・貫通孔、
２１・・・半導体装置、２３・・・外部リード、３１・
・・半導体装置、３３・・・外部リード、４１・・・半
導体装置、４２ａ、４２ｂ、４２Ｃ−−・半導体装置単
体（ＬＣＣ）、４３ ・ ・ ・基板、４４ ・ ・
・ リード。
第 ４ 図
第５図
第 ６ 図FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention in a mounted state, FIG. 2 is a sectional view showing a semiconductor device according to a first embodiment in a mounted state, and FIG. 3 is a semiconductor device according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a semiconductor device I according to a second embodiment of the present invention, and FIG. 5 is a cross-sectional view showing the mounting state of a semiconductor device according to a third embodiment of the present invention. , FIG. 6 is a perspective view showing a mounted state of a semiconductor device according to a fourth embodiment of the present invention. 1... Semiconductor device, 2... Package body 3 ・
・ ・External lead, 4 ・ ・ ・Internal lead, 5 ・
... Insulating plate, 6... Semiconductor pellet, 7... Band, 8... Wire, 9... Mounting board, 11.12...
・Printed wiring, 13...electrode, 14...through hole,
21... Semiconductor device, 23... External lead, 31.
...Semiconductor device, 33...External lead, 41...Semiconductor device, 42a, 42b, 42C--Semiconductor device (LCC), 43...Substrate, 44...
・Lead. Figure 4 Figure 5 Figure 6
Claims (1)
させるようにして立設実装され、該リードが実装基板上
の電極と面接触するように折曲成形されていることを特
徴とする立設実装形半導体装置。 ２、パッケージより突出されたリードがパッケージの裏
面方向にＪ字状に折曲されていることを特徴とする特許
請求の範囲第１項記載の立設実装形半導体装置。 ３、パッケージが配線基板であり、かつこの配線基板上
に二以上の単体の半導体装置またはペレットを装着して
なることを特徴とする特許請求の範囲第１項記載の立設
実装形半導体装置。 ４、パッケージ本体より突出されたリードがその途中部
分でパッケージの立設方向に対して垂直方向でかつリー
ド先端が互いに隣合うリードと反対方向となるように折
曲成形されていることを特徴とする特許請求の範囲第１
項記載の立設実装形半導体装置。 ５、パッケージ内に封止される半導体ペレットがパッケ
ージ内のリードの表面に装着された樹脂基板上に取付け
られ、該リードとペレットのパッドとがワイヤボンディ
ングにより電気的に導通されていることを特徴とする特
許請求の範囲第１項、第２項または第４項記載の立設実
装形半導体装置。[Scope of Claims] 1. The package body is mounted vertically with the protruding surface of the leads facing the surface of the mounting board, and the leads are bent so as to make surface contact with the electrodes on the mounting board. An upright mounting semiconductor device characterized by: 2. The vertically mounted semiconductor device according to claim 1, wherein the leads protruding from the package are bent in a J-shape toward the back surface of the package. 3. The vertically mounted semiconductor device according to claim 1, wherein the package is a wiring board, and two or more single semiconductor devices or pellets are mounted on the wiring board. 4. The leads protruding from the package main body are bent at their midpoints in a direction perpendicular to the direction in which the package is erected, and the lead tips are in the opposite direction to the adjacent leads. Claim 1
2. The vertically mounted semiconductor device described in 2. 5. The semiconductor pellet sealed in the package is attached to a resin substrate attached to the surface of the lead in the package, and the lead and the pad of the pellet are electrically connected by wire bonding. An upright mounting type semiconductor device according to claim 1, 2, or 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223581A JPH0821668B2 (en) | 1986-09-24 | 1986-09-24 | Vertically mounted semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61223581A JPH0821668B2 (en) | 1986-09-24 | 1986-09-24 | Vertically mounted semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6379361A true JPS6379361A (en) | 1988-04-09 |
| JPH0821668B2 JPH0821668B2 (en) | 1996-03-04 |
Family
ID=16800407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61223581A Expired - Fee Related JPH0821668B2 (en) | 1986-09-24 | 1986-09-24 | Vertically mounted semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0821668B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH038363A (en) * | 1989-06-05 | 1991-01-16 | Hitachi Ltd | Resin sealed type semiconductor device |
| JPH05160298A (en) * | 1991-07-10 | 1993-06-25 | Mitsubishi Electric Corp | Surface mounting type package |
| US5413970A (en) * | 1993-10-08 | 1995-05-09 | Texas Instruments Incorporated | Process for manufacturing a semiconductor package having two rows of interdigitated leads |
| JP2015060882A (en) * | 2013-09-17 | 2015-03-30 | 株式会社デンソー | Method for manufacturing electronic element and method for manufacturing electronic component including the electronic element |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4992960B2 (en) | 2009-12-07 | 2012-08-08 | 株式会社村田製作所 | High frequency module |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125848U (en) * | 1977-03-16 | 1978-10-06 | ||
| JPS57128171U (en) * | 1981-02-02 | 1982-08-10 | ||
| JPS58184849U (en) * | 1982-06-01 | 1983-12-08 | 日本電気株式会社 | semiconductor equipment |
| JPS6142855U (en) * | 1984-08-22 | 1986-03-19 | 日本電気株式会社 | semiconductor equipment |
| JPS61111155U (en) * | 1984-05-31 | 1986-07-14 |
-
1986
- 1986-09-24 JP JP61223581A patent/JPH0821668B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53125848U (en) * | 1977-03-16 | 1978-10-06 | ||
| JPS57128171U (en) * | 1981-02-02 | 1982-08-10 | ||
| JPS58184849U (en) * | 1982-06-01 | 1983-12-08 | 日本電気株式会社 | semiconductor equipment |
| JPS61111155U (en) * | 1984-05-31 | 1986-07-14 | ||
| JPS6142855U (en) * | 1984-08-22 | 1986-03-19 | 日本電気株式会社 | semiconductor equipment |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH038363A (en) * | 1989-06-05 | 1991-01-16 | Hitachi Ltd | Resin sealed type semiconductor device |
| JPH05160298A (en) * | 1991-07-10 | 1993-06-25 | Mitsubishi Electric Corp | Surface mounting type package |
| JP2862437B2 (en) * | 1991-07-10 | 1999-03-03 | 三菱電機株式会社 | Surface mount type package |
| US5413970A (en) * | 1993-10-08 | 1995-05-09 | Texas Instruments Incorporated | Process for manufacturing a semiconductor package having two rows of interdigitated leads |
| JP2015060882A (en) * | 2013-09-17 | 2015-03-30 | 株式会社デンソー | Method for manufacturing electronic element and method for manufacturing electronic component including the electronic element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0821668B2 (en) | 1996-03-04 |
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