JPH04280667A - High integrated semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high integrated semiconductor device which is hardly enlarged in size even if semiconductor chips are increased in number by a method wherein wiring boards are arranged nearly in parallel at prescribed intervals, which are assembled into a multiboard structure with a single lead wire. CONSTITUTION:A chip 1 is mounted on a wiring board 2 through the intermediary of adhesive agent or the like, a wiring pattern 3 is provided onto the upside of the board 2, and the front and the rear of the board 2 are electrically connected together to constitute a rigid wiring board. For instance, the rear and the front of a printed board are electrically connected together through a through-hole wiring 4, and the through-hole wirings 4 are connected to the terminals provided onto the chip 1 through a wiring pattern 3 and a bonding wire 5 of the board 2. Solderable lands 4A are formed around the through-hole wirings 4 provided to the front and the rear of the board 2, a solder guide line 4B formed of the same material with the wiring is provided extending from a part near the end of the board 2 to the land 4A, a lead wire 7 and the land 4A are surely soldered to each other even if the gap is narrow.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a highly integrated semiconductor device composed of a plurality of semiconductor chips used in memory cards, memory modules, hybrid ICs, VTRs, television cameras, etc. The present invention relates to a technology for assembling wiring boards substantially parallel to each other to form a laminated structure and electrically connecting them.

0002

[Prior Art] A conventional device with a three-dimensional circuit configuration based on a laminated structure is the Nikkei Micro Device ('88
As described in the September and November issue, P15, published by Nikkei BP, TAB (Tape Aoutmated Bon
Adjacent leads are electrically connected using the outer leads of the ding.

For example, when stacking memory chips, the outer leads of the TAB are bent vertically, stacked as many as the required number of chips, and then the overlapping outer leads are electrically connected to each other using a solder material or the like. conduct. Thereafter, the connected outer leads are bent horizontally to form a gull wing shape.

Furthermore, since the chip select terminals of the memory chips must be electrically independent for each chip, it is necessary to cut off unnecessary outer lead portions of the TAB before stacking the TAB, or to remove the outer leads from the TAB. It is necessary to disconnect the leads after connecting them with solder or the like.

Furthermore, as described in the publication ``Hybrid Integrated Circuits'' (published by Kogyo Kenkyukai in June 1968), metal balls are interposed between the electrode terminals of the bare chip and the electrode terminals of the wiring board. There is flip-chip mounting in which electrodes on a bare chip and electrode terminals on a substrate are electrically connected using a solder material or the like.

[0006] Furthermore, when mounting electronic components assembled on printed boards three-dimensionally, a plurality of printed boards are arranged almost parallel to each other at a predetermined interval (5 mm to 1 cm), and each printed board is Electrical and mechanical connections are made by passing lead wires through the board and soldering the lead wires to each printed board.

[0007]

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, in the case of flip-chip mounting, it is not possible to attach an electrode connected to the back surface and the front surface of the chip, so a laminated structure cannot be formed, and conduction between the front and back surfaces cannot be established. In order to do this, it was necessary to attach some kind of relay point. A laminated TAB was devised for this purpose, and the outer lead of the TAB corresponds to this relay point.

However, in a laminated TAB, the upper and lower T
There is a gap between AB that corresponds to the thickness of the chip,
In order to fill this gap, it is necessary to bend and mold the outer lead, but when doing so, the outer lead has the drawbacks of being extremely thin, making it difficult to achieve molding precision, and having low strength. Therefore, there was a problem in that the connection part easily came off when assembled to the motherboard.

Furthermore, since the outer leads can only be taken out around the chip, the number of connection pins is limited, and if there are pins that do not need to be electrically connected, the outer leads must be cut. there were.

[0010] Furthermore, when electronic components are assembled three-dimensionally on the conventional printed board, the parts mounted on the printed board become thinner, and the thickness of the printed board laminate becomes thinner. It has become thinner and smaller,
In addition, the solder does not fit well with the printed board (material: glass epoxy, phenol, etc.) (due to the surface tension of the solder), making it difficult for the solder to fit into narrow gaps.

The present invention has been made to solve the above problems, and its object is to provide a technique for obtaining a highly integrated semiconductor device that does not become larger in plan view even when the number of semiconductor chips is increased. There is a particular thing.

Another object of the present invention is to improve the reliability of electrical connections between wiring boards in a semiconductor device having a stacked structure in which a plurality of wiring boards each carrying a semiconductor chip are stacked on top of each other. The goal is to provide technology.

Another object of the present invention is to provide a technique that enables electrical connection between wiring boards using inexpensive parts without bending or cutting the outer leads.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0015]

[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.

(1) A plurality of wiring boards on which semiconductor chips are mounted are arranged approximately parallel to each other at predetermined intervals, and these are assembled into a laminated structure with at least one lead wire penetrating each wiring board, and the leads This is a highly integrated semiconductor device in which wires and electrode terminals on each of the wiring boards are electrically connected by soldering.

(2) Solder guide wires connected to electrode terminals provided on the wiring boards are arranged closer to the end faces than the distance from which solder can penetrate from the end faces of each of the wiring boards.

(3) A taper is provided at the end of each wiring board on the opposing surface side.

[0019]

[Operation] According to the above-mentioned means, the following operation and effect can be achieved.

[0020] Here, the wiring board on which the bare chip is mounted is regarded as a new enlarged chip. Through holes provide terminals with the same potential on the front and back sides of the wiring board, and by bonding the bare chip onto this board, electrode terminals are now available on both sides of the chip, whereas bare chips only had electrode terminals on the front side. The state is the same as when the electrode terminal was formed. As a result, the electrodes of the laminated substrates face each other, so that the facing terminals can be connected to each other by a connecting means such as soldering.

However, there are chips and
There are protrusions made of wires and materials to protect them, and there is a gap between the wiring boards when they are stacked. In order to fill this gap, it is necessary to interpose a conductive substance. In the present invention, a lead wire is used as the conductive material, the lead wire is passed through the through hole of the wiring board, and the lead wire and each wiring board are electrically and mechanically connected with solder.

[0022] Furthermore, if the conductive object is misaligned and misaligned, it will result in poor continuity or short-circuiting, so in the present invention, the lead wire is passed through the through hole in order to prevent misalignment from occurring. .

Furthermore, since the solder guide wires connected to the electrode terminals provided on the wiring boards are placed closer to the end faces than the distance at which solder can penetrate from the end faces of each of the wiring boards, the lead wires and the wiring boards are connected to each other. It can be easily soldered to the upper wiring terminal.

Furthermore, by providing a taper at the end of the opposing surface between the wiring boards, the surface tension of the solder is reduced, so that the solder fits better, and the solder fills the gaps between the wiring boards. It becomes easier to enter.

[0025] By doing this, the wiring boards and the lead wires in the laminated structure of a plurality of wiring boards are fixed to each other by solder, so that positional deviation does not occur, and the electrical connection is good and the mechanical connection is good. It has a structure that is resistant to impact.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiment 1] FIG. 1 is a cross-sectional view showing the overall schematic configuration of a highly integrated semiconductor device according to an embodiment in which the present invention is applied to a wiring board mounted with an SRAM memory chip, and FIG.
FIG. 3 is a cross-sectional view showing a schematic configuration of one wiring board on which the SRAM memory chip of FIG. 1 is mounted, and FIG.
(A) It is a sectional view cut along the line.

As shown in FIGS. 1, 2 and 3, semiconductor devices 100A, 100B, 100C, 10 of this embodiment
In each 0D, a 256 kbit SRAM memory chip (hereinafter simply referred to as a chip) 1 is mounted on a wiring board (hereinafter simply referred to as a board) 2 via an adhesive or the like.

The substrate 2 is a rigid wiring board with a wiring pattern 3 provided on its upper surface (front surface), and the front and back surfaces of the substrate 2 are electrically connected by through-hole wiring 4. For example, it is a printed circuit board whose front and back surfaces are electrically connected by through-hole wiring 4, and each through-hole wiring 4 is electrically connected to a terminal on a chip 1 by a wiring pattern 3 of the board 2 and a bonding wire 5. ing.

[0031] Solderable lands 4A are formed on the front and back surfaces of the periphery of the through-hole wiring 4. In this land 4A, as shown in FIG. 5(a),
In order to make it easier for the solder 8 to penetrate from the end surface of the substrate 2,
A solder guide wire 4B made of the same material as the wiring is arranged from near the end surface of the substrate 2 to the land 4A. By doing this, the solder 8 is guided to the land 4 by the solder guide wire 4B from a position where it easily enters from the end surface of the board 2, so even if the space between the boards 2 is narrow, the lead wire 7 and the land 4A can be securely connected. Can be soldered.

Note that the wiring pattern 3, through-hole wiring 4, land 4A, and solder guide wire 4B may be formed individually on the substrate 2, or may be formed integrally. Also,
The wiring pattern 3, through-hole wiring 4, and land 4A are electrically connected to each other. Moreover, the solder guide wire 4B does not need to be electrically connected to the land 4A, and only needs to have the function of guiding the solder 8 to the land 4A.

Further, as shown in FIG. 5(b), the ends of the lands 4A connected to the wiring pattern 3 provided on the board 2 are soldered by dipping the board 2 into a solder bath. When attaching, on the end of the opposing surface of each board 2,
A taper (diagonal notch) 2A may be provided to reduce the surface tension of the solder 8. By doing this, the surface tension of the solder 8 is reduced, so even if the space between the boards 2 becomes narrow, the solder will fit better, and the solder will enter the gap from the end surface of the board 2 to the end of the wiring pattern 3. It becomes easier.

In order to protect the chip 1 and the bonding wires 5, they are sealed by transfer molding with a sealing resin 6 such as resin. Further, the motherboard 10 is provided with through-hole wiring 11 provided at the same position as the through-hole wiring 4 formed at the end of each of the semiconductor devices.

The highly integrated semiconductor device 100 of this embodiment includes a plurality of substrates 2 on which the chips 1 are mounted, that is, semiconductor devices 100A, 100B, 100C, and 100D.
However, as shown in FIG. 3, a lead wire extension portion 7A, which is an extension of the lead wire 7, is inserted into a through hole of a through hole wiring 11 provided on the motherboard 10. This lead wire extension 7A and lands 11A provided on the front and back surfaces around the through-hole wiring 11 are electrically and mechanically connected by solder 8. Therefore, the address terminal, data terminal, and power supply terminal of chip 1 are commonly connected.

[0036] Furthermore, each semiconductor device 100A, 100B,
Chip select terminals for selecting each chip 1 of 100C and 100D are connected independently.

Next, the means for selecting chips 1A, 1B, 1C, and 1D will be explained.

6, FIG. 7, and FIG. 8 are explanatory views for explaining the structure of the chip select terminal section, FIG. 6 is an explanatory cross-sectional view, and FIGS. 7 and 8 are explanatory views of the wiring pattern 3 of each board 2. FIG. 3 is an explanatory diagram showing an example where all of the values are different.

For example, each semiconductor device 100A, 100B
, 100C, 100D chips respectively 1A, 1B
, 1C, and 1D, their selection is performed by the chip select terminal CS as shown in FIGS. 6, 7, and 8, respectively.
1, CS2, CS3, and CS4.

In FIG. 6, the first chip 1A from the top
is selected by the chip select terminal CS1. Similarly, the second chip 1B from the top has a chip select terminal CS.
2, the third chip 1C from the top is selected by the chip select terminal CS3, and the fourth chip 1D from the top is selected by the chip select terminal CS4.

As shown in FIG. 7, the chip select terminal CS1 is electrically connected to the chip select wiring pattern 9A of the first chip 1A from the top by a through-hole wiring 4, and the chip select wiring pattern 9A is a bonding wire. 5 is electrically connected to the chip 1A.

Similarly, the chip select terminal CS2 is electrically connected to the wiring terminal pattern 9B (not shown) of the second chip 1B from the top by the through-hole wiring 4, and the chip select wiring pattern 9B is connected to the bonding wire. 5, it is electrically connected to the chip 1B.

The chip select terminal CS3 is electrically connected to the chip select wiring pattern 9C (not shown) of the third chip 1C from the top by the through-hole wiring 4, and the chip select wiring pattern 9C is connected to the chip select wiring pattern 9C by the bonding wire 5. It is electrically connected to chip 1C.

As shown in FIG. 8, the chip select terminal CS4 is electrically connected to the wiring terminal pattern 9D of the fourth chip 1D from the top by the through-hole wiring 4, and the chip select wiring pattern 9D is connected to the wiring terminal pattern 9D by the bonding wire 5. It is electrically connected to chip 1D.

[0045] Also, each of the chips 1A, 1B, 1C, 1
The selection of D is based on the chip select wiring patterns 9A and 9B on each board 2, as shown in FIGS. , 9C, and 9D may be provided, and only the chip select wiring pattern for which each board 2 is selected may be wire-bonded.

Furthermore, as shown in FIG. 11 (explanatory cross-sectional view), FIG. 12 and FIG. 13 (chip select wiring pattern),
Chip select wiring pattern 9E common to each board 2
It is also possible to provide a short-circuit with the metal ball 12 or solder when the substrates 2 are stacked on top of each other.

Next, the highly integrated semiconductor device 100 of this embodiment
We will briefly explain how to assemble the .

As shown in FIG. 14, in the semiconductor devices 100A, 100B, 100C, and 100D of this embodiment, a chip 1 is mounted on the substrate 2 (a) with an adhesive or the like (b). Next, the terminals on the chip 1 and the wiring patterns 3 on the substrate 2 are electrically connected by bonding wires 5 (b). After that, in order to protect the chip 1 and the bonding wires 5, a sealing resin 6 such as resin is used.
It is sealed by transfer molding (c). As a result, each semiconductor device 100A, 100B, 100C, 1
00D is completed.

Next, the semiconductor devices 100A and 100B are stacked, and the lead wire 7 is inserted into the through hole of the through-hole wiring 4 in a skewered manner, so that the lead wire 7 protrudes long from the back surface of the semiconductor device 100B. In this state, it is dipped into a solder bath, and the lands 4A provided on the front and back surfaces around the through-hole wiring 4 are soldered to the lead wires 7 to electrically connect them (d).

Next, the long protruding lead wire 7 is inserted into the through hole of the through hole wiring 11 of the motherboard 10 (e). Solder paste is applied to this through hole in advance. In this state, the motherboard 10
By applying hot air (240 degrees Celsius) to melt the solder paste, the lands 11A provided on the front and back surfaces of the through-hole wiring 11 of the motherboard 10 and the lead wires 7 are soldered to electrically and mechanically. Connect to (f). Finally, the excess lead wire 7 is cut off to complete the assembly.

If there is a terminal that you do not want to electrically connect, it will not be electrically connected unless a soldering land is formed in that area.

As can be seen from the above description, according to this embodiment, the chips 1 are three-dimensionally interconnected via the substrate 2 to form a circuit network, so that even if the number of chips 1 is increased, Since it does not become large in plan, semiconductor elements can be mounted with high density. For example, 1MbitSR
A memory with the same functionality as AM memory capacity can be realized with almost the same package size, and a highly integrated circuit memory can be manufactured in a short period of time.

Further, the through hole 4 of the substrate 2 is provided with a through hole, so that the upper and lower substrates can be easily electrically connected to each other by the lead wire 7.

Furthermore, since the substrates 2 or the substrate 2 and the motherboard 10 are fixed by the lead wires 7, the highly integrated semiconductor device is difficult to misalign, is resistant to mechanical shock, and has highly reliable electrical connections. 100 is obtained.

Furthermore, since there is a lead wire 7 for connection,
Since there is no need to bend or deform the wiring part when connecting the boards, a stable shape with high precision can be obtained.

Furthermore, since the lead wire 7 for connection can be easily attached or removed, circuit formation can be facilitated.

[0057] Furthermore, if it is desired to mount the device on the motherboard 10 in two ways, upward mounting and downward mounting, it is sufficient to prepare only one type of component.

Although the present invention has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.

[0059]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) Since the semiconductor chips are three-dimensionally interconnected via the substrate to form a circuit network, a highly integrated semiconductor device that does not become larger in plan even if the number of semiconductor chips is increased. can get.

(2) Since the solder is guided from the end surface of the board to the land from a position where it is easy to enter, the lead wire and the land can be reliably soldered even if the distance between the boards is narrow.

(3) By providing a taper at the end of the facing surface between each board, the surface tension of the solder is reduced, so the solder blends better, and even in narrow gaps between each board. , solder easily enters the gap up to the end of the electrode terminal pattern.

According to (2) and (3) above, it is possible to obtain a highly integrated semiconductor device in which positional displacement between the substrates or between the substrates and the motherboard is difficult to occur, and which is resistant to mechanical shock and has highly reliable electrical connections. .

[Brief explanation of the drawing]

FIG. 1 is an external perspective view showing the overall schematic configuration of a highly integrated semiconductor device according to an embodiment in which the present invention is applied to a substrate on which an SRAM memory chip is mounted.

FIG. 2 is a cross-sectional view showing a schematic configuration of a board on which one SRAM memory chip shown in FIG. 1 is mounted.

FIG. 3 is a sectional view taken along line (A)-(A) shown in FIG. 1;

FIG. 4 is an enlarged view of the vicinity of a land on the substrate shown in FIG. 1;

FIG. 5 is a cross-sectional view for explaining the structure of the end portion of the substrate shown in FIG. 3;

FIG. 6 is an explanatory diagram for explaining the chip select means of this embodiment.

FIG. 7 is an explanatory diagram for explaining the chip selection means of this embodiment.

FIG. 8 is an explanatory diagram for explaining chip selection means of this embodiment.

FIG. 9 is an explanatory diagram for explaining a modification of the chip select means of this embodiment.

FIG. 10 is an explanatory diagram for explaining a modification of the chip select means of this embodiment.

FIG. 11 is an explanatory diagram for explaining another modification of the chip select means of this embodiment.

FIG. 12 is an explanatory diagram for explaining another modification of the chip select means of this embodiment.

FIG. 13 is an explanatory diagram for explaining another modification of the chip select means of this embodiment.

FIG. 14 is a diagram for explaining a method of assembling the highly integrated semiconductor device of this embodiment.

[Explanation of symbols]

1, 1A, 1B, 1C, 1D...chip, 2...substrate, 3...
Wiring pattern, 4, 11...Through hole wiring, 4A, 1
1A... Land, 4B... Solder guide wire, 5... Bonding wire, 6... Sealing resin, 7... Lead wire, 8... Solder, S
1, CS2, CS3, CS4...chip select terminal, 9
A, 9B, 9C, 9D...Chip select wiring pattern,
10...Motherboard, 100A, 100B, 100C,
100D...semiconductor device, 100...highly integrated semiconductor device.

Claims (3)

[Claims] 1. A plurality of wiring boards on which semiconductor chips are mounted are arranged substantially in parallel at predetermined intervals, and these are assembled into a laminated structure with at least one lead wire penetrating each wiring board, and the lead wire and electrode terminals on each of the wiring boards are electrically connected by soldering. 2. The highly integrated semiconductor device according to claim 1, wherein the solder guide wire is connected to an electrode terminal provided on the wiring board at a distance from the end surface of the wiring board that allows solder to penetrate into the end surface. A highly integrated semiconductor device characterized by the following: 3. The highly integrated semiconductor device according to claim 1, wherein each wiring board has a tapered end on the opposing surface side.