WO1998025305A1

WO1998025305A1 - Method for manufacturing semiconductor device

Info

Publication number: WO1998025305A1
Application number: PCT/JP1996/003547
Authority: WO
Inventors: Toshio Miyamoto; Asao Nishimura; Koki Noguchi; Satoshi Michishita; Masashi Horiguchi; Masaharu Kubo
Original assignee: Hitachi, Ltd.
Priority date: 1996-12-04
Filing date: 1996-12-04
Publication date: 1998-06-11
Also published as: JP4025372B2; TW326559B; AU1040197A

Abstract

A semiconductor process for a laminated package that contains a semiconductor chip on which at least a CPU and flash memory are formed and one or more semiconductor chips on which at least DRAMs are formed. The process comprises the steps of: patterning conductive layers formed on the tape carriers so that leads may protrude into device holes on one side and connected to the through holes in tape carriers on the other side; sealing the semiconductor chips with a resin after the leads are bonded to the terminals of the chips for electrical connections; stacking the tape carriers with their through holes aligned and filling conductor in the through holes for electrical connections; and forming external terminals connected with the through holes on one end.

Description

Specification

Manufacturing method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device in which a plurality of types of semiconductor chips are housed in a single package so that signals can be input and output from each other from an MCM (Multi Chip Module) approach. One package includes a micro computer including a Central Processing Unit, a programmable nonvolatile memory such as a flash memory, and a logic LSI such as a Dynamic Random Access Memory (DRA) and an Application Specific Integrated Circuit (ASIC). Technology that is effective when applied to the manufacture of semiconductor devices. Background art

The inventor of the present invention has been working on a semiconductor device related to a system-on-chip in order to realize a DRAM on single-inline memory module (SMM) approach and a microcomputer on a flash memory / DRAM with high customer needs. Rather than making all computers, flash memory, DRAM, ASIC, etc. all in one chip, a technology that accommodates multiple types of semiconductor chips in a single package from a MCM approach and enables signal input and output to and from each other. I was thinking about it. The following are the technologies studied by the inventor, and their outlines are as follows: In recent years, in advanced technology fields such as multimedia, information communication, etc .. Microcomputer, flash memory, DRAM, ASIC By forming such devices on a single chip, there is a growing movement to increase the data transfer speed, save space (improve packaging density), and reduce power consumption. However, if such a large variety of LSIs are to be formed on a single chip, the burden on the semiconductor manufacturing process becomes extremely large.

The reason will be described below based on the microcomputer, flash memory, DRAM, and ASIC mixed processes studied by the present inventors. The outline of this mixed loading process is as follows. First, as shown in FIG. 78, a p-type impurity (boron) is ion-implanted into the main surface of the semiconductor substrate 100 to form a p-type well 101, and then a field is formed on the surface of the p-type well 101 by the LOCOS method. An oxide film 102 is formed. The element formed at the left end of the figure is the MOS FET that constitutes the DRAM memory cell, and the element formed to the right is the M〇S FET that constitutes the memory cell of the flash memory and the peripheral circuits of the flash memory. The high-voltage M〇S FET that forms part of this element, and the element formed at the right end is the MOSFET that makes up a logic LSI such as a micro computer or AS IC. Note that an actual LSI is mainly composed of an n-channel MOS FET and a p-channel MOS FET, but for simplicity of description, only a region for forming an n-channel MOSFET is illustrated.

Next, as shown in FIG. 79, a tunnel oxide film 103 of the flash memory is formed. The thickness of the tunnel oxide film 103 is set to about 8 to 13.

Next, as shown in FIG. 80, a polycrystalline silicon film deposited by the CVD method is patterned on the semiconductor substrate 100 to form (part of) the floating gate 104 of the flash memory. As shown in FIG. 1, a second gate insulating film (ONO film) 105 having a thickness of about 10 to 30 nm formed by stacking a silicon oxide film, a silicon nitride film and a silicon oxide film is formed thereon.

Next, as shown in FIG. 82, a gate oxide film 106 of a high withstand voltage MOSFET is formed in the peripheral circuit region of the flash memory. The gate oxide film 106 is formed with a thickness (10 to 30 nm) larger than the gate oxide films of other MOS FETs in order to increase the breakdown voltage.

Next, as shown in FIG. 83, a gate oxide film 107 of the MOS FET forming the logic LSI and a gate oxide film 130 of the MOS FET forming the memory cell of the DRAM are formed. The thickness of the gate oxide film 107 is about 4 to 10 nm, and the thickness of the gate oxide film 130 is about 8 to 15 nm.

Next, as shown in FIG. 84, the polycrystalline silicon film deposited by the CVD method on the semiconductor substrate 100 is patterned to form a gate electrode (gate line) 108 of a DRAM memory cell. Flash memory controller gate 109, High voltage M〇 SFET gate electrode 110, MO SFET gate electrode 1 1 1 constituting logic LSI Then, the (partially formed) floating gate 104 of the flash memory is patterned to form the floating gate 104, as shown in FIG.

Next, as shown in FIG. 86, n-type impurities (phosphorus and arsenic) are ion-implanted into a part of the memory cell region of the flash memory to form an rT type semiconductor region 112 of the flash memory. As shown in Fig. 7, n-type impurities (phosphorus and arsenic) are ion-implanted into a part of the memory cell area of the flash memory, the peripheral circuit area, and the logic LSI formation area, and the n-type semiconductor area of the flash memory is removed. , 1 13, n-type semiconductor regions 1 13, 1 13 of the high-voltage MOS FET and n-type semiconductor regions 1 1 3, 1 1 3 of the M〇S FET constituting the logic LSI are formed simultaneously Next, as shown in Fig. 88, the gate electrode (word line) 108 of the DRAM memory cell, the control gate 109 of the flash memory, the gate electrode 110 of the high-voltage MOS FET, The gate voltage of the M〇 SFET that constitutes the logic LSI A side wall spacer 114 is formed on the side wall of the pole 111.

Next, as shown in FIG. 89, n-type impurities (phosphorous or arsenic) are implanted into a part of the memory cell area of the flash memory, the peripheral circuit area, and the logic LSI formation area, and the n ⁺ -Type semiconductor region 1 15, n-type semiconductor region 1 15, 1 15 of high voltage MOS FET, and n-type semiconductor region 1 15 1 1 5 of VIOSFET constituting logic LSI By forming one of the source and drain regions of the flash memory and the source and drain regions of the high-voltage MOS FET, the drain region and the M〇SFET that constitutes the logic LSI, the LDD (Lightly Doped Drain) ) Structure,

Next, as shown in FIG. 90, the silicon oxide film 116 deposited on the semiconductor substrate 100 by the CVD method is etched to form connection holes on both sides of the DRAM gate electrode (lead wire). forming a, after forming the n ^÷ type semiconductor region 1 1 2 of the upper connection hole of the flash memory, both sides of the gate electrode of the DRAM forming a plug 1 1 7 of the polycrystalline silicon film to內部these connecting holes Then, an _n- type semiconductor region 118 is formed by the impurity diffused from the polycrystalline silicon film. After that, the polycrystalline silicon film deposited by CVD on the silicon oxide film L and the bit line BL of the flash memory are formed.

Next, as shown in FIG. 91, after depositing a silicon oxide film 119 on the semiconductor substrate 100 by a CVD method, the polycrystalline silicon film deposited on the silicon oxide film 119 is patterned. The lower electrode 120 of the DRAM capacitor is formed.

Next, as shown in FIG. 92, the tantalum oxide film (or silicon nitride film) and the polycrystalline silicon film deposited on the semiconductor substrate 100 are patterned to form a capacitor insulating film 1221 of a DRAM capacitor. After forming the upper electrode 122, as shown in FIG. 93, a silicon oxide film 123 is deposited on the semiconductor substrate 100 by the CVD method, and the A1 film deposited on the silicon oxide film 123 is patterned. As a result, a first-layer metal wiring 124 is formed. Then, as shown in FIG. 94, a silicon oxide film 125 is deposited on the semiconductor substrate 100 by the CVD method, and the A 1 film deposited on the silicon oxide film 125 is patterned to form a second metal layer. The wiring 126 is formed.

The above is the outline of the microcomputer, flash memory, DRAM, and ASIC mixed process.

According to the study of the present inventor, the above mixed process has the following problems.

(1) To increase the logic speed, it is necessary to shorten the gate length of the MOS FET and reduce the thickness of the gate oxide film. On the other hand, the gate oxide of the MOS FET in the DRA-VI part needs to be somewhat thicker than the gate oxide of the MOS FET in the logic part in consideration of the withstand voltage. Furthermore, the gate oxide film of the high breakdown voltage MOS FET of the flash memory to which a high breakdown voltage is applied needs to be further thickened in order to secure a sufficient breakdown voltage. In other words, when DRAM, logic, and flash memory are mixed, gate oxide films with different thicknesses are required depending on the required power supply level, so the number of processes and the number of masks increase significantly.

(2) If a DRAM is composed of one transistor and one capacitor, high-temperature heat treatment (heat treatment for stabilizing a tantalum oxide film or high-temperature nitridation treatment for forming a silicon nitride film) is performed when forming a capacitor. It is necessary to set the gate length of the part slightly longer. However, increasing the gate length of the logic section sacrifices the high-speed performance of the mouthpiece.

(3) The elevation of the DRAM section on the semiconductor chip is higher than that of the logic section. Since a step is generated between them, wiring formation is adversely affected. In particular, this tendency is remarkable in the case of DRAMs that employ a stacked capacitor structure. In this way, a one-chip configuration is maintained while maintaining the performance of both the DRAV1, the logic, and the flash memory. Attempting to do so would require a drastic increase in the number of steps and masks, or a new mixed process suitable for one-chip integration, in each case significantly increasing manufacturing costs.

Further, in addition to the cost analysis in the manufacturing process as described above, there is a strong demand for a microphone-based computer system including a CPU to be equipped with both a flash memory and a DRAM in terms of a circuit based on a functional block configuration. Considering the ease of mounting on embedded devices, it is essential to integrate two types of semiconductor chips, flash memory and DRAM, into one package. Therefore, the present inventor has attempted to reduce the number of external connection terminals by assigning the common communication signal of each semiconductor chip to a common external connection terminal, and to reduce the mounting area by integrating a plurality of types of semiconductor chips into one package. I thought that it would be possible to reduce the cost of the microphone computer system in terms of circuitry. One object of the present invention is to reduce the number of external connection terminals and reduce the number of external connection terminals by using a function block configuration in a package structure in which two types of semiconductor chips, a CPU and a flash memory and a DRAM, are packaged separately. One-package semiconductor chip: An object of the present invention is to provide a semiconductor device capable of reducing the mounting area and reducing the cost of a microcomputer system.

Further, one object of the present invention is to provide a common external connection terminal when each semiconductor chip has a built-in logic circuit such as an ASIC or when a DRAM is a synchronous DRAM. It is still another object of the present invention to provide a semiconductor device capable of reducing the number of external connection terminals and reducing the cost. Further, a third object of the present invention is to provide the above-described semiconductor device at a low cost. And there.

Further, in the microcomputer system as described above, for example, a semiconductor chip called a microcomputer equipped with a flash memory equipped with a CPU and a flash memory, and a logic circuit such as a DRAM and an ASIC are mounted. Two types of semiconductor chips called so-called DRAM on-chip logic When considering semiconductor chips of a kind, it is essential to take countermeasures between the microphone-computer with flash memory and the DRA [on-chip logic]. In other words, measures are taken for the data transfer speed between the CPU operation of the computer with the flash memory-equipped microphone and the access operation to the DRAM of the DRAM on-chip logic and the access operation to the DRAM from the logic circuit inside the DRAM on-chip logic. Is required.

For example, if you want to connect the above-mentioned microcomputer with flash memory and the semiconductor chip of the DRAM on-chip logic at high speed, you can use the direct connection interface of DRAM to connect at high speed. When an on-chip logic circuit wants to access DRA-M, the first method is to return a wait signal to the CP while the logic circuit is operating. In this method, since the memory between the microcomputer with flash memory and the DRAM on-chip mouth must be treated as an asynchronous memory, one clock cycle cannot be transferred, that is, the time during which the wait signal is being viewed. ₃ also becomes data transfer 2 Qu port Kkusaikuru and does not take, as the second method can be realized by one clock cycle, there is a method of Basuabito Reshiyon the deaf Ppurojikku itself into the flash memory mounted microcomputer. In this method, the logic circuit of the DRAM on-chip logic outputs a request signal requesting the CPU to open the bus, and the CPU does nothing while the bus is open to the logic circuit. In this case, the overhead of the arbitration becomes large and the CPU itself cannot perform time control.

Therefore, the present inventor focused on the fact that it is preferable that the CPU of the microcomputer with the flash memory control the time itself, and effective the self-refresh period of the DRAM viewed from the CPU of the microcomputer with the flash memory. In addition to enabling the DRAM self-refresh operation during this self-refresh period, the logic circuit inside the DRAM Data transfer between on-board microcomputer and DRAM on-chip logic We came up with the idea that high-speed transmission can be realized.

One object of the present invention is to provide a semiconductor chip on which a DRAM and a logic circuit such as an AS IC are mounted, by effectively utilizing a self-refresh period of the DRAM viewed from the outside by eliminating the need for wait control. An object of the present invention is to provide a semiconductor device which enables a logic circuit to perform an access operation to a DRAM during a refresh period, thereby realizing high-speed data transfer between an external device and a semiconductor chip.

Also, in a package structure in which two types of chips, a semiconductor chip equipped with DRAM and a logic circuit, and a semiconductor chip equipped with a CPU and flash memory, are integrated into one package, weight control becomes unnecessary and C An object of the present invention is to provide a semiconductor device that enables a logic circuit to perform an access operation to a DRAM during a DRAM self-refresh period as viewed from a PU, thereby realizing high-speed data transfer between semiconductor chips.

In addition, there is no need for weight control for weight signal exchange, and the timing of processing itself can be controlled from the CPU, thereby providing a semiconductor device that can facilitate program creation. is there.

In addition, by using a general-purpose DRA-VI interface, a semiconductor chip equipped with DRAM and a logic circuit is directly connected to a semiconductor chip equipped with CP and flash memory for high-speed operation. It is decided to provide a semiconductor device capable of performing such operations.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Disclosure of the invention

The following is a brief description of an outline of typical inventions disclosed in the present application.

That is, the method for manufacturing a semiconductor device according to the present invention includes:

(a) After forming device holes and through holes in each of the plurality of tape carriers, patterning the conductive layer formed on one surface of the tape carrier. Forming a lead having one end protruding into the device hole and the other end connected to the through hole;

(b) After bonding the leads to the connection terminals of the semiconductor chip arranged in the device holes of the plurality of tape carriers and electrically connecting them, a plurality of tapes are formed by resin-sealing the semiconductor chip. The process of forming a carrier,

(c) by stacking the plurality of tape carriers in a vertical direction such that the through holes overlap each other, and then forming a conductor layer inside the through holes and electrically connecting the through holes. The process of forming a stacked TCP,

(d) forming an external connection terminal of the laminated TCP at one end of the through hole, wherein a connection terminal common to a plurality of semiconductor chips mounted on the plurality of tape carriers is the same as the plurality of tape carriers. This is drawn out to the same external connection terminal through the through hole formed at the location.

Further, in the method for manufacturing a semiconductor device according to the present invention, the semiconductor chip includes at least a semiconductor chip on which a CPU and a flash memory are formed, and at least one or more semiconductor chips on which a DRAM is formed. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. BRIEF DESCRIPTION OF THE FIGURES

FIGS. 1 to 6 are schematic configuration diagrams showing a configuration example of a semiconductor device according to an embodiment of the present invention, and FIGS. 7 to 14 are internal configurations of a semiconductor chip constituting a semiconductor device according to an embodiment of the present invention. Functional block diagrams showing examples and explanatory diagrams showing examples of terminal functions, FIGS. 15 to 18 show explanatory diagrams showing examples of terminal functions of semiconductor chips, and FIGS. 19 and 20 show examples of connection of semiconductor chips. FIG. 21 is a schematic configuration diagram schematically showing an example of an internal function of a semiconductor chip, FIG. 22 is a configuration diagram showing a detailed example of a DRAM access control unit, and FIG. 23 is an internal control signal generation circuit FIG. 24 is an explanatory diagram showing an example of a transition state of an operation mode. FIG. 24 is an operation timing diagram showing a control example of a DRAM access control unit for a DRAM. FIG. 25 is an overall perspective view of a package according to an embodiment of the present invention. 2 6 of this package Sectional views, FIGS. 27 and 28 are plan views showing a lead pattern formed on one surface of the tape carrier, and FIGS. 29 to 37 show a method of manufacturing a semiconductor device according to an embodiment of the present invention. 38 to 66 are cross-sectional views showing another method of manufacturing this semiconductor device, and FIGS. 67 to 69 are plan views showing patterns of leads formed on one surface of a tape carrier. FIGS. 70 to 72 are cross-sectional views showing another embodiment of the semiconductor device, and FIGS. 73 to 77 are functional block diagrams showing an example of a system configuration using the semiconductor device of the present embodiment. FIG. 78 to FIG. 94 are cross-sectional views showing the microcomputer, flash memory, DRAM, and ASIC mixed processes studied by the present inventors. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and the description thereof will not be repeated.

First, a configuration example of the semiconductor device of the present embodiment will be described with reference to FIGS. The semiconductor device according to the present embodiment is, for example, an LSI package having a stacked structure in which a plurality of types of semiconductor chips are connected to each other so that signals can be input and output. A chip MF (first semiconductor chip) called a microcomputer equipped with a flash memory, which is equipped with a microcomputer M including peripheral circuits and peripherals, and a flash memory F, and logic such as DR AMD and ASIC It consists of a chip AD (second semiconductor chip) called a so-called DRAM on-chip logic on which the circuit A is mounted. The connection terminal between each chip MF and chip AD is connected via a bus inside the package. Connected to each other and to an external connection terminal that enables connection with the outside.

Here, the flash memory F is one of the LSI memories, which is a programmable nonvolatile memory, and is a memory that performs writing or erasing by applying a high voltage to the memory cells. An LSI memory is a memory in which it is necessary to supply a control (refresh) signal for repetitive data reproduction in order to retain the contents of data in one of the LSI memories. In addition, ASICs are application-specific ICs. Other Les dedicated IC, have Unlike a general-purpose LSI that are sold on the open market as a large-capacity memory LS I and micro-processor LSI, there is an LSI that was developed for the specific equipment, to _sell:)

As another configuration example, as shown in FIG. 2, a chip MF (first semiconductor chip) on which a microphone computer M including a CPU, a memory, a peripheral circuit, and the like, and a flash memory F are mounted. , DR A chip D (second semiconductor chip) on which only AMD is mounted. In the configuration example of Fig. 1, the logic circuit A such as AS IC is removed from the second semiconductor chip. I have.

Further, as another configuration example, as shown in FIG. 3, a microphone memory computer M including a CPU, a memory and peripheral circuits, a flash memory F, and a logic circuit A are mounted. It consists of a chip MFA (first semiconductor chip) called an on-chip logic microcomputer and a chip D (second semiconductor chip) on which only DRAMD is mounted. The configuration is such that a logic circuit A such as an AS IC is mounted on the first semiconductor chip.

In addition, for example, as a modified example of FIG. 1, when a chip is configured by a chip MF A and a chip AD as shown in FIG. 4, as a modified example of FIG. 2, one chip MF as shown in FIG. In the case of a configuration including a plurality of chips D, a configuration example such as a configuration including a chip MFA and a plurality of chips D as shown in FIG. .

Semiconductors with chip MF + chip AD, chip MF + chip D, chip MF A 丄 chip D, chip MF A + chip AD, chip MF + chip D (extended), chip MFA + chip D (extended) In the example of the device configuration, the microcomputer M, flash memory F, DRAMD, and logic circuit A mounted on each chip are composed of the same functional blocks even if the chip configuration is different:

The chip AD and the chip D are easily connected directly to the chip MF and the chip MFA by the general-purpose DRAM interface specification, and the DR AMD is used as an extended memory in each semiconductor device. Furthermore, AS IC of chip AD In any logic circuit A, access control to DR AMD can be performed inside chip AD independently of access control by the CPU of chip MF and chip MFA.

Here, the outline of each semiconductor chip will be described with reference to FIGS. In particular, chip MF, chip AD, and chip D will be described in order. FIGS. 15 to 18 show a list of examples of the terminal functions of the chip MF.

7 and 8 show examples of the 144-pin chip MF, FIG. 7 is a functional block diagram showing an example of the internal configuration, and FIG. 8 is an explanatory diagram showing an example of the terminal functions. 9 and 10 show examples of pins 112 of the chip MF, FIG. 9 is a functional block diagram showing an example of the internal configuration, and FIG. 10 is an explanatory diagram showing an example of the terminal functions. The difference between the 144-pin chip: l F and the 11.2-pin chip MF is that the external terminals for data input / output correspond to the 32-bit and 16-bit data widths of D0 to D, respectively. 31 is the only difference between D0 and D15. Here, the 144-pin chip MF will be mainly described. — This 144-pin chip MF is formed at least by the microphone port computer and the flash memory. It has a circuit configuration that has overall control and processing functions of the semiconductor device and a programmable memory function that can be electrically erased in a batch. For example, as shown in FIG. 1 ash, random access memory / cache memory RA 1 / Cache, data transfer controller DTC, direct memory access controller DMA C, bus state controller BSC, user blur Network controller UBC, interrupt controller I NTC, serial communication interface SCI, multi-function timer panelless unit MTL; compare match timer CMT, / D converter A / D, watchdog timer WDT, faze look loop The processor CPU is a central processing unit having a RISC type instruction set, for example. Since this CPU basically operates in one instruction and one cycle, the instruction execution speed is dramatically improved, and the internal 32-bit configuration enhances the data processing capability. The features of this CPU include a general-purpose register machine (16 general-purpose registers, 16 32-bit registers, 3 32-bit control registers, Instruction set compatible with RISC (Instruction length is 16-bit fixed length to improve code efficiency), Load store architecture (Basic operation is executed between registers), Delayed branch instruction Reduces pipeline turbulence at branching, C language-oriented instruction set), instruction execution time is 1 instruction Z1 cycle (35 ns / instruction at 28 MHz operation), address space is 4 GB in architecture, multiplier Built-in functions include 32 x 32 → 64 multiplication in 2 to 4 cycles, 32 x 32 + 64-64 multiply and accumulate in 2 to 4 cycles, and a 5-stage pipeline method.

The flash memory F 1 ash is a circuit that incorporates, for example, a 64 Kbyte or 128 Kbyte electrically erasable programmable memory that can be erased collectively. This F1ash is connected to the CPU, DMAC, and DTC via a 32-bit data bus, for example. The CPU, DMAC, and DTC can access F1ash with 8, 16, or 32 bits wide. This F 1 ash data can always be accessed in one state.

The random access memory / cache memory RAM / Cache is, for example, a memory composed of a random access memory RAM of 4 KB and a cache memory Cache of 1 KB. The features of this cache are instruction code and PC relative readout, data caching, line length is 4 bytes (1 long word is 2 instruction lengths), cache tag is 256 entries, direct map method, built-in ROM / RA , The built-in IZ area is not subject to caching and is also used as built-in RAM. When cache is enabled, various functions are provided, such as using 2 KB of the built-in RAM as an address array and data array.

The data transfer controller DTC is a circuit that can be activated by an interrupt or software to perform data transfer. The features of this DTC are that data can be transferred independently of the CP by an interrupt request from the peripheral I70, the transfer mode can be set for each interrupt source (transfer mode is set on the memory), and one activation source Multiple data transfer possible, various transfer modes (Normal mode / Rebeat mode / Block transfer mode) can be selected, Byte transfer unit

// Can be set to word Z long mode, request the CPU to activate the DTC interrupt (An interrupt to the CPU can be generated after one data transfer is completed, and an interrupt can be generated to the CPU after all specified data transfers are completed.) I have. The address space can be specified with 32 bits for both the transfer source address and the transfer destination address, and the transfer target device is for the internal memory such as Flash memory, Flash / RAM, external memory, and internal peripheral circuits. Data transfer

The direct memory access controller DMAC consists of, for example, four channels. Data is transferred between an external device with DACK (transfer request acceptance signal), an external memory, an external memory map device, and internal peripheral circuits (excluding DMAC, BSC, and UBC). This is a circuit that can perform high-speed data transfer in place of the CPU. Using this DMAC can reduce the load on the CPU and increase the operating efficiency of the chip MF. The features of this DMAC are: cycle stealing transfer, dual address mode transfer support, direct transfer mode Z indirect The transfer mode can be switched (only channel 3). In this direct transfer mode, the data in the source address is transferred to the destination address. In the indirect transfer mode, the data in the source address is used as the address. Is a function to transfer the data in the destination to the destination address. In addition, for specific channels, there is a reload function, an external request, an internal circuit, a transfer request function by auto request, a bus mode selection, a fixed priority mode, a priority setting by a round mouth bin mode, and a CP. It has various functions such as interrupt request to the same

The bus state controller BSC is a circuit that separates an address space, outputs control signals corresponding to various memories, and the like. This makes it possible to directly connect DRAM, SRAVI, ROM, etc. to the chip MF without external circuits. The feature of this BSC is that it supports memory access during external expansion (external data bus The address space is divided into 5 areas (SRAM space x 4 areas, DRAM space XI area), each area has a bus size (8 / 16Z 32-bit), number of wait cycles, and each area Output of chip select signal corresponding to DDR, output of DRAM RAS when accessing DRAM space, output of CAS signal, RAS precharging time securing Tp cycle can be set, and which characteristics can be set, DRAM bar Fast access function (supports DRAM high-speed access mode), DRAM refresh function (programmable refresh interval, supports CAS refresh before RAS refresh / self-refresh), wait cycle insertion by external wait signal Yes, various functions that can access the address data multipletus IZ II device are provided.

The user break controller UBC is a circuit that provides functions that facilitate user program debugging. When a break condition is set in this UBC, a user break interrupt is generated according to the contents of the bus cycle by the CPU or DMAC and DTCC. By using this function, a high-performance self-monitoring debugger can be easily created, and programs can be easily debugged with the chip MF alone without using a large-scale in-circuit emulator. . The features of this UBC are that an interrupt is generated when the CPU or DMAC generates a bus cycle under a set condition, and that an on-chip debugger can be easily constructed. MAZDTC cycle, instruction fetch or data access, read or write, operand size (longword, word, byte) can be set. When these break conditions are satisfied, a user break interrupt is generated and the user The break interrupt exception routine can be executed.-The interrupt controller INTC is a circuit that determines the priority of interrupt factors and controls interrupt requests to the processor CPU. This INTC has a register for setting the priority of each interrupt, so that interrupt requests can be processed according to the priority set by the user. The features of this INTC include nine external interrupt pins, 43 internal interrupt sources, 16 levels of priority setting, and a noise canceller function that indicates the status of the NMI pin. It is possible to output the occurrence of an interrupt to the outside, notify the external bus master that an internal peripheral circuit interrupt has occurred while the chip MF has released the bus right, and request the bus right. I have.

The serial communication interface SCI, for example, has two independent channels. The two channels have the same function. This SCI is a circuit that can perform serial communication in two systems: start-stop synchronous communication and clock synchronous communication. In addition, a serial communication function between multiple processors (multiprocessor communication function) is provided. The features of this SCI are: Asynchronous / clock synchronous mode can be selected for each channel, transmission and reception can be performed simultaneously (full duplex), dedicated baud rate generator built-in, multiprocessor Various functions such as communication functions are provided.

The Manorechi function timer pulse unit MTU is a circuit configured by, for example, a 16-channel 16-bit timer. This MTU has the following features: 16 types of waveform output or 16 types of input / output processing of up to 16 types of pulses based on 5 channels of 16-bit timer, 16 output compare registers and input keys Bucher registers, total number of 16 independent comparators, selectable eight types of counter input clocks, input capture function, pulse output mode (in-shot / toggle ZP WM complementary PWM / reset synchronization PWM ), Synchronization function of multiple counters, Complementary PWM output mode (outputs non-overlap waveform for 6-phase inverter control, dead time automatic setting, PWM duty can be set to any value from 0 to 100%, output OFF function), Reset synchronous PWM mode (Positive and negative phase PWM waveforms of arbitrary duty are output in 3-phase), Phase counting mode (2-phase encoder counting is possible), etc. Various functions are provided.

The compare match timer CMT is composed of, for example, two channels, a 16-bit free running counter, one compare register, etc., and has a function of generating an interrupt request at the compare match.

The A / D converter AZD is a 10-bit x 8 channel, which enables conversion by external trigger and has two built-in sample & hold functions, so that two channels can be sampled at the same time. I have.

The watchdog timer WDT is a one-channel timer that can monitor the system. This WDT outputs an overflow signal to the outside if the CPU overflows the counter value due to system runaway, etc., without being correctly rewritten by the CPU. At the same time, the chip MF can generate an internal reset signal. Wear. When not used as a WDT, it can be used as an interval timer. When used as an interval timer, an interval timer interrupt is generated each time the counter overflows. The WDT is also used when exiting standby mode.The internal reset signal can be generated by setting a register, and the reset type can be set to a reset or manual reset. You can choose. The features of this WDT include the ability to switch the watchdog timer and the interval timer, a countover buffer temporary, an internal reset, and the ability to generate an external signal or interrupt.

The phase-look loop circuit PLL is a circuit that incorporates, for example, a clock oscillator and operates as a PLL circuit for clock doubling.

In the chip MF configured as described above, these internal circuits are connected to each other by an internal address bus BUS AI and upper and lower internal data buses BUS DI as shown in FIG. And the external connection terminal IZO are connected by the peripheral address bus BUS A〇, the peripheral data bus BUSDO, and the control signal line SL.

Internal address bus BU SAI is a bus width of 24 bits, the processor CP ^to: flash memory F 1 ash, random access memory / cache memory RAM / C ache, Data transfer control one la DTC, direct Tomemo Li Access Controller DMAC and bus state controller BSC are connected between each other.

The internal data bus BU SDI consists of a high-order 16-bit bus and a low-order 16-bit bus, each of which is a processor CPU, flash memory F1ash, random access memory Z cache memory RAM / C ache, data transfer controller DTC, direct memory access controller DMAC, and state controller BSC are connected between each other, and the upper 16-bit bus and the lower 16-bit bus This allows for a 32-bit data width.

The address bus BUS AO has a bus width of 24 bits and a bus state code. Controller BSC, interrupt controller I NTC, serial communication interface SCI, multi-function timer pulse unit MTL; compare match timer CMT, watchdog timer WDT internal circuit and external connection terminal I ZO Is connected between.

The peripheral data bus BUSDO has a bus width of 16 bits. The bus state controller BSC, interrupt controller I NTC, serial communication interface SCI, manorechi function timer pulse unit MTU compare match timer CMT, It is connected between each internal circuit of watchdog timer WDT and external connection terminal IZ〇.

The control signal line SL consists of a data transfer controller DTC, a direct memory access controller DMAC, a bus state controller BSC, a use break controller UBC, an interrupt controller INTC, a serial communication interface SCI, and a multifunction timer panorama. It is connected between the internal circuits of the Resunit MTU, compare match timer CMT, and AZD converter A / D, and between these internal circuits and the external connection terminal I / O.

In this chip MF, the functions are assigned as shown in Fig. 8 as the external connection terminal I ZO, with 98 input / output terminals and 8 input terminals. The functions of 〇 are as shown in the list of examples of terminal functions corresponding to the classification, symbols, input / output, and names, as shown in Fig. 15 to Fig. 18. The MF is assigned functions as shown in Fig. 10, and has 74 input / output terminals and 8 input terminals.

Fig. 11 is a functional block diagram showing an example of the internal configuration of the chip AD, and Fig. 12 is an explanatory diagram showing an example of the terminal functions. Note that the chip AD shows an example of 144 pins: , A DRAM and an ASIC are formed, and have a circuit configuration having a memory function that can be written and read at any time and a processing function by a logic circuit. For example, as shown in FIG. DRAM bank Bank, main amplifier MA, data transfer circuit DT, digital signal processing circuit DSP, row address buffer RAB, column address buffer CAB, control logic, It is composed of a mining generation circuit CRZTG. The DRAM is a dynamic random access memory (DRAM) that can be written and read at any time that requires a memory retention operation, a synchronous synchronous DRAM (SDRAM) using a clock, and an external memory that can lengthen the data output time. Date Data Out DR A (EDO-DRAM).

The power supply circuit VS is a circuit for supplying necessary power to the plurality of DRAM banks B ank and the main amplifier MA by using externally supplied voltages of the power supply V cc and the ground V ss. Can operate independently, and each bank includes, for example, a memory cell, a word decoder, a column decoder, a sense amplifier, and a timing generator. For example, the capacity of these DRAM banks B an k is 256 k bits per bank.

The main amplifier MA is a circuit that performs data input / output between the plurality of DRAM banks B ank and the external connection terminals DO to D31. For example, between each DRAM bank B ank, there are 128 and many global data lines through which data is exchanged.

The data transfer circuit DT switches a data transfer pattern between a DRAM including a DRAM bank B ank and a main amplifier MA and a digital signal processing circuit D SP in real time. For example, it is possible to select one of the adjacent data or clear the data

Digital signal processing circuit DSP is a circuit that executes digital signal processing such as image and sound processing.For example, in the case of image processing, processing to remove hidden surfaces by Z comparison, processing to give transparency by ct blending, etc. Execute. Also, data is output from the serial output ports SD0 to SD23 to an output device such as a display. The digital signal processing circuit DSP and the data transfer circuit DT are controlled by control signals C0 to C27.

The address address buffer RAB and the column address buffer CAB are circuits that take in address signals from the external address signal input terminals AO to A10, generate internal address signals, and supply the signals to each DRAM bank Bank. . Bar RAS timing row address, bar CAS L, bar CASH, bar CASHL, bar Capture column address at CASHH timing.

The control logic / timing generation circuit CR / TG is a circuit that generates various timing signals necessary for the operation of the DRAM. The input bar CS is the chip select signal, bar RAS is the row address strobe signal, bar CAS L, bar CASH, bar CASHL, bar CASHH is the column address strobe signal, and RD / bar WR is the read / write signal (high). Level indicates read, low level indicates write). The four column address strobe signals are used to enable byte control (read / write control for each byte), with CAS L being the lowest byte D0 to D7 and CASH being the lowest. The second byte D8 to D15, the bar CASHL is for the third byte D16 to D23 from the bottom, and the bar CASHH is for the top byte D24 to D31.

In the internal circuit of the chip AD configured as described above, the plurality of DRAM banks Bank, the row address buffer RAB, and the column address buffer CAB are connected to each other by the internal address bus BUSA I, and further, the row address buffer is used. The peripheral address bus BUS AO connects the RAB and column address buffer CAB to the external connection terminal I / O, and the peripheral data bus BUS DO connects the main amplifier IA to the external connection terminal I / O:

The data transfer circuit DT and the digital signal processing circuit DSP are connected to each other by an address bus and an internal data bus BUS I. The data transfer circuit DT, the digital signal processing circuit DSP and the external connection terminal I / O Are connected by a peripheral bus BUSO for data and control signals.

In this chip AD, as external connection terminals, as shown in Fig. 12, power supply Vcc, ground Vss voltage terminals Vcc, Vss, address terminals AO to A10, data input / output terminals D0 to D31 1, Chip select pin bar CS, row address strobe pin bar RAS, column address strobe pin bar CAS L, bar CASH, bar CASH L, bar CASHH, read / write pin RD / bar WR, clock pin CK: Serial data output terminals SD0 to SD23 and AS IC control signal terminals C0 to C27 are provided.

Fig. 13 is a functional block diagram showing an example of the internal configuration of chip D, and Fig. 14 is its terminal functions. It is explanatory drawing which shows an example. Note that chip D shows an example of 50 pins.

This chip D has a circuit configuration having only a DRAM and a memory function that can be written and read at any time. For example, as shown in FIG. 13, a power supply circuit VS, a plurality of DRAM banks Bank, It consists of a main amplifier MA, a row address buffer RAB, a column address buffer CAB, and a control logic Z timing generator CR ZTG.

The chip D has a circuit configuration of only the DRAM in which the logic circuit of the data transfer circuit DT and the digital signal processing circuit DSP of the chip AD shown in FIG. Since the internal circuit to be used is the same as the internal circuit of the chip AD, the functional description is omitted here.

In this chip D, as external connection terminals, as shown in FIG. 14, power supply Vcc, ground Vss voltage terminals Vcc, Vss, address terminals ΑΟ to Α11, data input / output terminals 0 <30 to 0 <331 1, Row address strobe pin bar RAS, column address strobe pin bar LCAS, bar UCAS, write enable pin bar WE, output enable pin bar OE.

In the semiconductor device of the present embodiment configured by combining the chip MF and the chip MFA with one or a plurality of chips AD and the chip D as described above, the chip MF is one of the features of the present invention. Alternatively, the signal terminal common to the chip MFA connection terminal and the chip AD or chip D connection terminal is commonly assigned to the same external connection terminal. Hereinafter, the connection terminals commonly assigned to the same external connection terminal will be described in detail.

FIG. 19 is a connection diagram showing an example of connection between the 144-pin chip MF shown in FIGS. 7 and 8 and the two 50-pin chips D shown in FIGS. 13 and 14. In FIG. 19, only the connection between the signal terminal common to the connection terminal of the chip MF and the connection terminal of the chip D and the external connection terminal is shown. In practice, the signal terminal independent only to the chip MF is shown. Is also connected to the external connection terminal.

In the connection between the 144-pin chip MF and the two 50-pin chips D, the address terminals AO to A11 of the chip MF are connected to the address terminals AO to A11 of the two chips D and the same external terminals. Connected to connection terminals A 0 to A 1 1 and chip M The data input / output terminals D 0 to D 31 of the F are divided and connected to the data input / output terminals D Q0 to DQ 15 of the respective chips D and connected to the same external connection terminals DO to D 31, and

In addition, the power supply terminal V _CC and the ground terminal V ss of the chip MF are connected to the power terminal V _cc and the ground terminal V ss of the respective chip D and also connected to the same external connection terminal V cc and V ss, respectively. I have. Since these voltage terminals are actually assigned to a plurality of terminals such as a chip MF, a chip D, and an external connection terminal, each is connected by the same terminal.

Further, according to the control signal, the row address strobe terminal bar RAS of the chip MF is commonly connected to the two chips D and connected to the external connection terminal bar RAS, and the column address strobe of the chip MF is provided. Terminal bar CAS L and bar CAS H are connected to column dress strobe terminal bar L CAS and bar UCAS of chip D, and are also connected to external connection terminal bar CAS L and bar CASH and chip MF The column address strobe terminals CASHL and CAS HH are connected to the column address strobe terminals L CAS and UCAS of the other chip D, and to the external connection terminals CASHL and CASHH. Also, the read / write terminal RDZ bar WR of the chip MF is connected to the write enable terminal bar WE of the two chips D in common, and is also connected to the external connection terminal RD / bar WR, and the chip select terminal bar CS of the chip MF Numeral 3 is commonly connected to the output enable terminal bar OE of the two chips D and to the external connection terminal bar CS3.

As described above, in the connection between the chip MF, the chip D, and the external connection terminal, all the connection terminals of the chip D are common to the connection terminals of the chip MF and are connected to the same external connection terminals. Note that, in the semiconductor device including the chip MF and the chip D, there are actually connection terminals which are independent signal terminals only on the chip \ 1F, so that external connection terminals connected to the independent connection terminals are also included. Provided so that it can be connected to the outside ₃

FIG. 20 is a connection diagram showing a connection example between the 144-pin chip MF shown in FIGS. 7 and 8 and the 144-pin chip AD shown in FIGS. 11 and 12. In addition, FIG. 20 also shows only the connection between the signal terminal common to the connection terminal of the chip MF and the connection terminal of the chip AD and the external connection terminal, as in FIG. The connection terminal, which is an independent signal terminal only for the chip AD, is also connected to the external connection terminal.

In the connection between the 144-pin chip MF and the 144-bin chip AD, the address terminals AO to A10 of the chip MF are connected to the address terminals AO to A10 of the chip AD and the same external connection terminal AO. To A10, and the data input / output terminals D0 to D31 of the chip MF are connected to the data input / output terminals D0 to D31 of the chip AD and the same external connection terminals DO to D31 It is connected to the.

The power supply terminal Vcc and the ground terminal Vss of the chip MF are connected to the power supply terminal Vcc and the ground terminal Vss of the chip AD, respectively, and are also connected to the same external connection terminals Vcc and Vss, respectively. Note that these voltage terminals are actually assigned to multiple terminals of the chip MF, chip AD, and external connection terminal, so each is connected by the same terminal.

In addition, the control signals are as follows: row address strobe terminal bar RAS of chip MF, column address strobe terminal bar CAS L, bar CASH, bar CA SHL, bar CASHH, read Z write terminal RD / bar WR, chip select CTS terminal bar CS 3 and clock terminal CK are the chip AD row address strobe terminal bar RAS, column address strobe terminal bar CAS L, CASH, CASH L, CASHH, read / write terminal RDZ, WR, Chip select terminal bar CS 3 and clock terminal CK are connected to each other, and the same external connection terminal, row address strobe terminal bar RAS, column address port terminal bar CASL, bar CASH, bar CASHL, bar CA SHH, read / write terminal RD / bar WR, chip select terminal CS3, clock terminal CK ing.

As described above, in the semiconductor device including the chip MF and the chip AD, the serial data outputs SD0 to SD23, which are signals specific to only the chip AD, and the ASIC control signal terminals C0 to C27 are independent. Since there are also connection terminals that are independent signal terminals only in the chip MF, external terminals connected to these independent connection terminals The connection terminal is also provided so as to be connectable to the outside.

In the semiconductor device, when the DRAM of the chip AD and the chip D is a synchronous DRAM, it is necessary to further synchronize inside the semiconductor device. Therefore, a clock signal which is a control signal for this synchronization is required. The clock terminal to which is assigned is also connected to the same external connection terminal as a common connection terminal.

Next, regarding the operation of the present embodiment, in a semiconductor device configured by combining the chip MF and the chip MFA with one or more chips AD and the chip D, the chip MF (chip IF A) The outline of read, write, and refresh operations from the processor CPU to the DRAM of chip AD (chip D) is described.

(1) Read operation

For example, in the addressless bretas, since the address signal is input in a time-division manner, two synchronous signals of a row address strobe signal RAS and a column address strobe signal CAS from the processor CPU are required. The period when RAS is high (H) is the period during which the RAS circuit is precharged, and no memory operation is performed inside the chip during this period. On the other hand, the period when the bus CAS is H is a period in which the CAS circuits such as the data output buffer and the data input buffer are precharged, and during this period, the read operation and the write operation with the outside of the chip AD are not performed.

When RAS goes low (L), the RAS circuitry is activated and memory operation begins. Subsequently, when the bar CAS becomes L, the read operation or the write operation starts, and data is exchanged with the chip MF outside the chip AD. As described above, in the DRAM of the chip AD, the precharge period and the active period are alternately repeated. Normally, the cycle time of RAS is the cycle time of chip AD. The read operation is specified by setting the write enable signal WE to H before the falling edge of CAS, until the CAS rises. Do it by holding it. Once the data is output, the data is held until the basic CAS starts. There are three types of access time, bar RAS and bar The time from the falling edge of one CAS until the data is output to the data output terminal is called the RAS access time and the CAS access time, respectively.The time from when the column address is determined until the data is output Is called the address access time.

(2) Write operation

The relationship between the address signal and RAS and CAS is the same as in the read operation, so the description is omitted here. The timing specifications of RAS and CAS, such as the cycle time, are the same as in the read operation. However, the write operation is specified by setting WE low before the fall of CAS. During this cycle, the data output terminal is kept in the high impedance state. It should be noted that there is also a specification of a Read-a-write Write operation in which data once read out to the chip MF outside the chip AD is changed by the chip MF while the base R AS is kept at L, and the data is written again to the same memory cell.

(3) Refresh operation

There are two types of refresh operations: interrupt operations during random access operations such as read and write operations, and refresh operations that are performed only to retain information stored inside the chip AD during the battery backup period. The former is standard for RASonely refresh and CBR (RAS for RAS) refresh, and the latter is standard for self-refresh.

For example, in RAS only refresh, all memory cells in one row (word line) are refreshed simultaneously during one cycle of RAS with the same timing standard as read operation and write operation. However, the bus CAS must be set to H and the refresh address must be given from the chip MF outside the chip AD. There are two types of refresh: centralized refresh and distributed refresh. Centralized refresh repeats the refresh in the minimum cycle. During this period, the memory cannot be accessed from the chip MF outside the chip AD, but the rest of the period is the refresh. This is a method that accepts external memory access without interrupting the refresh. Distributed refresh is one in which one refresh operation is evenly distributed over the maximum refresh period. In practice, distributed refresh is often used, One cycle of the fresh operation is the timing that interrupts the normal read / write operation cycle.

The CBR refresh is internally determined to be a refresh operation by setting the CAS to L before the RAS. With this determination pulse, an address is generated from the internal refresh address counter, and the word line is selected and refreshed. Therefore, it is not necessary to give an address from outside the chip AD.

Further, in the self-refresh, after the normal memory cycle is completed, the pulse width of RAS is set to, for example, 100 μs or more by performing CBR timing. Internally, when this time is exceeded, the refresh operation using the refresh address counter and refresh timer starts, and self-refresh continues as long as both RAS and CAS are low. The less frequently refreshed, the lower the power consumption of chip AD, but this frequency is automatically adjusted by a timer that detects the internal temperature of chip AD. When shifting from the self-refresh to the normal cycle, a precharge period of RAS is required.

As described above, the read operation, the write operation, and the refresh operation are performed from the processor CPU of the chip MF to the DRAM of the chip AD. In particular, at the time of the refresh self-refresh operation, one feature of the present invention is that the chip AD The internal logic circuit has a circuit configuration capable of executing a refresh operation / access operation. Hereinafter, it will be described in detail that the refresh operation / access operation can be performed during the self-refresh operation.

FIG. 21 is a schematic configuration diagram schematically showing an example of internal functions of the chip AD shown in FIG. This chip AD is composed of a dynamic random access memory DRAM, a memory logic Logic, and a DRAM access control circuit DAC. Note that the DRAM, logic logic with built-in memory, and DRAM access control circuit DAC in FIG. 21 correspond to a DRAM section by a plurality of DRAM banks and a main amplifier MA shown in FIG. Circuit DT and digital signal processing circuit AS AS part by DSP and access by low address buffer RAB and dynamic RAM address buffer CAB etc. It corresponds to the control part. The input buffer IB and the output buffer 〇B are connected to the circuit I / O for performing data input / output between the main amplifier MA and the external connection terminals DO to D32 shown in FIG. 11 and the digital signal processing circuit DSP. It corresponds to the circuit I / O to be performed.

In this chip AD, the chip select signal CS, the row address strobe signal RAS, and the column address strobe signal CAS are used as control signal terminals, and address signals are sent to the DRAM access control circuit DAC via address terminals. Input and data signals can be input / output via the data input / output terminal. Further, inside the chip AD, the DRAM and the DRAM access control circuit DAC are connected by an address bus BUS A, and the DRAM and a logic built in the memory Logic and a data bus BUS are connected between the data input / output terminals. Connected by D. For example, the internal data bus BUS D has a wider 64-bit bus width than the 8-bit data input / output terminals, for example:

Also, inside the chip AD, the logic logic with built-in memory and the DRAM access control circuit DAC are connected by an address bus control signal line, and the logic logic with built-in memory is connected from the DRAM access control circuit DAC. In response to this, a self-refresh operation enable signal is output, and a read / write Z write signal R / W and an address signal are output from the logic inside the memory to the DRAM access control circuit DAC. Note that the read Z write signal RZW can also be output separately for the read signal R and the write signal W. During the self-refresh period, the data input / output inhibit signal DIS is output from the DRAM access control circuit DAC to the input buffer IB and the output buffer OB. During the self-refresh period by the data input / output inhibit signal DIS, the input buffer IB inhibits data input from outside the chip AD, and the output buffer circuit OB outputs data on the data bus BU SD to the outside of the chip AD. Prohibit that. FIG. 22 is a configuration diagram showing a detailed example of the DRAM access control circuit DAC. The DRAM access control circuit DAC includes an internal control signal generation circuit CSG, a plurality of selector circuits SC, and the like, and is input to the internal control signal generation circuit CSG. Based on the chip select signal bar CS, row address strobe signal bar RAS, and column address strobe signal bar CAS, it generates a control signal to select an address, etc., and also generates a self-refresh operation enable signal and incorporates memory. Output to logic.

The logic in the memory that has received the permission signal becomes accessible to the DRAM, and outputs a read / write signal R / W to the DRAM access control circuit DAC to read / write data. Makes a request, outputs an address signal to the DRAM access control circuit DAC, selects an arbitrary memory cell, and reads / writes data between the selected memory cell and the logic with built-in memory. It can be carried out. Note that this read / write request can be made by outputting a read signal R when making a read request and outputting a write signal W when making a write request.

The address control signal generated by the internal control signal generation circuit CSG is used for access operations from the processor CPU of the chip MF outside the chip AD and access operations from the logic Logic inside the chip AD internal memory. In contrast, one is selected via a selector circuit SC and used as an address control signal for selecting an arbitrary memory cell of the DRAM.

FIG. 23 is an explanatory diagram showing an example of a transition state of the operation mode by the internal control signal generation circuit CSG. This operation mode can be divided into a normal DRAM access operation mode, a DRAM senoref refresh operation mode, and an access operation mode using the internal logic logic of the internal memory. A transition to the operation mode is made without a read / write request by the read / write signal R / W from the logic inside the memory Logic. Return to the normal DRAM access operation mode is performed by releasing the refresh.

In addition, transition from the self-refresh operation mode to the internal access operation mode is made when a read / write request is made from the logic inside the memory, and the return to the self-refresh operation mode is performed by the completion of the read / write. From normal DRAM access operation mode to internal access operation mode Transitions when there is a read / write request from the logic inside the memory, and the normal return to the DRAM access operation mode is performed by releasing the refresh.

FIG. 24 is an operation timing chart showing a control example of the DRAM access control circuit DAC including the internal control signal generation circuit CSG for the DRAM. In the operation control for this DRAM, as shown in FIG. 24 (a), a normal DRAM access period during which normal DRAM access can be performed, and a period between the normal DRAM access period and the normal DRAM access period. There is a DRAM self-refresh period in which DRAM self-refresh can be performed. This DRAM self-refresh period is a period in which normal access operation from the chip MF to DRA-V [is not performed.

During the DRAM self-refresh period, a self-refresh operation enable signal is applied to the internal memory logic L 0 gic based on the address strobe signal RAS and the column address strobe signal CAS in synchronization with the clock signal CK. The refresh operation is released only when there is a request for an access operation for read / write by the control signal RZW to the DRAM from the logic Logic of the memory and the logic Logic of the DRAM. Access operation from digital signal processing circuit (DSP) is possible.

The execution of the refresh operation Z access operation during the self-refresh period can be repeated in accordance with a read request by the control signal R, for example, as shown in FIG. The refresh operation can be executed during the period between the two, and the read operation can be repeated according to the write request by the control signal W. The refresh operation can be executed during the period between the write and the write, and the read operation by the control signal R can be performed. The read and write access operations can be repeated according to the output request and the write request by the control signal W, and the refresh operation can be executed during the access operation:

As described above, the chip AD DRA by the chip-VI F processor CP During the self-refresh operation for M, the logic inside the memory of the chip AD can access the DRAM, and data can be written to the DRAM in response to a write request from the logic inside the memory. Also, data can be read from the DRAM in response to a read request. Note that the access operation to the DRAM by the logic built into the memory of the chip AD during the self-refresh operation is the same when the other chip is connected to the chip AD. For example, the chip MFA or the CPU Similar effects can be expected for other semiconductor chips including. That is, the present invention can be applied to a semiconductor device having a package structure capable of performing an access operation to a chip AD DRAM from the outside and a self-refresh operation of the DRAM.

Next, a specific structure of the package according to the present embodiment will be described in detail. FIG. 25 is an overall perspective view of the package of the present embodiment, and FIG. 26 is a cross-sectional view of the package.

The package of the present embodiment seals the first chip MF (microcomputer equipped with flash memory) on which a microcomputer and a flash memory are formed in a first TCP (Tape Carrier Package) 1A and The second chip AD (DRAM on-chip logic) on which DRAM and AS IC are formed is sealed in a second TCP 1B, and these two TCP 1A and IB are vertically It has a stacked TCP structure that is superimposed and bonded together.

The first chip MF sealed in the first TCP 1A has its main surface (element formation surface) facing down in the device hole 3a opened in the center of the tape carrier 2a. And electrically connected to one end (inner lead portion) of a lead 5a formed on one surface of the tape carrier 2a via a bump electrode 4 formed on the periphery of the main surface. I have. The main surface of the chip MF is covered with a potting resin 6 for protecting the LSI (microphone computer with flash memory) formed on the main surface from the external environment.

The lead 5a formed on one surface of the tape carrier 2a has a pattern as shown in FIG. The surfaces of these leads 5a project into the device holes 3a. Except for the one end (inner lead part) that protrudes, it is covered with solder resist 7. The other end of each lead 5a is electrically connected to a through hole 8a penetrating from one surface of the tape carrier 2a to the other surface. These through holes 8a are arranged in two rows along the four sides of the tape carrier 2a, and the surface of each through hole 8a is provided with the stacked TCPs as shown in Fig. 26. Solder bumps 9, which are external connection terminals when mounting the printed circuit board on a printed wiring board, are joined.

The second TCPIB is stacked on the first TCP 1A. TCP 1A and TCPIB are tightly joined by an adhesive 10 applied to the mating surface of both. The second chip AD sealed in the TCP 1B is disposed with its main surface facing downward in a device hole 3b opened in the center of the tape carrier 2b. It is electrically connected to one end (inner lead portion) of a lead 5b formed on one surface of the tape carrier 2b via a bump electrode 4 formed on a peripheral portion of the surface. The main surface of the chip AD, potting resin 6 to protect LSI formed on the main surface (DR AM on-chip logic) from the external environment is deposited Rereru ₃

The outer diameter of the tape carrier 2b of the TCP 1B is the same as the tape carrier 2a of the TCP 1A. The dimension of the device hole 3b of the tape carrier 2b is smaller than that of the device hole 3a of the tape carrier 2a because the outer diameter of the chip AD is smaller than that of the chip MF.

The lead 4b formed on one surface of the tape carrier 2b has a pattern as shown in FIG. The other end of each lead 5b is electrically connected to a through hole 8b penetrating from one surface of the tape carrier 2b to the other surface. These through holes 8b are arranged in two rows along the four sides of the tape carrier 2b, like the through holes 8a of the tape carrier 2a. The through holes 8a of the tape carrier 2a and the through holes 8b of the tape carrier 2b are formed with the same number and the same bit, respectively, and they face each other when the tape carriers 2a and 2b are overlapped. The through holes 8a and 8b are arranged so as to overlap each other exactly. The inside of the through holes 8a and 8b is filled with solder 11, and the facing through holes 8a and 8b are electrically connected to each other via the solder 11. In the laminated TCP of the present embodiment, connection terminals (pins) common to the two chips MF and AD (that is, having the same function) are arranged at the same position on the tape carriers 2a and 2b. It is electrically connected through the through holes 8a and 8b, and is connected to the outside (printed wiring board) through the solder bump 9 joined to one end of the through hole 8a.

In FIG. 27, the numbers (1 to 144) of the connection terminals formed on the chip MF and the numbers (1 to 200) of the through holes 8a formed on the tape carrier 2a are given. In FIG. 28, the numbers (1 to 144) of the connection terminals formed on the chip AD and the numbers (1 to 200) of the through holes 8b formed on the tape carrier 2b are given. The same numbers are given to the through holes 8a and 8b arranged at the same position on the tape carriers 2a and 2b.

Table 1 shows an example of the assignment of the connection terminals for the chips MF and AD and the through holes 8a and 8b. In the table, the numbers (1 to 144) in the MF pin # column correspond to the connection terminal numbers (1 to 144) of the chip MF shown in FIG. 27, and the numbers (1 to 144) in the AD pin # column. 144) correspond to the connection terminal numbers (1 to 144) of the chip AD shown in FIG. 28. The numbers in the Via # column are the through-holes 8a, Of the numbers in 8b (1 to 200), these are the numbers assigned to the connection terminal common to one or both of the chip MF and AD.

Z2

L 9 £ OI96d £ ll3d As shown in FIGS. 27 and 28, the connection terminals common to the chips MF and AD are arranged at substantially the same positions on the chips MF and AD. As a result, the leads 5a and 5b of the tape carriers 2a and 2b can be easily routed and the lead length can be reduced, so that the data transfer of the chips MF and AD can be speeded up. Also, since the number of required through holes 8a and 8b can be minimized, the tape carrier 2a,

The package size can be reduced by reducing the outer diameter of 2b.

Although not particularly limited, each member constituting the laminated TCP of the present embodiment is formed of the following materials and dimensions.

The tape carriers 2a and 2b are made of a 75-μm-thick polyimide resin film. Leads 5a and 5b are made of 18m thick Cu (copper) foil, and the surface of one end (inner lead) is made of Au (gold) or Sn (tin). Meshes are applied. The adhesive 10 is made of polyimide resin and has a thickness of 12 μm. The solder resist 7 is made of an epoxy resin and has a thickness of 20 μm. Solder in the external connection terminal solder bump 9 and through hole 8a, 8b 1 1 is made of lead (Pb) -tin (Sn) alloy :: Chip MF and chip AD have thickness 5 It is composed of 0 m single crystal silicon, and the botting resin 6 for protecting the main surfaces thereof is composed of epoxy resin. The bump electrode 4 formed on the main surface of the chip MF and the chip AD is made of Au and has a height of 20 μπ \: That is, the stacked TCP is composed of the chip MF and the bump electrode. 4 is smaller than the thickness of the tape carrier 2a, and the total thickness of the chip AD and the bump electrode 4 is smaller than the thickness of the tape carrier 2b. It is an ultra-thin package with a thickness of 218 μιη in the stacking direction.

Next, a method of manufacturing the laminated TCP of the present embodiment will be described with reference to FIGS. 29A to 33 are (a) a cross-sectional view of TCPIB, and (b) a cross-sectional view of TCP1A.

First, as shown in Fig. 29, tape carriers 2a and 2b made of a polyimide resin film are prepared, punched out, and device holes are placed in the tape carrier 2a.

3a and through hole 8a are formed, and device hole 3b is formed in tape carrier 2b. And a through hole 8b. Note that these tape carriers 2a and 2b are long films wound on reels, and only a part (one for TCP 1A and one for TCP 113) is shown in the figure.

Next, as shown in FIG. 30, after laminating a Cu foil on one surface of each of the table carriers 2 a and 2 b, the Cu foil is wet-etched to form a lead 5 a on the tape carrier 2 a. The lead 5b is formed on the tape carrier 2b. At the same time, a Cu foil hole 12a is formed at one end of the through hole 8a, and a Cu foil hole 12b is formed at one end of the through hole 8b. In order to secure the contact area between the solder (1 1) that fills the inside of the through holes 8 a and 8 b and the leads 5 a and 5 b in the later process and prevent disconnection of the through holes, a Cu foil hole 1 2 The diameter of a is smaller than the through hole 8a, and the diameter of the Cu foil hole 12b is smaller than the through hole 8. In addition, Cu foil has a smaller thermal expansion coefficient and higher dimensional stability than tape carriers 2a and 2b made of polyimide resin, so it passes through the diameter of Cu foil holes 12a and 12b. If the holes are smaller than the holes 8a and 8b, the positioning of the tape carrier 2a and the tape carrier 2b when using the through holes 8a and 8b in the subsequent process will be highly accurate. Can be done.

Next, as shown in FIG. 31, the surface of one end (inner lead portion) of the lead 5a protruding into the device hole 3a of the tape carrier 2a and the device hole 3b of the tape carrier 2b. After applying Au or Sn plating to the surface of one end (inner lead part) of the lead 5 b that protrudes from the tape carrier 2 a, apply solder resist 7 to the lower surface of the tape carrier 2 a, and tape The adhesive 10 is applied to the lower surface of the carrier 2b.

Next, as shown in Fig. 32, the bump electrodes 4 formed on the connection terminals of the chip MF and the leads 5a of the tape carrier 2a are collectively connected by a gang bonding method. The bump electrodes 4 formed on the connection terminals of the above and the leads 5b of the tape carrier 2b are collectively connected by a gang bonding method. After the back surface of the chip MF and the chip AD is polished in advance in a wafer state, the thickness is reduced to 5 μμπι by spin etching. The bump electrode 4 is formed in the final step of the wafer process by using a stud bump bonding method. Lead 5 Since the inner leads of a and 5b are plated with Au or Sn, the lead 5a and the bump electrode 4 and the lead 5b and the bump electrode 4 are connected by Au—Au bonding or Au—S Bonded by n-eutectic bonding. The bonding between the leads 5a and 5b and the bump electrode 4 may be performed by a single point bonding method instead of the gang bonding method.

Next, as shown in FIG. 33, using a resin potting dispenser, apply the botting resin 6 to the main surface of the chip MF and the gap between the tape carrier 2a and the device hole 3a. . Similarly, a potting resin 6 is applied to the main surface of the chip AD and the gap between the tape carrier 2b and the device hole 3b.

Next, the long tape carriers 2a and 2b are separated into individual pieces using a cutting die, and then the individual tape carriers 2a and 2b are mounted in sockets and subjected to an aging inspection. Sort out. Aging of tape carriers 2a and 2b is performed by applying socket pins to the test pads formed on each part of tape carriers 2a and 2b. By the steps up to this point, TCP 1A encapsulating the chip MF and TCP 1B encapsulating the chip AD are almost completed.

Next, as shown in Fig. 34, the tape carriers 2a and 2b are overlapped so that the positions of the through holes 8a and 8b facing each other exactly match, and then heat-pressed. To form a single package of TCPs 1A and 1B: as described above, the chip MF is thinner than the tape carrier 2a, and the chip AD is thinner than the tape carrier 2b. A and TCP 1 B can be tightly joined. For positioning the through hole 8a and the through hole 8b, the above-described Cu foil holes 12a and 12b are used. There is a test pad that is formed on each part of the tape carriers 2a and 2b.

Next, as shown in Fig. 35, a solder paste made of a lead (Pb) -tin (Sn) alloy is embedded in the through holes 8a and 8b by screen printing, and the paste Is reflowed to form solder 11 1.

Thereafter, a solder bump 9 is formed at one end of the through hole 8a of the tape carrier 2a, whereby the stacked TCP shown in FIGS. 1 and 2 is completed. Solder bumps 9 are placed beforehand with the solder bump forming surface of tape carrier 2a facing up. The solder ball formed above is positioned on the through hole 8a, and then the solder ball is formed by reflow. Alternatively, the solder bumps arranged on the surface of the glass substrate may be transferred to the surface of the through hole 8a. The solder bump 9 is made of a lead (Pb) -tin (Sn) alloy having a lower melting point than the solder 11 filled in the through holes 8a and 8b.

In order to mount the thus manufactured laminated TCP on a printed wiring board, as shown in FIG. 36, the solder bumps 9 are positioned on the electrodes 15 of the printed wiring board 14, and then the solder bumps 9 are formed. I'll make a riff.

In the laminated TCP of the present embodiment, since heat generated from the chips MF and AD mainly escapes to the substrate through the solder bumps 9, when the TCPs 1 A and 1 B are laminated, a chip that generates a larger amount of heat is used. On the lower side (closer to the substrate). In the above example, the chip MF, which forms the computer with the microphone port with flash memory, has more functional blocks and generates more heat than the chip AD, which forms the DRAM on chip logic. Chip MF is arranged. In addition, arranging a chip having a large number of connection terminals on the lower side (substrate side) facilitates routing of wiring connecting the chip connection terminals and external connection terminals.

In addition, in a stacked module that generates a large amount of heat and is designed to be a system-on-chip, it is preferable that the DRAM memory cells formed in the chip AD adopt a stacked capacitor (STC) structure. . The multilayer capacitor structure has a lower thermal leakage current and higher thermal reliability than the Braina capacitor structure.In addition, the multilayer capacitor structure can prolong the refresh cycle and generate heat. It is also possible to reduce the amount.

If the heat generated by the chip is very large, a radiation fin 16 made of a metal having high thermal conductivity such as A1 may be attached to the upper part of the stacked TCP as shown in FIG. In this case, a chip that generates a large amount of heat is placed above the chip AD (closer to the radiation fins 16).

Next, another embodiment of the package of the present invention will be described.

In the manufacturing method described above, after TCP 1A and TCP 1B are overlapped, solder 11 is embedded in the through holes 8a and 8b where the directional force is combined (see Figs. 34 and 35). Force S, TCP 1 A, 1 B can be made into one package by the following method.

First, as shown in FIG. 38, TCP 1 A and TCP 1 B are individually formed according to the method described above. Next, as shown in FIG. 39, the solder paste l ip is embedded in the through hole 8a of the TCP 1A, and the solder paste 11 p is embedded in the through hole 8b of the TCP 1B. Screen printing is used for embedding the solder paste.

Next, as shown in FIG. 40, the tape carriers 2a and 2b are overlapped and heated and pressed, and the two are joined with an adhesive 10 and the solder paste lip is reflowed to form the through holes 8a and 8b. Solder 11 is formed inside b. Subsequent steps are the same as the above-mentioned manufacturing method.

In the second manufacturing method, TCP 1A and TCP 1B are temporarily attached with the adhesive force of solder paste 11p, so the stacked TCP 1A and IB are transported to a heating furnace, etc., and both are heated and pressed. In the meantime, the displacement of the facing through holes 8a and 8b can be prevented.

As another method of forming through holes 8a and 8b, tape carriers 2a and 2b are overlapped to form TCP 1A and 1B into one package, and then tape carriers 2a and 2b are drilled. Alternatively, a conductive layer may be formed inside the hole by an electroless plating method.

In addition, the chips MF and AD can be sealed by a transfer molding method instead of the botting method. In this case, first, as shown in FIG. 41, the bump electrode of the chip MF is formed according to the method described above. 4 and the leads 5a of the tape carrier 2a are electrically connected, and the bump electrodes 4 of the chip AD and the leads 5b of the tape carrier 2b are electrically connected.

Next, as shown in Fig. 42, the chips MF and AD are sealed with the mold resin 17. To seal the chips MF and AD, the tape carriers 2a and 2b are attached to the molds, respectively. Then, a plurality of chips MF and AD are respectively sealed in multiple units. Epoxy resin is used for the mold resin 17.

In the illustrated example, the entire surface of the chips MF and AD is covered with the mold resin 17, but a structure in which the back surfaces of the chips MF and AD are exposed from the mold resin 17 may be employed. In this case, instead of the usual transfer molding method, the resin processed into a sheet is applied to the upper surfaces of the tape carriers 2a and 2b and heated and pressed, so that the resin flows into the main and side surfaces of the chips MF and AD. Can also. However, in this method, it is necessary to control the resin pouring amount with high precision so that the resin does not protrude from the upper surfaces of the table carriers 2a and 2b.

In the package of the present invention, since the thickness of the mold resin 17 for sealing the chips MF and AD is extremely small, the case where the back surface of the chips MF and AD is exposed from the mold resin 17 or the entire surface of the chips MF and AD is used. If the thickness of the mold resin 17 is not uniform between the main surface and the back surface of the chip MF, AD, the heat of the chip \ 1F, AD and the mold resin 1Ί If there is a difference in expansion coefficient, TCP 1A and 1B will warp, causing chip cracks and poor connection during board mounting. Accordingly, the mold resin 17 has a low coefficient of thermal expansion, and it is necessary to select a material close to the coefficient of thermal expansion of the chips MF and AD.

Next, using a cutting die, the tape carriers 2a and 2b are singulated, and each TCP 1A and 1B is subjected to an aging inspection to select non-defective products, and as shown in Fig. 43. The tape carriers 2a and 2b are superimposed and heated and pressed together so that the positions of the facing through holes 8a and 8b exactly match, and the two are joined with an adhesive 10.Then, according to the method described above. Solder 11 is formed inside through-holes 8a and 8b, and solder bump 9 is formed at one end of through-hole 8a of tape carrier 2a to complete the laminated TCP. Alternatively, as shown in Fig. 44, TCPs 1A and 1B are stacked after filling solder 11 inside TCP 1A through hole 8a and TCP 1B through hole 8b, respectively. You can make one package.

The chip MF and the chip AD may be sealed simultaneously with the mold resin 17 at the same time. In this case, first, as shown in FIG. After electrically connecting the leads 5a of the tape carrier 2a and the bump electrodes 4 of the chip AD and the leads 5b of the tape carrier 2b, the tape carriers 2a and 2b are superimposed. And then heat and pressure-bond and bond them with adhesive 10: Then, as shown in Fig. 46, chips IF and AD are simultaneously coated with mold resin 17 After soldering, as shown in Fig. 47, solder 11 is formed inside through holes 8a and 8b according to the method described above, and solder bumps are attached to one end of through hole 8a of tape carrier 2a. _C to form 9 _:

According to the above method of sealing the chips IF and AD with the molding resin 17, the outer diameter dimension accuracy of the sealing portion is improved compared to the method of sealing the chips MF and AD with the botting resin 6. Therefore, also ₃ can be manufactured multilayer TCP of uniform shape with high dimensional stability, Ri by the be sealed collectively plurality of chip MF, the AD in multiple-shortened sealing time can do. Furthermore, by making the thickness of the mold resin 17 the same as that of the tape carriers 2a and 2b, there is no gap between TCP 1A and TCP 1B. It is possible to prevent problems such as accumulation of moisture between the layers, and it is possible to manufacture a highly reliable laminated TCP.- The laminated TCP of the present invention is replaced with a method in which external connection terminals are formed by solder bumps 9. Thus, the external connection terminals can be formed by the leads 5a and 5b. A method of manufacturing the stacked TCP will be described with reference to FIGS.

First, as shown in FIG. 48, a tape carrier 2a, 2b made of polyimide resin film is punched out to form a device hole 3a in the tape carrier 2a, and a device hole 3b in the tape carrier 2b. . The tape carriers 2a and 2b do not have the through holes 8a and 8b as described above.

Next, as shown in FIG. 49, a lead 5a is formed on the tape carrier 2a according to the above-described method, and a lead 5b is formed on the tape carrier 2b, and one end (inner lead portion) is formed. After applying Au or Sn plating to the surface of the tape carrier 2a, a solder resist 7 is applied to one surface of the tape carrier 2a, and an adhesive 10 is applied to one surface of the tape carrier 2b. The leads 5a and 5b are formed in such a length that their other ends (outer leads) can be used as external connection terminals.

Next, as shown in FIG. 50, the bump electrode 4 of the chip MF and the lead 5a of the tape carrier 2a are electrically connected according to the method described above, and the bump electrode 4 of the chip AD and the lead of the table carrier 2b are electrically connected. After electrically connecting 5b, the chips MF and AD are sealed with botting resin 6.Then, tape carriers 2a and 2b are singulated, and each TCP 1A and 1B is aged. Good products are selected by inspection. Next, as shown in FIG. 51, the TCPs 1A and 1B are made into one package by overlapping and joining the tape carriers 2a and 2b according to the method described above, and then, as shown in FIG. The tape carriers 2a and 2b supporting the other ends (outer lead portions) of the leads 5a and 5b are cut and removed.

Next, after soldering the surfaces of the other ends (outer lead portions) of the leads 5a and 5b, as shown in FIG. 53, the other ends of the leads 5a and 5b (outer lead portions) Is formed into a galling shape using a lead molding die. Leads 5a and 5b are molded simultaneously using the same mold.

To mount the multilayer TCP manufactured as described above on a printed wiring board, as shown in FIG. 54, connect the other ends (outer leads) of the leads 5a and 5b to a printed wiring board. After superimposing on the electrodes 1 5 of the lead, the solder plating is lifted . _{: At} this time, the leads 5 a and 5 b connected to the common connection terminal of the two chips MF and AD are connected to the printed wiring board 1. Connect to 4 same electrodes 15. In other words, this laminated TCP electrically connects the common connection terminals of the two chips MF and AD through the leads 5a and 5b, and externally (printed wiring) through the leads 5a and 5b. Board).

Although the illustrated stacked TCP has the main surfaces of the chips MF and AD facing upward, it may be placed facing downward. Also, the force of sealing the chips MF and AD with the botting resin 6 As shown in FIG. 55, the chips MF and AD may be sealed with the molding resin 17.

According to the above-mentioned laminated TC # in which the external connection terminals are constituted by the leads 5a and 5b, the manufacturing process is simplified as compared with the above-mentioned laminated TC # in which the external connection terminals are constituted by the solder bumps 9. Therefore, the manufacturing cost of the stacked TCP can be reduced. Also, since it is not necessary to provide the through holes 5a and 5b in the tape carriers 2a and 2b, the leads 5a and 5b can be easily routed and the manufacturing cost of the tape carriers 2a and 2b can be reduced. It can also be reduced.

Furthermore, by simultaneously forming the leads 5a of the tape carrier 2a and the leads 5b of the tape carrier 2b with the same mold, the time required for forming the external connection terminals can be reduced. Also, connect the other ends (outer leads) of the leads 5a and 5b. By overlapping and connecting the electrodes 15 on the printed wiring board 14, the area of the electrodes 15 occupying the surface of the printed wiring board 14 can be reduced, and the mounting of the stacked TCP (lead 5 a , 5b and the electrode 15) can be performed once.

The leads 5a and 5b, which constitute the external connection terminals, may be individually molded using two dies. In this case, as shown in Fig. 56 (chip MF, AD sealed with potting resin 6) and Fig. 57 (chip MF, AD sealed with molding resin 17), two chips MF and AD are sealed. The leads 5 a and 5 b connected to the common connection terminal of AD and AD are connected to the same electrode 15 of the printed wiring board 14.

In the stacked TCP shown in Fig. 58, the external connection terminal is formed by forming the other end (outer lead) of the lead 5a formed on the lower TCP 1A into a gull-wing shape, and the TCP 1A and TCP 1A The electrical connection with B is made through a _c- gull wing-shaped lead that is made through solder 11 embedded in the through holes 8a and 8b formed in the tape carriers 2a and 2b. In the above structure that forms the connection terminals, the stress applied to the connection between the stacked TCP and the printed wiring board due to the difference in thermal expansion coefficient between them is absorbed and relaxed by the deformation of the flexible lead. The connection reliability with the board is higher than the structure where the external connection terminals are composed of solder bumps.

As shown in FIG. 59, the package of the present invention can be individually mounted on the printed wiring board 14 without forming the TCP 1A and the TCP 1B into one package. In this case, although the mounting density is lower than that of the stacked TCP in which TCPs 1A and 1B are packaged in one package, the process of stacking TCPs 1A and 1B into one package is unnecessary. The manufacturing cost of the package can be reduced.

The stacked TCP of the present invention is used in a PGA (Pin Grid Array) type package as shown in FIG. 60, instead of a method in which external connection terminals are formed by solder bumps 9 and leads 5a and 5b. The external connection terminal can also be configured with pin 18. The surface of the bottle 1 8 is decorated plated such as S n (tin), the through-hole 8 a, 8 b leads have you inside of 5 a and Z or the lead 5 b and ₃ electrically connected

Further, in the laminated TCP of the present invention, the chip MF and the lead 5a and the chip AD and the lead 5b can be connected by using an anisotropic conductive film. To manufacture a laminated TCP using an anisotropic conductive film, first, as shown in Fig. 61, the device hole 3a, the through hole 8a and the lead 5a are formed in the tape carrier 2a according to the method described above. After forming device holes 3b, through holes 8a and leads 5b on the tape carrier 2b, a solder resist 7 is applied on one side of the tape carrier 2a, and one side of the tape carrier 2b is formed. Adhesive 10 is applied to the substrate.

Next, as shown in FIG. 62, the anisotropic conductive film 19a, which has been cut to the same size as the device hole 3a of the tape carrier 2a in advance, is projected into the device hole 3a. Position it on one end (inner lead part) of lead 5a. Similarly, an anisotropic conductive film 19b, which has been cut to the same size as the device hole 3b of the tape carrier 2b in advance, is provided with one end 19b of the lead 5b protruding into the inside of the device hole 3b. (Inner lead part). Next, as shown in FIG. 63, the chip MF on which the bump electrodes 4 are formed is positioned on the anisotropic conductive film 19 a with the main surface facing down, and then the anisotropic conductive film 1 is positioned. By heating and pressurizing 9a, bump electrode 4 and lead 5a are electrically connected via conductive particles in anisotropic conductive film 19a. Similarly, after the chip AD on which the bump electrode 4 is formed is positioned on the anisotropic conductive film 19 b with the main surface facing downward, the anisotropic conductive film 19 b is heated and pressed. Then, the bump electrode 4 and the lead 5b are electrically connected via conductive particles in the anisotropic conductive film 19b. Subsequently, the tape carriers 2a and 2b are separated into individual pieces, and each TCP 1 A, 1 B is subjected to aging inspection to select good products.

Next, as shown in Fig. 64, the tape carriers 2a and 2b are superimposed according to the above-described method to form TCPs 1A and 1B into one package, and then, as shown in Fig. 65, Solder 11 is filled in 8a and 8b, and solder bump 9 is formed at one end of snorkel hole 8a.

The various stacked TCPs of the present invention described above are applicable not only to the case where the chip MF and the chip AD are combined, but also to the above-described configuration examples of the chip MFA + chip D, the chip MFA + chip AD, the chip IF + chip D, and the like. Of course, you can. The stacked TCP of the present invention can also be applied to a case where three or more chips are stacked. it can,,

The stacked TC II shown in Fig. 66 has a chip MF that forms a microcomputer and a flash memory encapsulated in a TC II, and two chips D 0 ₂ that form only DRAM are connected to two chips. (1) It has a stacked TCP structure in which it is sealed in TCP 1D, and these three TCPs 1A, 1C, and 1D are vertically overlapped and joined together.

The chip MF sealed in the lowermost layer TCP 1A is placed in the device hole 3a of the tape carrier 2a with its main surface (element forming surface) facing upward, and the peripheral portion of the main surface. The tape carrier 2a is electrically connected to one end (inner lead portion) of a lead 5a formed on one surface of the tape carrier 2a via a bump electrode 4 formed on the tape carrier 2a. The chip is sealed with a mold resin 17. The lead 5a formed on one surface of the tape carrier 2a has a pattern as shown in FIG.

On top of TCP 1 A, TCP 1 C sealing chip D, is laminated, and further on top, TCP 1 D sealing chip D ₂ is laminated. Tip D sealed in TC P 1 C! Is disposed in a device hole 3c opened in the center of the tape carrier 2c with its main surface facing upward, and via a bump electrode 4 formed in the center of the main surface of the tape carrier 2c. It is electrically connected to one end (inner-lead portion) of a lead 5c formed on one surface of the tape carrier 2c. Similarly, the chip D ₂ sealed in the TCP 1 D is arranged with its main surface facing upward in a device hole 3 d opened in the center of the tape carrier 2 d. It is electrically connected to one end (inner lead portion) of a lead 5d formed on one surface of the tape carrier 2d via a bump electrode 4 formed at the center of the tape carrier 2d. These chips D and D ₂ are also sealed with the mold resin 17. The lead 5c formed on one surface of the tape carrier 2c has a pattern as shown in FIG. 68, and the lead 5d formed on one surface of the tape carrier 2d is formed as shown in FIG. It has a pattern.

The multilayer TCP is the three-chip MF, D "common D ₂ to (i.e. having the same function) through a connection terminal (pin) disposed at the same position of the tape carrier 2 a, 2 c, 2 d Electrical connection through holes 8a, 8c, 8d The lead 5a formed on the carrier 2a has a structure in which the lead 5a is commonly drawn to the outside (blind wiring board) through the other end (outer lead). The external connection terminals can be composed of solder bumps, pins, etc., in addition to the leads. _C FIG. 67 shows the connection terminal numbers (1 to 144) formed on the chip MF and the tape carrier. The number (1 to 144) of the through hole 8a formed in 2a is given. In FIG. 68, the numbers (1 to 46) of the connection terminals formed on the chip D, and the numbers (1 to 144) of the through holes 8c formed on the tape carrier 2c are given. Figure 69 is a number of connection terminals formed on the chip D ₂ (1-46) and a tape carrier 2 d to form through holes 8 d number (1 to 144) are then Togazuke. The same numbers are assigned to the through horns 8a, 8c, and 8d arranged at the same position on the tape carriers 2a, 2c, and 2d ::

If the area of the chip D have D ₂ is less than half of the area of any chip MF, as shown in FIG. 70, are arranged side by side and tip D ,, D ₂ laterally, chip D _t, co of D ₂ Connection terminals to be connected can be connected by the common lead 5e. In this way, an ultra-thin package can be realized as in the case of the above-described stacked TCP mounting two chips MF and AD.

The package of the present invention is not limited to the above-described structure, and various design changes can be made to its details. For example, as shown in Fig. 71, a structure is adopted in which the chip λ'ΙF sealed in TCP 1A and the lead 5a formed in the table carrier 2a are electrically connected by the Au wire 20. You can also.

In addition to the stacked TCP structure, for example, as shown in Fig. 72, the chip MF and chip AD are not packaged in one package, but are individually sealed in a QFP (Quad Flat package) type package and printed wiring It can also be mounted on the substrate 14.

The package according to the present invention includes devices and systems such as multimedia devices and information home appliances, for example, a force navigation system as shown in FIG. 73, a D-ROM (Compact Disk ROM) driving device as shown in FIG. 74, and FIG. It is used for a game device as shown in FIG. 1, a PDA (Personal Digital Assistance) as shown in FIG. 76, a mobile communication device as shown in FIG. Figure 73 is a functional block diagram showing an example of the internal configuration of the car navigation system. is there. This car navigation system includes a control unit, a display unit connected to the control unit, a GPS and a CD-ROM. The control unit consists of a main CPU, program EPROM (4M), work RAM (SRAM: 1M), I / O control circuit, ARTOP, image RAM (DRAM: 4M), CG (Computer Graphics) ROM ( It consists of a mask ROM: 4M), a gate array, and the like, and the display unit consists of a slave microcomputer, TFT, and so on.

In this car navigation system, the main CPU of the control unit controls according to a control program stored in a program EPROM. First, the control unit compares the position information by GPS, which measures the position of the car between the satellite and the ground station, and the map information stored on the CD-ROM via the I / O control circuit and the gate array. Input and store this information in work RAM.

Then, according to the processing program stored in the CG ROM, the processing of arranging the position of the car on the map based on the position information and the map information stored in the work RAM is performed by ARTOP, and this image information is obtained. Store in image RAM. After that, the image information stored in the image RAM is passed to the display unit, and the display unit displays the image information on a TFT screen based on the control of the computer with the slave microphone, so that the vehicle information is displayed. An image whose position is arranged on a map can be displayed.

In this car navigation system, the main CPL is configured by a processor, the program EP ROM is configured by a flash memory, and the ART〇P is configured by a logic circuit using an ASIC. The chip AD of the present embodiment can be used for this block by using an MFA, configuring the image RAM with DRA 1 and the gate array with a logic circuit using an ASIC. It is also possible to simply use a chip MF for the main CPU and program EPROM, and a chip D for the image RAM. Fig. 74 is a functional block diagram showing an example of the internal configuration of a CD-ROM drive. FIG. This CD-ROM drive has a microcomputer including a flash memory, a pre-servo circuit, a signal processing circuit, a ROM decoder, a host IZF, a pre-servo circuit, and a signal processing circuit, which are bidirectionally connected to the microcomputer. It consists of a pickup, SRAM connected in the direction, a D / A connected to the ROM decoder, and a buffer RAM connected to the host I / F. A motor M for driving a CD-ROM is connected to the signal processing circuit, and signals from the CD-ROM are read by a pickup. The rotation of this motor is controlled by the signals of the mini servo circuit and the signal processing circuit. In addition, DZA is connected to the slipper. The CD-ROM drive is connected to the host computer via the host IZF.

In this CD-ROM drive, the signal of the CD-ROM is read by a pickup under the control of a microcomputer, the read information is processed by a signal processing circuit, and the processed information is stored in an SRAM. In addition, the information stored in SRA \ i can be decoded by the R〇VI decoder, converted to an analog signal via D / A, output from the speaker, and stored in the buffer RAM. After storing temporarily, it can be output to the host computer via the host I7F.

In this CD-ROM drive device, the chip MFA of the present embodiment is used for a block portion of a microcomputer including a flash memory, a signal processing circuit, and the like, and a block portion of a buffer RAM and a host I / F. The chip AD of the present embodiment can be used. Alternatively, the chip MF can be simply used for a microcomputer part including a flash memory, and the chip D can be used for a buffer RAM part.

FIG. 75 is a functional block diagram showing an example of the internal configuration of the game device. This game machine has a main unit control unit, a speaker connected to the main unit control unit, a display RAM (SDRAM: 4 M) connected to a CD-R〇M, ROM cassette, and CRT, DRAM: 4M) and keyboard. The main unit controls are the main CP, system ROM (mask ROM: 16M), DRAM (SDRA-VI: 4M), RAM (SRAM: 256k), sound processor, graphics processor, image compression processor, I It is composed of a DA control circuit. In this game machine, the main CPU of the main unit control unit is controlled according to a control program stored in the system ROM. CD-ROM, ROM cassette Image and audio information and instruction information from the keyboard are input via the IZ〇 control circuit, and these information are stored in DRAM and RAM. The information is processed into audio and video signals using a sound processor and a graphic processor, respectively. The audio signals are output as audio from speakers, and the video signals are temporarily stored in the display RAM and then displayed on the CRT screen. Can be displayed as an image. At this time, the video signal is used by being compressed in the amount of information by an image compression processor and stored in a buffer RAM.

In this game device, the chip MFA of the present embodiment is used for blocks such as a main CPU, a system ROM, a sound processor, and a graphic processor, and the present embodiment is used for blocks such as a DRAM and an image compression processor. It is also possible to use chip AD in the form of chip MF, DRAM, RΑλ1 for the part of main CPU, system ROM, chip I) for the part of buffer RAM, etc. it can.

FIG. 76 is a functional block diagram showing an example of the internal configuration of the PDA. This PDA consists of a microcomputer including a flash memory consisting of a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit; an LCD connected to the microcomputer's graphic control circuit; Digitizer via A / D connected to power circuit, system memory (mask ROM: 16) connected to memory control circuit, IC card connected to security management circuit, IR connected to communication control circuit It consists of IF, RS-232C, PCMCIA card via PCMCIA control circuit. This microcomputer is connected to PHS, GSM, ADC, etc. from a communication control circuit via a network.

This PDA is controlled by a memory control circuit according to a control program stored in a system memory, converts information written using a digitizer into digital signals by A / D, and stores it in a handwriting input circuit. . The information stored in the handwriting input circuit can be displayed on an LCD screen after signal processing using a graphic control circuit. Information such as quality management information can also be displayed on the LCD screen via the graphic control circuit.

Furthermore, communication with PHS, GS, ADC, etc. can be performed by controlling a communication control circuit via a network, and a PCMCIA card via an IR-IF, RS_232C, PCMCIA control circuit, etc. Can also be imported into the micro-computer. Further, information of the IC card is used for security management by the security management circuit ₃

In this PDA, the chip MFA of the present embodiment is used for a block portion of a micro computer including a flash memory including a graphic control circuit, a handwriting input circuit, a memory control circuit, a security management circuit, and a communication control circuit. it is; also simply, _c can also such as by using Chi Tsu Bed D graphic control circuit, a part of the handwritten input circuit

FIG. 77 is a functional block diagram showing an example of the internal configuration of the mobile communication device. This mobile communication device consists of a CPU including flash memory, a CH codec, LCD controller / driver, and IC card connected to this CPU, and an RF / RF card connected to the CH codec and connected via a modem. It consists of an IF, a speech codec, and an LCD connected to the LCD controller / driver. An antenna is connected to the RF / IF, and a speaker and a microphone are connected to the speech codec.

In this mobile communication device, control is performed by a program stored in a flash memory of a CPU, and when a signal is received, a signal from an antenna is received via RF / IF and modulated using a modem. Then, the modulated signal is converted into an audio signal using a CH codec and a speech codec, and can be output as audio from a speaker.

Also, when transmitting a signal, contrary to the reception, the voice signal from the microphone is converted using a speech codec and CH codec, demodulated using a modem, and then transmitted from the antenna via RF / IF. can do.

In this mobile communication device, the chip MFA of the present embodiment is used for a block portion such as a CP controller and a CH codec, and an LCD controller / driver is provided. In any part, the chip AD of the present embodiment can be used. It is also possible to simply use a chip MF for the CPU part.

As described above, the semiconductor device composed of the combination of the chip MF, the chip 1FA, the chip AD, the chip D, and the like according to the present embodiment includes a power acquisition system, a CD-ROM drive, a game device, a PDA, It can be widely applied to multimedia devices such as mobile communication devices, devices and systems such as information home appliances.

Therefore, according to the present invention, the following effects can be obtained.

(1) In terms of circuit cost, the number of external connection terminals is reduced by using a package structure in which two types of chips, a chip MF using a CPU and a flash memory, and a chip D using a DRAM, are packaged separately. In addition, the mounting area can be reduced by integrating two types of chips into a single package, and the cost of semiconductor devices can be reduced: In addition, the cost of equipment and systems using this semiconductor device can be reduced. .

(2) If the chip MF and chip D each have a chip MFA or chip AD with a built-in logic circuit such as an ASIC, and if the DRAM is a synchronous DRAM, the external connection terminals must be shared. Therefore, the number of external connection terminals can be further reduced and cost can be reduced.

(3) In terms of circuit operation, weight control is unnecessary by using a chip AD equipped with a DRAM and a logic circuit such as ASIC, so that external

Since the access operation from the logic circuit to the DRAM can be performed during the DRAM self-refresh period, the speed of data transfer between the external device and the chip AD can be increased.

In particular, since the CPU itself controls the time and realizes one clock cycle, it is not necessary to exchange wait signals, so that high-speed access can be performed. Further, the speed of processing in equipment and systems using the semiconductor device can be increased.

(4) There are two types of chips: a chip AD on which DRAM and logic circuits are mounted, a chip MF on which CPU and flash memory are mounted, and a chip MFA. Even in the packaged package structure, the logic circuit can access the DRAM during the DRAM self refresh period as seen from the CPU, so data transfer between chip AD and chip MF and chip MF A is possible. Can be realized at high speed.

(5) Since wait control for exchanging weight signals is not required, the processing timing itself can be controlled from the CPU, that is, the processing timing itself can be known in the CPU program. This makes it easy to create a semiconductor device program.

(6) Using a general-purpose DRAM interface enables high-speed operation of chip AD with DRAM and logic circuits, chip MF and chip MFA with CPU and flash memory, etc. Can be directly connected.

(7) The process load is reduced by dividing DRAM, logic, flash memory, etc. with different power levels into two or more chips, so that these are mixedly mounted on one chip. As a result, the manufacturing cost of the chip can be significantly reduced.

(8) The chip mounting area is reduced by mounting two types of chips, a chip MF using a CPU and a flash memory, and a chip D using a DRAM, in an ultra-thin stacked package to form a single package. It can be significantly reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and the present invention is not limited to the scope and scope thereof. Needless to say, various changes are possible. Industrial applicability

As described above, the semiconductor device according to the present invention employs, from an MCVI approach, a first chip in which a flash memory is further formed on a microcomputer including a CPU, and further a logic circuit such as an AS IC, a DRAM, Furthermore, in a package structure in which a plurality of types of semiconductor chips, such as one or more second chips forming a logic circuit such as an AS IC, are housed in the same package so that signals can be input / output to each other, In terms of circuit, the number of external connection terminals is reduced by the functional block configuration. It is useful for semiconductor devices that can reduce the mounting area by making one type of chip into one package and can reduce costs. Furthermore, multimedia devices, information home appliances, and other devices and systems using this semiconductor device It can be widely applied to such applications.

Claims

The scope of the claims

1. A method for manufacturing a semiconductor device, comprising the following steps:

(a) After forming a device hole and a through hole in each of the plurality of tape carriers, by patterning a conductive layer formed on one surface of the tape carrier, one end protrudes into the device hole and the other end protrudes into the device hole. Forming leads connected to the through holes,

(b) bonding the lead to a connection terminal of the semiconductor chip arranged in each device hole of the plurality of tape carriers to electrically connect them, and then sealing the semiconductor chip with resin. A process of forming a plurality of tape carriers,

(c) stacking the plurality of tape carriers in the vertical direction such that the through holes overlap each other, and then forming a conductor layer inside the through holes to electrically connect the through holes. The process of forming a stacked TCP,

(d) forming an external connection terminal of the laminated TCP at one end of the through hole;

2. The method for manufacturing a semiconductor device according to claim 1, wherein a connection terminal common to a plurality of semiconductor chips mounted on the plurality of tape carriers is formed at the same position of the plurality of tape carriers. Method for manufacturing a semiconductor device, characterized in that

3. The method for manufacturing a semiconductor device according to claim 1, wherein the external connection terminal is a solder bump formed at one end of a through hole of a lowermost table carrier. Method.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the external connection terminal is formed on one surface of a lowermost tape carrier, and one end is a lead protruding outward from the tape carrier. A method for manufacturing a semiconductor device.

5. The method of manufacturing a semiconductor device according to claim 1, wherein a part of the external connection terminal is a conductive bin that is inserted into the through hole and another part protrudes outward from the tape carrier. A method for manufacturing a semiconductor device.

6. The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of semiconductor chips are provided. Manufacturing a plurality of leads drawn out from a common connection terminal to form an external connection terminal by collectively molding the leads outside of the tape carrier in a state of being superimposed on each other. Method.

7. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip has a thickness smaller than that of the tape carrier by a spin etching method after polishing a back surface in a wafer state in advance. A method for manufacturing a semiconductor device.

8. The method of manufacturing a semiconductor device according to claim 1, wherein after embedding a solder paste in the through hole by a printing method, the solder paste is reflowed to form a conductor layer inside the through hole. A method of manufacturing a semiconductor device.

9. The method for manufacturing a semiconductor device according to claim 1, wherein an electroless plating is performed inside the through hole to form a conductor layer.

10. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is sealed with a boting resin.

11. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is sealed with a monolithic resin.

12. The method for manufacturing a semiconductor device according to claim 1, comprising at least a semiconductor chip on which a CPU and a flash memory are formed, and at least one or more semiconductor chips on which a DRAM is formed. Manufacturing method _{c of} semiconductor device characterized by the above-mentioned.