KR100587041B1 - Chip scale stack package - Google Patents

Abstract

The present invention discloses a chip scale stack package. In the present invention, at least two or more semiconductor chips with bonding pads facing downwards are disposed up and down. A lead frame is bonded to the bottom surface of each semiconductor chip, and the inner lead of each lead frame is electrically connected to the bonding pad by a metal wire. Several protrusions are formed on the bottom of each lead frame by partial etching. Each semiconductor chip and lead frame are molded with an encapsulant. The outer lead of each lead frame is exposed to both sides of the encapsulant and the bottom of the protrusion is exposed to the underside of the encapsulant. Convex portions for securing the wire bonding height are formed in the sealing agent under the inner lead of each lead frame. Each convex portion of each encapsulant abuts against the encapsulant surface for semiconductor chips disposed below. The outer leads of each lead frame are electrically connected by solder balls for package connection. Solder balls for external terminals mounted on the board are mounted on the protrusions of the lower lead frame. On the other hand, in order to enhance the bonding force by increasing the contact area between the outer lead and the solder ball for connecting the package, it is preferable that through holes are formed in each outer lead up and down. In addition, the through-holes formed in the plurality of outer leads applied to any one semiconductor chip is preferably arranged in a zigzag form to prevent interference between solder balls for connecting each package.

Description

Chip scale stack package {CHIP SCALE STACK PACKAGE}

1 and 2 are cross-sectional views showing a conventional stack package.

3 is a cross-sectional view showing a chip scale stack package according to Embodiment 1 of the present invention;

4 and 5 are plan views showing two arrangement structures of through holes formed in the outer lead of the lead frame.

Figure 6 is a cross-sectional view showing a chip scale stack package according to a second embodiment of the present invention.

Figure 7 is a cross-sectional view showing a chip scale stack package according to a third embodiment of the present invention.

-Explanation of symbols for the main parts of the drawing-

10,12; Semiconductor chips 11,13; Bonding pads

20,50; Lead frames 21,51; Inner lead

22,52; Outer lead 23,53; projection part

24,54; Through hole 40,41; Metal wire

60,61; Sealing agent 70; Solder Balls for Package Connection

71; Solder balls for external terminals 72; Package connection pin

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip scale stack package, and more particularly, to a stack package in which at least two or more semiconductor chips are stacked to form a single package about the size of a semiconductor chip.

Increasing capacity of memory chips is proceeding at a rapid pace. Currently, 128M DRAM is in mass production, and mass production of 256M DRAM is expected in the near future.

As a method of increasing the capacity of a memory chip, that is, high integration, a technique of manufacturing a larger number of cells in a limited space of a semiconductor device is generally known. However, such a method requires precise fine line width. It requires a high level of technology and a lot of development time. Therefore, recently, a stacking technology that can achieve high integration in an easier way has been developed, and research on this is being actively conducted.

In the semiconductor industry, stacking refers to a technology in which at least two or more semiconductor devices are stacked vertically to double the memory capacity. Such stacking, for example, stacks two 64M DRAM devices to form a 128M DRAM class. In addition, two 128M DRAM class devices can be stacked to form a 256M DRAM class.

Two typical examples of such a stacking package are shown in cross-section in FIGS. 1 and 2.

First, the structure of the stack package shown in FIG. 1 is as follows. Two semiconductor chips (not shown) are molded with the sealing agents 1 and 2, respectively, and are stacked up and down. Only the outer leads 3 and 4 of the lead frame, which are the signal transfer medium of each semiconductor chip, are exposed from the encapsulant 1 and 2 to both sides. Each of the outer leads 3 and 4 are joined by soldering to form a structure in which two packages are stacked.

On the other hand, in the package shown in Fig. 2, only the outer lead 7 having a short length is exposed to both sides of the encapsulant 5, 6 for molding each semiconductor chip. Each outer lead 7 is soldered to a separate lead frame 8 to form a structure in which each package is laminated.

However, the stack package shown in FIG. 1 differs in the shape of the outer lead of the lead frame of the package arranged at the bottom and the outer lead of the lead frame arranged at the top. This is because the lower end of the upper outer lead should be soldered to the middle portion of the lower outer lead, and thus, there is a disadvantage in that not all lead frames are formed in the same shape but the lower lead frame needs to be changed.

On the other hand, the stack package shown in Figure 2 has a disadvantage in that the bonding force is very weak because each outer lead protruding short lead must be soldered to a separate lead frame. In addition, there is a disadvantage that a separate lead frame is required.

Accordingly, the present invention has been made to solve all the problems of the conventional chip scale stack package, and the stack can be formed while the entire lead frame is formed in the same shape. It is an object of the present invention to provide a chip scale stack package.

Another object of the present invention is to provide a stackable package without using a separate lead frame.

In order to achieve the above object, the chip scale stack package according to the present invention is configured as follows.

Embodiment 1 comprising: at least two semiconductor chips disposed so that bonding pads face in the same direction; A lead frame having an inner lead electrically connected to the bonding pad and having a plurality of protrusions formed on a bottom thereof, and an outer lead extending horizontally from the inner lead to the outside to be exposed to the outside; An encapsulant for molding the semiconductor chip and the inner leader to expose the outer lead of the lead frame and the protrusion of the inner lead; A package connecting medium comprising a pin of a conductive metal electrically connecting the respective outer leads inserted into the respective through holes of the outer leads of each lead frame exposed by the encapsulant; And solder balls for external terminals mounted in contact with the protrusion exposed from the encapsulant.

Each convex portion of each encapsulant abuts against the encapsulant surface for semiconductor chips disposed below. The outer leads of each lead frame are electrically connected by solder balls for package connection. Solder balls for external terminals mounted on the board are mounted on the protrusions of the lower lead frame. On the other hand, in order to enhance the bonding force by increasing the contact area between the outer lead and the solder ball for connecting the package, it is preferable that through holes are formed in each outer lead up and down. In addition, the through-holes formed in the plurality of outer leads applied to any one semiconductor chip is preferably arranged in a zigzag form to prevent interference between solder balls for connecting each package.

In Embodiment 2, at least two or more semiconductor chips with bonding pads facing downwards are disposed up and down. A lead frame is bonded to the underside of each semiconductor chip, and each lead frame inner lead is electrically connected to the bonding pad by a metal wire. Several protrusions are formed on the bottom of each lead frame by partial etching. Each semiconductor chip and lead frame are molded with an encapsulant. The outer lead of each lead frame is exposed to both sides of the encapsulant and the bottom of the protrusion is exposed to the underside of the encapsulant. Convex portions for securing the wire bonding height are formed in the sealing agent under the inner lead of each lead frame.

Each convex portion of each encapsulant abuts against the encapsulant surface for semiconductor chips disposed below. Through holes are formed in each of the outer leads up and down, and the package connecting pins are inserted into the respective through holes, whereby the outer leads are electrically connected. Solder balls for external terminals mounted on the board are mounted on the protrusions of the lower lead frame.

In Embodiment 3, a lead frame is bonded to the bottom surface of the lowermost semiconductor chip with the bonding pad facing downward, and the inner lead of the lead frame is electrically connected to the bonding pad by a metal wire. On the underside of the lead frame, several protrusions are formed by partial etching. The semiconductor chip and the lead frame are molded with an encapsulant. The outer lead of the lead frame is exposed to both sides of the encapsulant, and the bottom of the protrusion is exposed to the bottom of the encapsulant. A convex portion for securing the wire bonding height is formed in the encapsulant under the inner lead of the lead frame.

Meanwhile, at least one semiconductor chip is disposed on the lowermost semiconductor chip. The lead frame is bonded to the bonding pad forming surface of at least one semiconductor chip so that its inner lead is electrically connected to the bonding pad by a metal wire. The entire product is molded with encapsulant so that only the outer lid of the lead frame is exposed on both sides. The bottom of each encapsulant abuts the bottom encapsulant surface. Each outer lead exposed to both sides in the upper encapsulant is bent downward, so that its lower end is soldered to the outer lead of the other outer lead and the lower lead frame. Solder balls are mounted on the protrusions of the lowermost lead frame.

According to the above-described configuration of the present invention, several packages can be laminated while using lead frames having the same shape, and the bonding force between packages is also enhanced without requiring a separate lead frame.

Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

Example 1

3 is a cross-sectional view illustrating a chip scale stack package according to a first embodiment of the present invention, and FIGS. 4 and 5 are plan views illustrating two arrangement structures of through holes formed in the outer lead of the lead frame.

As shown in FIG. 3, the two package structures stacked up and down are the same. Therefore, only one package structure is described.

The semiconductor chips 10 and 12 are disposed such that their bonding pads 11 and 13 face downward. The lead frames 20 and 50 are bonded to the bottom surfaces of the semiconductor chips 10 and 12 through the insulating adhesives 30 and 31. The inner leads 21 and 51 of the lead frames 20 and 50 are electrically connected to the bonding pads 11 and 13 by the metal wires 40 and 41. Here, the centers of the bottom surfaces of the lead frames 20 and 50 are partially formed by partial etching, and in this embodiment, two protrusions 23 and 53 are formed. Thus, the inner leads 21 and 51 of the lead frames 20 and 50 are maintained at the original thickness of the lead frames 20 and 50.

The entire result is molded with encapsulant 60, 61. However, the outer leads 22 and 52 are exposed through both sides of the encapsulant 60 and 61, and the bottom surfaces of the protrusions 23 and 53 are exposed through the bottom surfaces of the encapsulant 60 and 61. In addition, since the metal wires 40 and 41 extend from the bottom surfaces of the inner leads 21 and 51, the convex portion 62 is formed in the encapsulant 60 and 61 under the inner leads 21 and 51 to secure the wire bonding height. 63 is formed. Typically, the encapsulant (60, 61) is formed by a transfer molding method, the encapsulant (60, 61) is soaked into the bottom of the outer leads (22, 52) and the projections (23, 53) during this process, the electrical There is a concern that a mold flash may be formed that prevents contact. In order to solve this problem, it is preferable to spray the high pressure water to the area to remove the mold flash.

Two packages of this structure are stacked. That is, the protrusion 62 of the upper encapsulant 60 abuts the surface of the lower encapsulant 61. On the other hand, for electrical connection between the upper and lower packages, the solder ball 70, which is a medium for package connection, is interposed between the outer leads 22 and 52 of the upper and lower lead frames 20 and 50 exposed to both sides, so that the upper and lower lead frames are interposed. 20 and 50 are electrically connected.

On the other hand, the bonding strength of the solder ball 70 for package connection depends largely on the contact area between the solder ball 70 and the outer leads 22, 52. Therefore, in order to expand the contact area, it is preferable that through holes 24 and 54 are formed in the outer leads 22 and 52, respectively. 4 shows through holes 24 and 54 formed in a row in a plurality of outer leads 22 and 52 arranged horizontally in one package. However, as shown in FIG. 5, when the pitch between the outer leads 22 and 52 is narrow, interference may occur between the solder balls 70 for package connection. In order to prevent this, the through holes 24 and 54 are preferably arranged in a zigzag form as shown in FIG. 5.

On the other hand, the solder ball 71 for external terminals mounted on the board is mounted on the bottom surface of the lead frame 50 protruding portion 53 of the package disposed at the bottom. Here, in order to strengthen the bonding strength between the solder ball 70 for package connection and the solder ball 71 for the external terminal, the lead frames 20 and 5 are in contact with the respective solder balls 70 and 71, that is, the outer leads. It is preferable to plate precious metals such as molybdenum, palladium, silver, copper, tungsten, nickel, vanadium, tin, cobalt, chromium and gold on the bottoms of the 22 and 52 and the protrusions 23 and 53.

As described above, the stack package according to the first embodiment has an advantage in that two packages having the same structure, particularly the same lead frame shape, are simply stacked through the solder balls 70.

In particular, since the stacking is performed only when the user desires, in the description of the present embodiment, the solder ball 71 for the external terminal is described as being formed last, but the solder ball 71 for the external terminal is formed first, If stacking is required, the other solder balls are stacked via the solder balls 70 for package connection, so that the solder balls 71 for connection are later formed. Therefore, since the solder balls 70 and 71 are typically formed through the reflow process, the solder balls 71 for the external terminals, which are frequently cracked due to thermal stress, are subjected to the reflow process twice, and more firmly. There is also an advantage in that it is joined to the projection (53).

Example 2

6 is a cross-sectional view illustrating a chip scale stack package according to Embodiment 2 of the present invention. As shown in FIG. 6, the stack package according to the second embodiment is almost the same as the stack package structure according to the first embodiment. However, in the first embodiment, the solder ball 70 is adopted as each package connection medium, but in the second embodiment, only the pin 72 is used. That is, the package connecting pin 72 is inserted into each of the through holes 24 and 54, and is firmly attached to the inner walls of the through holes 24 and 54 by soldering. The package connection pin 72 may be nickel or a copper alloy excellent in conductivity, and a lead / tin alloy is preferably plated on its entire surface. Since the structure of other components is the same as that of Embodiment 1, a repeated description is abbreviate | omitted.

Meanwhile, in Examples 1 and 2, two packages are stacked, but three or more packages having the same structure may be stacked by a package connection medium such as solder balls or pins.

Example 3

7 is a cross-sectional view illustrating a chip scale stack package according to Embodiment 3 of the present invention. As shown in Fig. 7, the package disposed at the bottom is the same as that of the first embodiment. However, the package structure disposed thereon is different from the first and second embodiments.

The package placed on top is in the form of TSOP, which has been mentioned in the prior art. That is, in the upper semiconductor chip 10, the bonding pads 11 are disposed upward. The lead frame 80 is bonded to the surface of the upper semiconductor chip 10 by the insulating adhesive 30, and the inner lead 81 thereof is electrically connected to the bonding pad 11 via the metal wire 40. . The entire product is molded with encapsulant 64 so that only the outer lid 82 of the lead frame 80 is exposed to both sides. The outer lead 82 exposed from the encapsulant 64 has a shape bent downward.

A lower end of the outer lead 82 having a downwardly bent shape is bonded to the outer lead 52 of the lead frame 50 provided in the lowermost package by soldering. Of course, it is preferable that the through hole 54 is also formed in the outer lead 52 to expand the contact area.

Meanwhile, in the third embodiment, not only two but also other packages having the same structure as the upper package may be stacked. That is, other packages having the same structure as the upper package are stacked on the upper package, and the outer lead thereof is soldered to the middle portion of the lower outer lead 82 facing in the horizontal direction, so that three or more packages can be stacked. .

As described above, according to the present invention, since each lead frame of the package to be laminated is the same shape, the lead frame does not have to be molded differently according to the up and down positions of the package.

Moreover, instead of joining each lead frame by the simple soldering method like conventionally, it joins using solder balls, and joining reliability between each lead frame is also improved.

In the above, although the preferred embodiment for implementing the chip scale stack package according to the present invention has been illustrated and described, the present invention is not limited to the above-described embodiment, and the present invention is not limited to the scope of the present invention as claimed in the following claims. Without this, any person having ordinary knowledge in the field of the present invention will be able to implement various changes.

Claims (12)

At least two semiconductor chips disposed so that the bonding pads face in the same direction; A lead frame having an inner lead electrically connected to the bonding pad and having a plurality of protrusions formed on a bottom thereof, and an outer lead extending horizontally from the inner lead to the outside to be exposed to the outside; An encapsulant for molding the semiconductor chip and the inner leader to expose the outer lead of the lead frame and the protrusion of the inner lead; A package connecting medium comprising a pin of a conductive metal electrically connecting the respective outer leads inserted into the respective through holes of the outer leads of each lead frame exposed by the encapsulant; And And a solder ball for an external terminal mounted in contact with the protrusion exposed from the encapsulant. The chip scale stack package of claim 1, wherein a conductive metal is plated on each outer lead portion in contact with the package connection medium. The chip scale stack package of claim 2, wherein the conductive metal is at least one selected from the group consisting of molybdenum, palladium, silver, copper, tungsten, nickel, vanadium, tin, cobalt, chromium, and gold. delete delete delete delete The chip scale stack package of claim 1, wherein the package connection pin is soldered to the inner wall of the through hole. The chip scale stack package of claim 7, wherein the pin for connecting the package is made of nickel or a copper alloy. 10. The chip scale stack package of claim 9, wherein the entire surface of the package connection pin is plated with an alloy of lead / tin material. A plurality of bonding pads arranged vertically with bonding pads, at least the lowest bonding pads comprising: at least two semiconductor chips facing downward; A bottom lead having an inner lead formed on the bottom surface of the bottom semiconductor chip to be electrically connected to the bonding pad and having a plurality of protrusions formed on the bottom surface thereof, and an outer lead extending horizontally outward from the inner lead to the outside and having a through hole formed therein. frame; A lowermost encapsulant for molding the lower semiconductor chip and the inner leader of the lower lead frame such that the outer lead of the lower lead frame and the protrusion of the inner lead are exposed; A solder ball mounted to contact the protrusion of the lowermost lead frame; An upper lead frame adhered to a bonding pad forming surface of the at least one upper semiconductor chip and having an inner lead electrically connected to the bonding pad of the upper semiconductor chip, wherein the outer lead extending from the inner lead is bent downwardly ; And An upper encapsulant for molding the upper semiconductor chip and the inner lead of the upper lead frame such that only the outer lead of the upper lead frame is exposed; The outer scale of the outer lead exposed from the upper encapsulant is bonded to the outer lead of the lower lead frame or the outer lead of the other upper lead frame, the chip scale stack package, characterized in that each lead frame is electrically connected. 12. The chip scale stack package of claim 11, wherein through holes for contact area expansion are formed in upper and lower portions of the outer lead portion of the lower lead frame to which the outer lead of the upper lead frame contacts.

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