JPH09252014A - Manufacturing method of semiconductor element - Google Patents
Manufacturing method of semiconductor elementInfo
- Publication number
- JPH09252014A JPH09252014A JP5932896A JP5932896A JPH09252014A JP H09252014 A JPH09252014 A JP H09252014A JP 5932896 A JP5932896 A JP 5932896A JP 5932896 A JP5932896 A JP 5932896A JP H09252014 A JPH09252014 A JP H09252014A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metal foil
- wire
- manufacturing
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子の製造方法に
係り、特に、チップ実装並みの高密度実装が可能な半導
体素子の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for manufacturing a semiconductor element capable of high-density mounting equivalent to chip mounting.
【０００２】[0002]
【従来の技術】半導体素子の従来の実装方法としては、
例えば図７に示すような方法がある。すなわち、まず、
半導体素子１を接着剤３によってリードフレーム(図示
せず)の一部であるダイパッド２上に接合し、半導体素
子１の電極(図示せず)とリードフレームの一部であるイ
ンナーリード４との間を電気的に接続するためにワイヤ
５によって結線する。(以下、インナーリード＋ダイパ
ッド＋アウターリード(後出)をもってリードフレームと
総称する)。さらに、半導体素子１及びワイヤ５等を外
部環境から保護する目的で、封止樹脂６によって封止す
る。最終的には、封止樹脂から引き出されるリードフレ
ーム(図示せず)の一部であるアウターリード７によって
外部基板等との電気的接続が可能な構造としてある。な
お、図７に示すパッケージ構造は、一般によく用いられ
る表面実装パッケージ(SOP タイプ、QFPタイプ)で、樹
脂封止パッケージの中でも比較的高密度実装が可能なタ
イプのものである。2. Description of the Related Art As a conventional mounting method for semiconductor elements,
For example, there is a method as shown in FIG. That is, first,
The semiconductor element 1 is bonded onto the die pad 2 which is a part of the lead frame (not shown) by the adhesive 3, and the electrode (not shown) of the semiconductor element 1 and the inner lead 4 which is a part of the lead frame are connected. Wires 5 are connected to electrically connect the two. (Hereinafter, the inner lead + die pad + outer lead (described later) are collectively referred to as the lead frame). Further, the semiconductor element 1, the wire 5 and the like are sealed with a sealing resin 6 for the purpose of protecting them from the external environment. Finally, the structure is such that the outer lead 7 which is a part of a lead frame (not shown) drawn from the sealing resin can be electrically connected to an external substrate or the like. The package structure shown in FIG. 7 is a commonly used surface mount package (SOP type, QFP type), which is a type capable of relatively high density mounting among resin sealed packages.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記の
ような従来の半導体素子の製造方法においては、リード
フレームを用いてアウターリードを封止樹脂の周囲に引
き出して基板と接続する構造となっていること、リード
フレームを用いたインナーリード部にワイヤボンディン
グし、インナーリードが封止樹脂の周辺にアウターリー
ドとして引き出される構造となっているため、(1) 実装
面積が大きくなり、高密度実装ができないこと、(2) リ
ードフレームの金型が高価であるため、多品種少量生産
の場合、リードフレームも高価となること、(3) アウタ
ーリードを切断、成形する必要があり、工数を要し、さ
らに、切断、成形の金型も必要となること、などの問題
点があった。However, in the conventional method of manufacturing a semiconductor element as described above, the lead frame is used to draw the outer lead around the sealing resin to connect it to the substrate. That is, the structure is such that wire bonding is performed on the inner lead part using the lead frame, and the inner lead is pulled out as the outer lead around the sealing resin, so (1) the mounting area is large and high-density mounting is not possible. (2) Since the lead frame mold is expensive, in the case of high-mix low-volume production, the lead frame is also expensive, and (3) it is necessary to cut and mold the outer leads, which requires man-hours. Further, there is a problem that a die for cutting and molding is required.
【０００４】本発明の目的は、上記従来技術の有してい
た課題を解決して、チップ実装並みの高密度実装が可能
であり、製造工数もかからず、品種の切り換えが容易
で、多品種生産に好適な半導体素子の製造方法を提供す
ることにある。The object of the present invention is to solve the problems of the prior art described above, to enable high-density mounting equivalent to chip mounting, to reduce the number of manufacturing steps, to easily switch the product type, and to An object of the present invention is to provide a semiconductor element manufacturing method suitable for production of various products.
【０００５】[0005]
【課題を解決するための手段】上記目的は、金属板上に
半導体素子を固着し、該金属板と該半導体素子とをワイ
ヤによって電気的に結線した後、封止樹脂で上記半導体
素子を封止し、上記ワイヤで結線した上記金属板の直下
の裏面を電極として基板等と電気的に接続できるように
した半導体素子の製造において、基材上に金属箔を貼り
付け、所定部分を残すように該金属箔のエッチングを行
った後、該金属箔上に半導体素子を固着し、該金属箔と
該半導体素子とをワイヤによって結線した後に該半導体
素子を封止樹脂によって封止し、上記基材上から分離し
パッケージしてなる半導体素子の製造方法とすることに
よって達成することができる。The above object is to fix a semiconductor element on a metal plate, electrically connect the metal plate and the semiconductor element with a wire, and then seal the semiconductor element with a sealing resin. Then, in the manufacture of a semiconductor element in which the back surface immediately below the metal plate connected by the wire can be electrically connected to a substrate etc. by using an electrode, a metal foil is attached on a base material to leave a predetermined portion. After etching the metal foil on, the semiconductor element is fixed on the metal foil, the metal foil and the semiconductor element are connected by a wire, and then the semiconductor element is sealed with a sealing resin. This can be achieved by providing a method of manufacturing a semiconductor element that is separated from the material and packaged.
【０００６】[0006]
【発明の実施の形態】以下、本発明の方法について、実
施の形態の例によって具体的に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the method of the present invention will be specifically described with reference to examples of embodiments.
【０００７】[0007]
【実施の形態１】まず、本発明方法によって作製した半
導体素子の構成について説明すると、図１に示したよう
に、半導体素子１は接着剤３によって金属箔８上に接合
されている。また、半導体素子１の電極(図示せず)と金
属箔８とを電気的に接続するために、ワイヤ５で結線さ
れている。さらに、半導体素子１及びワイヤ５等を外部
環境から保護するように封止樹脂６で封止されている。
また、金属箔８の下面は封止樹脂６で成形された表面に
露出する構成となっている。First Embodiment First, the structure of a semiconductor element manufactured by the method of the present invention will be described. As shown in FIG. 1, the semiconductor element 1 is bonded onto a metal foil 8 with an adhesive 3. Moreover, in order to electrically connect the electrode (not shown) of the semiconductor element 1 and the metal foil 8, they are connected by a wire 5. Further, the semiconductor element 1, the wire 5 and the like are sealed with a sealing resin 6 so as to be protected from the external environment.
The lower surface of the metal foil 8 is exposed on the surface molded with the sealing resin 6.
【０００８】次に、本発明方法の実施の手順について図
２によって説明する。まず、基材９に金属箔８を貼り付
ける(a)。次に、金属箔８を所定のパターンにエッチン
グする(b)。次に、接着剤３を用いて半導体素子１を金
属箔８の所定の位置にダイボンディングし、さらに、ワ
イヤ５によって半導体素子１と金属箔８との電気的接続
を行う(c)。次に、金型10を用いて、封止樹脂でトラン
スファモールドを行う(d)。最後に、成形された封止樹
脂を基材９から分離することによって、半導体素子１を
パッケージとして完成する。ここで、基材９について
は、金属箔８及び封止樹脂６との密着力が低く、容易に
分離が可能な状態にある必要がある(例えば、基材９と
して、テフロン材料、シリコーン材料あるいはテフロン
コーティングした金属を使用する)。ただし、密着力が
余り弱すぎると、(b) の金属箔のエッチングの際に剥離
を生じるなどの問題が発生する。Next, the procedure for carrying out the method of the present invention will be described with reference to FIG. First, the metal foil 8 is attached to the base material 9 (a). Next, the metal foil 8 is etched into a predetermined pattern (b). Next, the semiconductor element 1 is die-bonded to a predetermined position of the metal foil 8 using the adhesive 3, and the wire 5 electrically connects the semiconductor element 1 and the metal foil 8 (c). Next, the mold 10 is used to perform transfer molding with a sealing resin (d). Finally, the molded sealing resin is separated from the base material 9 to complete the semiconductor element 1 as a package. Here, the base material 9 has a low adhesion to the metal foil 8 and the sealing resin 6 and needs to be in a state where it can be easily separated (for example, as the base material 9, a Teflon material, a silicone material, or Use Teflon coated metal). However, if the adhesion is too weak, problems such as peeling may occur during the etching of the metal foil (b).
【０００９】ここで、従来技術における基板への実装の
方法について図８によって簡単に説明を加えると、アウ
ターリード７ははんだ13を介して基板11上の配線12に電
気的に接続される。また、アウターリード７は封止樹脂
６から導き出されており、さらに、樹脂内部でワイヤ５
を介して半導体素子１と電気的に接続される構造となっ
ているために、実装面積が大きくなっている。また、ア
ウターリードを切断、成形する必要があるため、製造工
程が複雑で、工数もかかることになる。Here, the mounting method on the board in the prior art will be briefly described with reference to FIG. 8. The outer lead 7 is electrically connected to the wiring 12 on the board 11 via the solder 13. Further, the outer lead 7 is led out from the sealing resin 6, and the wire 5 is further provided inside the resin.
Since the structure is electrically connected to the semiconductor element 1 via the, the mounting area is large. Further, since it is necessary to cut and form the outer leads, the manufacturing process is complicated and the number of steps is increased.
【００１０】これに対して、本発明の方法の場合、図３
に示すように、半導体素子１は接着剤３によって金属箔
８に固着され、半導体素子１と金属箔８とはワイヤ５で
電気的に接続される。さらに、金属箔８は基板11上に形
成されている配線12と直下ではんだ13によって電気的に
接続される。このような構造となっているため、従来技
術の場合と比べ、実装面積を著しく小さくすることがで
きる。また、リードフレームを使用しないため、リード
の切断や成形といった作業は発生しない。さらに、適用
品種を変換する場合、金属箔をエッチングするマスク１
枚を換えることによって対応することができ、従来技術
の場合のようにリードフレーム材料の変更やリード成形
金型の変更等を必要とせず、安価にしかも迅速に対応す
ることができる。これらのことから、自動車用半導体の
ように多品種少量生産を要する場合に好適な構成という
ことができる。また、エッチングの手法を用いているた
め、微細加工が容易であり、加工形状の自由度も高い。On the other hand, in the case of the method of the present invention, FIG.
As shown in, the semiconductor element 1 is fixed to the metal foil 8 with the adhesive 3, and the semiconductor element 1 and the metal foil 8 are electrically connected by the wire 5. Further, the metal foil 8 is electrically connected to the wiring 12 formed on the substrate 11 directly below by the solder 13. With such a structure, the mounting area can be significantly reduced as compared with the case of the conventional technique. Further, since the lead frame is not used, work such as cutting and molding the lead does not occur. Further, when converting the applicable product, the mask 1 for etching the metal foil
This can be dealt with by changing the number of sheets, and unlike the case of the prior art, it is possible to deal with the cost inexpensively and quickly without the need to change the lead frame material or the lead molding die. From these things, it can be said that it is a suitable configuration when it is necessary to produce a wide variety of products in small quantities, such as semiconductors for automobiles. Further, since the etching method is used, fine processing is easy and the degree of freedom of the processed shape is high.
【００１１】[0011]
【実施の形態２】本発明の他の実施の形態について、図
４によって説明する。実施の形態１と大きく異なる点
は、実施の形態１の場合金属箔の表面のみが露出してい
る構成となっているが、本例の場合は金属箔８が封止樹
脂６から露出していることであり、露出部分が大きくな
っているために、はんだ付け強度とはんだ付けの作業性
が向上する。Second Embodiment Another embodiment of the present invention will be described with reference to FIG. The major difference from the first embodiment is that in the first embodiment only the surface of the metal foil is exposed, but in the present example, the metal foil 8 is exposed from the sealing resin 6. Since the exposed portion is large, soldering strength and soldering workability are improved.
【００１２】製造の手順は図５に示す通りで、まず、接
着剤を用いて半導体素子１を金属箔８上の所定の位置に
接続し、さらに、金属箔の所定の位置にワイヤ５でボン
ディングを行う(a)。次に、金型10を用いて、半導体素
子１及びワイヤ５を樹脂封止する(b)(c)。なお、封止樹
脂６による封止は、図に示した金型10を用いるトランス
ファモールド法によるだけでなく、ポッティング法(デ
ィスペンス法)あるいはキャスティング法によっても良
い。最後に、金属箔８をエッチングして、所定部分のみ
を残す。The manufacturing procedure is as shown in FIG. 5. First, the semiconductor element 1 is connected to a predetermined position on the metal foil 8 using an adhesive, and further, the wire 5 is bonded to the predetermined position on the metal foil. (A). Next, the semiconductor element 1 and the wire 5 are resin-sealed using the mold 10 (b) and (c). The sealing with the sealing resin 6 may be performed by the potting method (dispensing method) or the casting method as well as the transfer molding method using the mold 10 shown in the figure. Finally, the metal foil 8 is etched to leave only a predetermined portion.
【００１３】[0013]
【実施の形態３】図６によって説明する。本例は、複数
の半導体素子１を内蔵する場合の基板11上への実装搭載
方法の例を示す。まず、内部構造的には、２個の半導体
素子１が接着剤３等によって金属箔８上に接続され、さ
らに、ワイヤ５によって金属箔８と電気的に接続されて
いる。また、半導体素子１同士の接続は、同じ金属箔８
にワイヤ５をボンディングすることによって結線してい
る。また、基板11上の配線12との接続は、はんだ13を介
して行われる。なお、図６では複数の半導体素子１を搭
載した例を示したが、チップ抵抗やチップコンデンサ等
の受動部品を金属箔８と接続し、封止樹脂６内に封止す
ることも容易に行うことができる。このように、本発明
によれば、マルチチップモジュール構造も容易に実現す
ることができる。Third Embodiment A third embodiment will be described. This example shows an example of a mounting method on the substrate 11 when a plurality of semiconductor elements 1 are built in. First, in terms of internal structure, the two semiconductor elements 1 are connected to the metal foil 8 by the adhesive 3 or the like, and further electrically connected to the metal foil 8 by the wire 5. Further, the semiconductor elements 1 are connected to each other with the same metal foil 8
The wires 5 are connected to each other by bonding. Further, the connection with the wiring 12 on the substrate 11 is performed via the solder 13. Although FIG. 6 shows an example in which a plurality of semiconductor elements 1 are mounted, it is also easy to connect passive components such as a chip resistor and a chip capacitor to the metal foil 8 and seal them in the sealing resin 6. be able to. Thus, according to the present invention, a multi-chip module structure can be easily realized.
【００１４】[0014]
【発明の効果】以上述べてきたように、半導体素子の製
造方法を本発明の製造方法とすることによって、従来技
術の有していた課題を解決して、チップ実装並みの高密
度実装が可能であり、製造工数もかからず、品種の切り
換えが容易で、多品種生産に好適な半導体素子の製造方
法を提供することができた。すなわち、薄い金属箔上に
半導体素子を搭載して、ワイヤによって半導体素子と金
属箔とを電気的に結線し、さらにワイヤボンドされた直
下の金属箔の裏面を電極として基板上の配線部とはんだ
等を介して電気的に接続する構造とすることによって、
パッケージされている構造であってもベアチップ実装並
みの高密度実装が可能となること、リードフレーム材
料、リード成形用金型を使用しないため、製造コストが
安価となり、また、工程が簡単になるため製造工数もか
からないこと、多品種少量生産に適しており、品種の切
り換えが容易であることなどの効果を得ることができ
る。As described above, by adopting the manufacturing method of the present invention as the semiconductor element manufacturing method, it is possible to solve the problems of the prior art and realize high-density mounting equivalent to chip mounting. Therefore, it is possible to provide a method for manufacturing a semiconductor element, which does not require a manufacturing man-hour, is easy to switch between different kinds of products, and is suitable for multi-product production. That is, a semiconductor element is mounted on a thin metal foil, the semiconductor element and the metal foil are electrically connected by a wire, and the back surface of the metal foil immediately below the wire bond is used as an electrode and the wiring portion on the substrate is soldered. By having a structure that is electrically connected via
Even with a packaged structure, high-density mounting comparable to bare chip mounting is possible, and because lead frame materials and lead molding dies are not used, manufacturing costs are low and the process is simple. The manufacturing man-hours are not required, it is suitable for small-lot production of a wide variety of products, and it is possible to obtain effects such as easy switching of products.
【図１】本発明の方法による実装構造の一例を示す断面
図。FIG. 1 is a sectional view showing an example of a mounting structure according to a method of the present invention.
【図２】本発明の方法による製造の手順を示す図。FIG. 2 is a diagram showing a manufacturing procedure according to the method of the present invention.
【図３】本発明の方法による実装構造を基板上に搭載し
た場合の構成を示す図。FIG. 3 is a diagram showing a configuration in which a mounting structure according to the method of the present invention is mounted on a substrate.
【図４】本発明方法の他の実施の形態を示す図。FIG. 4 is a diagram showing another embodiment of the method of the present invention.
【図５】図４の実施の形態の製造の手順を示す図。FIG. 5 is a diagram showing a manufacturing procedure of the embodiment shown in FIG. 4;
【図６】本発明方法のさらに他の実施の形態(複数の半
導体素子を搭載した場合)の構成を示す図。FIG. 6 is a diagram showing a configuration of still another embodiment of the method of the present invention (when a plurality of semiconductor elements are mounted).
【図７】従来の半導体素子の実装構造を示す図。FIG. 7 is a diagram showing a conventional semiconductor element mounting structure.
【図８】従来の実装構造を基板上に搭載した場合の構成
を示す図。FIG. 8 is a diagram showing a configuration when a conventional mounting structure is mounted on a substrate.
１…半導体素子、２…ダイパッド、３…接着剤、４…イ
ンナーリード、５…ワイヤ、６…封止樹脂、７…アウタ
ーリード、８…金属箔、９…基材、10…金型、11…基
板、12…配線、13…はんだ。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Die pad, 3 ... Adhesive agent, 4 ... Inner lead, 5 ... Wire, 6 ... Sealing resin, 7 ... Outer lead, 8 ... Metal foil, 9 ... Base material, 10 ... Mold, 11 … Board, 12… Wiring, 13… Solder.
Claims (2)
と該半導体素子とをワイヤによって電気的に結線した
後、封止樹脂で上記半導体素子を封止し、上記ワイヤで
結線した上記金属板の直下の裏面を電極として基板等と
電気的に接続できるようにした半導体素子の製造におい
て、基材上に金属箔を貼り付け、所定部分を残すように
該金属箔のエッチングを行った後、該金属箔上に半導体
素子を固着し、該金属箔と該半導体素子とをワイヤによ
って結線した後に該半導体素子を封止樹脂によって封止
し、上記基材上から分離しパッケージとして完成するこ
とを特徴とする半導体素子の製造方法。1. A semiconductor element is fixed on a metal plate, the metal plate and the semiconductor element are electrically connected by a wire, the semiconductor element is sealed by a sealing resin, and the wire is connected by the wire. In the production of a semiconductor element in which the back surface immediately below the metal plate can be electrically connected to a substrate or the like by using an electrode, a metal foil is attached onto a base material, and the metal foil is etched so that a predetermined portion is left. After that, the semiconductor element is fixed on the metal foil, the metal foil and the semiconductor element are connected by a wire, and then the semiconductor element is sealed with a sealing resin, and separated from the base material to complete a package. A method of manufacturing a semiconductor device, comprising:
を固着し、該半導体素子をワイヤによって該金属箔の所
定の位置に結線した後に封止樹脂によって封止し、上記
金属箔をエッチングして所定の部分を残すことによりパ
ッケージとして完成することを特徴とする請求項１記載
の半導体素子の製造方法。2. The semiconductor element is fixed to a predetermined position of the metal foil, the semiconductor element is connected to a predetermined position of the metal foil with a wire, and then sealed with a sealing resin, and the metal foil is etched. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the package is completed by leaving a predetermined portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5932896A JPH09252014A (en) | 1996-03-15 | 1996-03-15 | Manufacturing method of semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5932896A JPH09252014A (en) | 1996-03-15 | 1996-03-15 | Manufacturing method of semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09252014A true JPH09252014A (en) | 1997-09-22 |
Family
ID=13110176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5932896A Pending JPH09252014A (en) | 1996-03-15 | 1996-03-15 | Manufacturing method of semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09252014A (en) |
Cited By (19)
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|---|---|---|---|---|
| JPH11121646A (en) * | 1997-10-14 | 1999-04-30 | Hitachi Cable Ltd | Semiconductor package and manufacture thereof |
| JPH11195733A (en) * | 1997-10-28 | 1999-07-21 | Seiko Epson Corp | Semiconductor device and manufacture thereof, and conductive board thereof |
| KR20020009316A (en) * | 2000-07-26 | 2002-02-01 | 듀흐 마리 에스. | A Method of Manufacturing Thin Type Semiconductor Packages |
| US6498392B2 (en) | 2000-01-24 | 2002-12-24 | Nec Corporation | Semiconductor devices having different package sizes made by using common parts |
| US6858473B2 (en) | 2002-07-26 | 2005-02-22 | Nitto Denko Corporation | Method for manufacturing semiconductor device, adhesive sheet for use therein and semiconductor device |
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| US7115989B2 (en) | 2003-08-26 | 2006-10-03 | Nitto Denko Corporation | Adhesive sheet for producing a semiconductor device |
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-
1996
- 1996-03-15 JP JP5932896A patent/JPH09252014A/en active Pending
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| JPH11195733A (en) * | 1997-10-28 | 1999-07-21 | Seiko Epson Corp | Semiconductor device and manufacture thereof, and conductive board thereof |
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| US7235888B2 (en) | 2002-07-26 | 2007-06-26 | Nitto Denko Corporation | Method for manufacturing semiconductor device, adhesive sheet for use therein and semiconductor device |
| US6858473B2 (en) | 2002-07-26 | 2005-02-22 | Nitto Denko Corporation | Method for manufacturing semiconductor device, adhesive sheet for use therein and semiconductor device |
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| US8101864B2 (en) | 2005-03-17 | 2012-01-24 | Hitachi Cable, Ltd. | Electronic device substrate and its fabrication method, and electronic device and its fabrication method |
| US8230591B2 (en) | 2005-03-17 | 2012-07-31 | Hitachi Cable, Ltd. | Method for fabricating an electronic device substrate |
| US7880091B2 (en) | 2006-05-22 | 2011-02-01 | Hitachi Cable, Ltd. | Electronic device substrate, electronic device and methods for making same |
| US8230588B2 (en) | 2006-05-22 | 2012-07-31 | Hitachi Cable, Ltd. | Method of making an electronic device and electronic device substrate |
| WO2009148768A3 (en) * | 2008-06-04 | 2010-03-04 | National Semiconductor Corporation | Foil based semiconductor package |
| JP2011523213A (en) * | 2008-06-04 | 2011-08-04 | ナショナル セミコンダクタ コーポレイション | Semiconductor package based on thin foil |
| CN102057485A (en) * | 2008-06-04 | 2011-05-11 | 国家半导体公司 | Foil based semiconductor package |
| US8375577B2 (en) | 2008-06-04 | 2013-02-19 | National Semiconductor Corporation | Method of making foil based semiconductor package |
| US8341828B2 (en) | 2008-08-21 | 2013-01-01 | National Semiconductor Corporation | Thin foil semiconductor package |
| US7836586B2 (en) | 2008-08-21 | 2010-11-23 | National Semiconductor Corporation | Thin foil semiconductor package |
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| US8377267B2 (en) | 2009-09-30 | 2013-02-19 | National Semiconductor Corporation | Foil plating for semiconductor packaging |
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