KR950010112B1 - Semicondugor device method for z-line epoxy band mehtod - Google Patents
Semicondugor device method for z-line epoxy band mehtod Download PDFInfo
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- KR950010112B1 KR950010112B1 KR1019920014924A KR920014924A KR950010112B1 KR 950010112 B1 KR950010112 B1 KR 950010112B1 KR 1019920014924 A KR1019920014924 A KR 1019920014924A KR 920014924 A KR920014924 A KR 920014924A KR 950010112 B1 KR950010112 B1 KR 950010112B1
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- chip
- pad
- semiconductor device
- lead
- lead frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
Description
제1도는 종래의 반도체 장치의 단면도.1 is a cross-sectional view of a conventional semiconductor device.
제2도는 본 발명의 본드방법을 이용한 반도체장치의 단면도.2 is a cross-sectional view of a semiconductor device using the bonding method of the present invention.
제3도는 제2도의 “A”부분 확대도.3 is an enlarged view of portion “A” of FIG.
제4도는 본 발명의 실시예로, 칩에 분산배열된 패드와 리드프레임이 마운트된 것을 배선도 형태로 나타낸 설명도이다.4 is an exemplary diagram of a wiring diagram in which a pad and a lead frame mounted on a chip are mounted in an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 칩 20 : 리드프레임10: chip 20: leadframe
30 : 코팅부 40 : 회로접속부30: coating part 40: circuit connection part
41 : 패드 42 : 실버블41: Pad 42: Silverble
43 : Z－축 에폭시43: Z-axis epoxy
본 발명은 반도체 장치의 제조방법에 관한 것으로 특히, 칩의 패드부분을 분산배열하고, 분산배열된 패드부분을 제외하고 본딩용 코팅을 하며, 피드에는 실버블을 믹스한 Z－축 에폭시를 드롭 또는 어탯치하여 리드프레임과 접속시킨 후, 패키징하여 제조되도록 하는 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, the pad portion of the chip is dispersed and arranged, except that the pad portion is distributed, and the bonding coating is performed. The present invention relates to a method for manufacturing a semiconductor device that is attached to a lead frame and attached to the lead frame.
일반적으로 반도체 장치의 제조공정은 웨이퍼에서 다이싱 작업으로 칩을 분리시키고, 분리된 칩을 리드프레임에 접합(Die Attaching)하고 칩과 리드프레임을 와이어로 와이어본딩하고, 몰드수지로써 패키징하고 외부리드부에 납도금을 하여 일정형태로 리드를 포밍시키는 것으로 설명할 수 있다.In general, the manufacturing process of semiconductor devices is to separate chips from wafers by dicing, die attach the separated chips to lead frames, wire bond chips and lead frames with wires, package them with mold resins, and external leads. This can be explained by forming a lead in a predetermined form by lead plating the part.
일예로써 제1도에서 보는바와 같은 반도체장치는 LOC(LEAD ON CHIP)형태로 패키징하여 제조될 수 있는 바, 칩(1)과 리드프레임(2) 사이에 접착테이프(3)를 부착시킨 다음 일정시간 경화시켜(Curing) 칩(1)을 일정온도(200~400℃)에서 어태치하고, 이어 상기 칩(1)과 리드프레임(2)을 와이어본딩하여 패키징시켜 제조할 수 있다. 여기서 칩(1)의 패드(4)는 칩(1)의 중앙부에 배열되어 있어야 하는 한계성때문에 그에 따른 칩(1)의 소형화 흐름에 막대한 지장이 있으며, 또한 상기 칩(1)과 리드프레임(2)을 부착하기 위하여 접착테이프(3)를 사용함으로써 테이프커팅을 위한 별도의 기술 및 장치가 필요하게 되며 와이어본딩 후 이를 패키징할 때에는 와이어 스위프(Sweep) 및 인컴플리트 필(INCOMPLETE FILL) 현상이 발생되는 등 많은 문제점이 지적되고 있었다.As an example, a semiconductor device as shown in FIG. 1 may be manufactured by packaging in a lead on chip (LOC) type. The adhesive tape 3 may be attached between the chip 1 and the lead frame 2 and then fixed. After curing by curing (Curing) the chip 1 is attached at a predetermined temperature (200 ~ 400 ℃), then the chip 1 and the lead frame 2 can be manufactured by wire bonding and packaging. Here, the pad 4 of the chip 1 has a huge obstacle to the miniaturization flow of the chip 1 due to the limitation that the pad 4 of the chip 1 should be arranged at the center of the chip 1, and also the chip 1 and the lead frame 2. By using the adhesive tape (3) to attach), a separate technique and device for tape cutting are needed, and wire sweep and INCOMPLETE FILL phenomenon occurs when packaging it after wire bonding. Many problems were pointed out.
한편, 하이브리드 IC를 제조함에 있어서는, 기판위에 칩형태의 부품을 마운트 할 때에는 에폭시와 실버블이 결합되어 Z축으로 도통시키는 Z축 에폭시를 다만 패드위에 도포하여 부품이 기판의 패드와 도통되도록 제조하고 있어 사용상의 편리함을 제공하고 있으나, 패키지 제조시에는 칩의 패드 부가 중앙에 위치함으로써 상기 Z축 에폭시 본드방법을 적용시킬 수 없는 단점이 있었다.On the other hand, in manufacturing a hybrid IC, when mounting a chip-shaped component on a substrate, the Z-axis epoxy, which is connected to the Z-axis by connecting epoxy and silverble, is applied to the pad. There is provided a convenience in use, but when manufacturing the package there is a disadvantage that the Z-axis epoxy bond method can not be applied by the center of the pad portion of the chip.
본 발명은 이러한 문제점을 해결코자 하는 것으로, Z－축 에폭시 본드방법을 패키지타입의 반도체 제조공정에 적용시켜 와이어본드 공간을 줄이도록 함으로써 패키지의 두께와 크기 증을 현저히 줄일 수 있도록 함을 특징으로 한다.The present invention is to solve this problem, by applying a Z-axis epoxy bonding method to the semiconductor manufacturing process of the package type to reduce the wire bond space is characterized in that it can significantly reduce the thickness and size increase of the package .
즉, 본 발명은 리드온칩 반도체 장치를 제조하는 방법에 있어서, 칩의 패드를 내부리드의 하부에 위치토록 배열형성하고, 패드를 제외하고 본딩용 코팅을 하며, 패드부분에는 Z－축 에폭시를 드롭 또는 어탯치하여 코팅부를 이루게 하고, Z－축 에폭시와 리드프레임은 코팅부에 의해 상호 연결되도록 부착됨과 동시에 상기 X－축 에폭시에는 실버블을 믹싱하여 Z축으로만 전류가 흐르도록 제조하는 방법을 제공하려는 것이다.That is, in the method of manufacturing a lead-on chip semiconductor device, the pads of the chip are arranged to be positioned below the inner lead, the coating is performed except for the pad, and the Z-axis epoxy is dropped on the pad part. Or attaching to form a coating part, and the Z-axis epoxy and the lead frame are attached to be interconnected by the coating part, and at the same time, the X-axis epoxy is mixed with silver balls to manufacture a current flowing only in the Z axis. Is to provide.
이하 본 발명을 제2도 및 제3도를 참조하여 설명하면 다음과 같다.Hereinafter, the present invention will be described with reference to FIGS. 2 and 3.
본 발명은 칩(10)의 패드(41)가 내부리드 위치에 위치토록 패드(41)를 배열형성하고, 상기 패드(41)부를 제외한 부분을 접착성은 있으나 부도체인 본딩용 코팅층(30)으로 코팅하며, 상기 각 패드(41)에는 실버블(42)과 믹스된 Z－축 에폭시(43)를 드롭 또는 어태치하여 칩(10)과 리드프레임(20)이 상호 접착되면서 실버블(42)에 의해 도통되도록 하는 접속공정을 포함하여 이루어진 것이다.According to the present invention, the pads 41 of the chip 10 are arranged to be positioned at internal lead positions, and the portions except for the pads 41 are adhesively coated with a non-conductive bonding coating layer 30. Each of the pads 41 has a Z-axis epoxy 43 mixed with the silver balls 42 or is attached to the pads 41 so that the chip 10 and the lead frame 20 are bonded to each other. It is made including the connection process to be conducted by.
제3도는 제2도의 “A”부 상세도로써 칩(10)의 패드(41)와 리드프레임(20)과의 접속상태를 나타낸 것이며, 부도체인 Z－축 에폭시(43)에 믹스된 도체인 실버블(42)은 제3도에서 보는바와 같이 Z－축 에폭시(43)에 의해 X, Y축 방향으로는 서로 접속되지 않게 일정간격이 유지되며 설사 실버블이 X, Y축으로 일부접속된다 하여도 이는 일부에 불과하므로, X, Y축 방향으로는 도통되지 않는다. 따라서 패드(41) 윗면(1a)과 리드프레임(20) 밑면(21)을 Z방향으로 접속시켜 회적인 연결을하게 된다. 이때 Z축 에폭시(43)는 리드프레임(20)과 칩(10)을 부착시켜줌은 물론이다.FIG. 3 is a detailed view of the “A” portion of FIG. 2 showing the connection state between the pad 41 of the chip 10 and the lead frame 20. The conductor mixed with the non-conductive Z-axis epoxy 43 is shown in FIG. As shown in FIG. 3, the silver rings 42 are maintained at regular intervals by the Z-axis epoxy 43 so as not to be connected to each other in the X and Y axis directions, and the silver balls are partially connected to the X and Y axes. Even if this is only a part, it does not conduct in the X and Y axis directions. Therefore, the upper surface 1a of the pad 41 and the lower surface 21 of the lead frame 20 are connected in the Z-direction so as to be connected in a rotational manner. At this time, the Z-axis epoxy 43 attaches the lead frame 20 and the chip 10 as well.
제4도는 본 발명의 실시예로써, 칩(10)의 패드(41) 배열이 중앙부에서만 형성되는 한계성을 탈피하여 어떤 위치든지 필요에 패열이 가능하게 됨에 따라(패드(41)가 양측으로 분산내열되고, 패드(41)와 내부 리드프레임(20)이 도통되어 결선상태를 이룸을 알 수 있다) 칩(10)은 크기를 자유롭게 변경시킬 수 있게 한다.4 is an embodiment of the present invention, as the pad 41 arrangement of the chip 10 deviates from the limitation that is formed only at the center portion, so that any position can be ruptured as needed (the pad 41 is distributed to both sides with heat dissipation). It can be seen that the pad 41 and the internal lead frame 20 are connected to each other so that the connection state can be achieved. The chip 10 can be freely changed in size.
이상과 같이 본 발명은 칩의 패드를 분산배열시켜 패드를 제외한 부분을 본딩 코팅처리하고 패드부위에 실버블을 믹스한 Z축 에폭시를 어태치하여 칩과 리드프레임을 접속케 함으로써, 와이어 본딩부가 차지하는 공간을 줄이게 되고, 본 발명에 의해 수득되는 반도체장치는 두께가 줄어들고 이에따라 크기도 현저히 줄어들게 되며, 상기 리드프레임과 칩의 접착도 접착테이프로 사용하지 않아 별도의 접착테이프 절단공정이 생략되어 생산단가의 절감 및 품질의 향상을 이루며, 작업공정을 축소할 수 있다.As described above, the present invention disperses and arranges the pads of the chip to bond the coating except for the pad, and attaches the Z-axis epoxy mixed with silver balls to the pad to connect the chip and the lead frame, thereby occupying the wire bonding part. The space is reduced, the semiconductor device obtained by the present invention is reduced in thickness and accordingly significantly reduced in size, and the adhesion of the lead frame and the chip is also not used as an adhesive tape, so the separate adhesive tape cutting process is omitted, thereby reducing the production cost. Reduced work quality can be reduced and work quality can be reduced.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920014924A KR950010112B1 (en) | 1992-08-19 | 1992-08-19 | Semicondugor device method for z-line epoxy band mehtod |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019920014924A KR950010112B1 (en) | 1992-08-19 | 1992-08-19 | Semicondugor device method for z-line epoxy band mehtod |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940004790A KR940004790A (en) | 1994-03-16 |
| KR950010112B1 true KR950010112B1 (en) | 1995-09-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019920014924A KR950010112B1 (en) | 1992-08-19 | 1992-08-19 | Semicondugor device method for z-line epoxy band mehtod |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950010112B1 (en) |
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1992
- 1992-08-19 KR KR1019920014924A patent/KR950010112B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR940004790A (en) | 1994-03-16 |
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