KR100558269B1 - Metal chip scale semiconductor package and method the same - Google Patents

Abstract

The present invention includes the steps of providing a frame; Forming at least one ground electrode and a plurality of external connection electrodes on one surface of the frame; Fixing a semiconductor chip on one surface of the frame; Electrically connecting the at least one ground electrode and the plurality of external connection electrodes to a semiconductor chip, respectively; Molding the semiconductor chip, at least one ground electrode, and a plurality of external connection electrodes on one surface of the frame; It provides a method of manufacturing a metal chip scale semiconductor package comprising the step of removing the frame to expose the at least one ground electrode and the plurality of external connection electrodes and a metal chip scale semiconductor package manufactured through the same.

Metal, Semiconductor Package

Description

Metal chip scale semiconductor package and method of manufacturing the same {Metal chip scale semiconductor package and method the same}             

Figure 1a is a plan view showing a portion of a typical metal chip scale semiconductor package cut away

1B is a bottom view of a typical metal chip scale semiconductor package.

FIG. 2 is a partial cross-sectional view taken along the line II-II of FIG. 1A

3 is a flowchart illustrating a manufacturing process of a general metal chip scale semiconductor package in order;

4A to 4H are cross-sectional views illustrating a cross section taken along line II-II of FIG. 1A according to a manufacturing process sequence of a general metal chip scale semiconductor package, respectively.

Figure 5a is a plan view showing a cut away a portion of the metal chip scale semiconductor package according to the present invention

5B is a bottom view of a metal chip scale semiconductor package according to the present invention.

6 is a partial cross-sectional view taken along the line VI-VI of FIG. 5A

7 is a flow chart showing the manufacturing process of the metal chip scale semiconductor package according to the present invention in order

8A to 8F are cross-sectional views illustrating a cross section taken along the line VI-VI of FIG. 5A according to a manufacturing process sequence of the metal chip scale semiconductor package according to the present invention, respectively.

9 is an enlarged partial view of the circle of FIG. 8C in an enlarged manner;

<Description of the symbols for the main parts of the drawings>

111 semiconductor chip 111a adhesive

113: external connection terminal 113a: external connection electrode

113b: solder terminal 115: ground electrode

117: molding 119: wire

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packaging method of a semiconductor chip and a semiconductor package manufactured by the same, and more particularly to a metal chip scale semiconductor package and a method of manufacturing the same. It is about.

The semiconductor package is a commercial name for a memory device including a semiconductor chip, and is used as an important functional device that is mounted on a substrate such as a printed curcuit board (PCB) to implement a circuit of an electronic information device.

On the other hand, in recent years, various electronic information devices require a large memory due to high speed and high functionality, and have been in a trend of being lighter and smaller in size. Therefore, a new packaging method that can realize thin and small size and multi-pinning of semiconductor packages has become an important topic. Currently, the semiconductor package is a so-called metal CS package that is thin and small so that the size of the semiconductor package is almost the same as that of a semiconductor chip. Metal Chip Scale Packaging) technology is attracting attention.

As a result of this metal CS technology, a bumper chip carrier (BCC) semiconductor package of Fujitsu, Japan, introduced at SEMICON Korea Technical Symposium 98, is a good example, which will be described in detail with reference to the accompanying drawings. .

FIG. 1A is a plan view showing an internal structure of a typical metal chip scale semiconductor package 1 cut along an X-X line, and FIG. 1B is a bottom view thereof. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. 1A, which has a block shape such as a circle or a rectangle in appearance.

More specifically, the metal chip scale semiconductor package 1 includes a semiconductor chip 11, a plurality of external connection terminals 13 and at least one ground electrode 15 electrically connected thereto. And a plurality of moldings (17) of the exterior which accommodate and enclose the semiconductor chip 11 in a state in which the plurality of external connection terminals 13 and the ground electrodes 15 are exposed to the outside, respectively. In this case, the external connection terminal 13 and the ground electrode 15 are respectively connected to the semiconductor chip 11 through a plurality of Au wires 19 into the molding 17.

As a result, the metal chip scale semiconductor package 1 includes a semiconductor chip 11, a plurality of external connection terminals 13 and at least one ground electrode 15 connected to the semiconductor chip 11 by wires 19, respectively. And a molding 17 surrounding the wire 19 and the semiconductor chip 11 in a state in which they are exposed to protect from an external impact.

Therefore, when the metal chip scale semiconductor package 1 is mounted on a circuit board such as PCB, the plurality of external connection terminals 13 are connected to other electrical elements by soldering or the like, and at least one ground electrode 15 Are grounded respectively.

In this case, reference numeral 11a in FIG. 2 denotes an adhesive for fixing the semiconductor chip 11, and may be exposed to the bottom of the molding 17, which will be described later through a manufacturing process. It can be easily understood.

On the other hand, the manufacturing method of the metal chip scale semiconductor package 1 is simply, after forming a plurality of external connection terminals 13 and at least one ground electrode 15 on one surface of a frame on a plate, and then The semiconductor chip 11 connected to the wire is fixed and a molding 17 surrounding the semiconductor chip 11 is formed. And finally removes the frame.

3 is a flowchart illustrating a manufacturing process of a general metal chip scale semiconductor package, and FIGS. 4A to 4H are cross-sectional views taken along line II-II of FIG. 1A, respectively. Process cross-sectional view showing.

First, the plate-like frame 2 as shown in FIG. 4A is provided. (St1)

The frame 2 is a substrate made of a metal material such as Cu, similar to a conventional lead frame, and the thickness k is generally about 250 micrometers in consideration of half etching described later. . As will be described later, the thickness of the frame 2 has a very important meaning in a metal chip scale semiconductor package.

Subsequently, a first photoresist pattern is formed on the frame 2 through a first photo lithography process (st2), which is a first method of applying photoresist to one surface of the frame 2. A photoresist coating step st2a and an exposure and developing step st2b for exposing or hiding the photoresist in the selected area using a first mask and then removing it. As a result, as shown in FIG. 4B, a first photoresist pattern 4a including a frame 2 and a plurality of first holes 6a exposing the frame 2 to one surface thereof is formed.

In addition, a predetermined etchant is used to etch the frame 2 exposed to the plurality of first holes 6a. In particular, only a portion of the upper end of the portion exposed to the first hole 6a is removed. Half etching is performed to form grooves 13a having a cave shape (st 3: see FIG. 4C).

In addition, by first plating the metal material to be filled in each of the grooves 13a, the external connection terminal 13 is formed as shown in FIG. 4D. (St4) The external connection terminal 13 is formed by stacking several kinds of metal films. In general, for example, a gold (Au) film is interposed on the outermost surface, which is soldered to an external circuit or wire-bonded with a semiconductor chip, and a palladium (Pd) and / or nickel (Ni) film is interposed therebetween. Can be.

Next, as shown in FIG. 4E, a frame 2 and an external connection electrode 13 formed by injecting a metal material into each of the surfaces of the frame 2 are formed through a first cleaning process of removing residual photoresist and removing impurities. (St5)

Then, the second photolithography process proceeds to one side of the frame 2 again (st6), which is the second photoresist coating process st6a for applying photoresist to one side of the frame 2 as in the first case, A second exposure and development process st6b is used to remove the photoresist of the double selected region using the second mask.

Accordingly, a second photoresist pattern 4b having at least one second hole 6b exposing a part of one surface of the frame 2 is formed, and metal such as gold is second plated into the second hole 6b. By filling, the ground electrode 15 is formed (st7: Fig. 4f).

The remaining photoresist is then stripped and a second cleaning step is performed to remove impurities. (St8)

As described above, in a state in which a plurality of external connection terminals 13 and at least one ground electrode 15 are formed on one surface of the frame 2, the semiconductor chip 11 is formed on one surface of the frame 2 through an adhesive 11a or the like. (St9) and the semiconductor chip 11, the external connection terminal 13, and the ground electrode 15 are bonded by wire 19, respectively. (St10: Fig. 4G).

Thereafter, the semiconductor chip 11, the external connection terminal 13 and the ground electrode 15, and a molding 17 covering the wire 19 are formed. (St11: Fig. 4h) This is a mold molding using an epoxy resin Or it can be implemented by a method such as potting (potting).

Finally, the frame 2 is etched and removed, so that the bump chip carrier peninsula body package in which the external connection terminal 13 protrudes to the bottom and the ground electrode 15 is exposed as shown in FIG. 2 is completed.

Meanwhile, in the above description, in order to increase process efficiency, a plurality of metal chip scale semiconductor packages may be manufactured at the same time with respect to a large area frame, and in this case, a cutting process of cutting and separating them may be followed. (St13)

However, the general metal chip scale semiconductor package described above has a disadvantage in that the manufacturing process is complicated by going through at least two photolithography processes. In other words, since the first photolithography process (st2) for the external connection terminal 13 and the second photolithography process (st6) for the ground electrode 15 are required, the overall manufacturing process becomes very complicated, which in turn Caused to increase manufacturing cost

In addition, there is a disadvantage in that a large amount of etchant and a long time is required to remove the frame 2 by etching. Referring to the above description, it can be seen that the thickness of the frame 2 should be at least greater than the height of the external connection terminal 13, and for this purpose, the thickness is generally 250 micrometers or more. However, in subsequent processes (see st12) all of these frames must be removed, requiring a large amount of etchant and long etching time.

The waste of resources, as well as the disadvantages of lowering the manufacturing yield, environmental pollution is very high.

Also, as is well known, the half-etching of the st 3 stage is difficult to control uniformity, and thus, a phenomenon in which the thickness of the external connection terminal 13 is uneven is frequently observed.

The present invention has been made to solve the above problems, it is possible to implement a reliable device while simplifying the manufacturing process of the metal chip scale semiconductor package, and also to increase the manufacturing yield and raw material cost by using a thinner frame A metal chip scale semiconductor package and a method of manufacturing the same, which can reduce the amount of pollution and, in particular, reduce environmental pollution, will be described.

In particular, it is an object of the present invention to provide a metal chip scale semiconductor package which can be manufactured without performing half etching and a method of manufacturing the same.

In order to achieve the above object, the present invention provides a method of manufacturing a metal chip scale semiconductor package, comprising the steps of: providing a frame; Forming at least one ground electrode and a plurality of external connection electrodes on one surface of the frame; Fixing a semiconductor chip on one surface of the frame; Electrically connecting the at least one ground electrode and the plurality of external connection electrodes to the semiconductor chip, respectively; Molding the semiconductor chip, at least one ground electrode, and a plurality of external connection electrodes on one surface of the frame; And removing the frame such that the at least one ground electrode and the plurality of external connection electrodes are exposed.

At this time, after the step of removing the frame, characterized in that it further comprises any one of the plating step selected from the solder dipping or the solder ball attach to grow and protrude the exposed external connection electrode.

In addition, forming one or more ground electrodes and a plurality of external connection electrodes on one surface of the frame may include applying photoresist to one surface of the frame; Forming a photoresist pattern including a plurality of holes exposing the frame through exposure and development using a mask; Laminating and plating metal at least twice so as to fill each hole to form at least one ground electrode and a plurality of external connection electrodes; And removing the photoresist pattern.

In the step of electrically connecting the at least one ground electrode and the plurality of external connection electrodes to the semiconductor chip, respectively, the semiconductor chip, the at least one ground electrode and the plurality of external connection electrodes are each made of Au. It is characterized in that the bonding of the wire.

In addition, the step of removing the frame, characterized in that implemented by dipping etching to immerse the frame in an etchant.

In addition, the material of the frame is characterized in that it is made of any one selected from Cu, Fe or Cu alloy, Fe alloy.

The at least one ground electrode and the plurality of external connection electrodes may each include a first Au metal film in contact with one side of the frame; And a second Au metal film to which the wire is bonded.

A first Ni metal film interposed between the first Au metal film and the second Au metal film, the first Ni metal film being in contact with one surface of the first Au metal film; A second Ni metal film in contact with the second Au metal film; And a Cu metal film interposed between the first Ni metal film and the second Ni metal film.

In addition, the present invention provides a metal chip scale semiconductor package manufactured by the above method, hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

First, FIG. 5A is a plan view illustrating the internal structure of the metal chip scale semiconductor package 101 according to the present invention along the line XX so as to easily understand its internal structure. FIG. 5B is a bottom view thereof, and FIG. Sectional drawing which cut along the VI-VI line.

Referring to these, the metal chip scale semiconductor package 101 according to the present invention includes a semiconductor chip 111, a plurality of external connection terminals 113 and at least one connected to the semiconductor chip 111 by wires 119, respectively. The above-described ground electrode 115 and a molding 117 which surrounds the wire 119 and the semiconductor chip 111 in a state where they are exposed and protects from an external impact.

Therefore, the external connection terminal 113 may be connected to other electrical elements through a soldering method, and at least one or more ground electrodes 115 may be grounded, respectively, and may be mounted on a circuit board such as a PC.

Meanwhile, reference numeral 111a in FIGS. 5B to 6 indicates that an adhesive for fixing the semiconductor chip 111 may be exposed to the bottom surface of the molding 117.

The structure of the metal chip scale semiconductor package 101 according to the above description may be similar to the general case, but is characterized in that the manufacturing method is very different. The external connection electrode 113a and at least one ground electrode 115 are formed, and the semiconductor chip 111 is fixed on the same plane.

The external connection electrode 113a and the ground electrode 115 may have an island shape.

Subsequently, the electrodes 113a and 115 are electrically connected to the semiconductor chip 111, and then, the semiconductor chips 111 and moldings 117 are formed to surround the electrodes 113a and 115.

And it completes by removing a frame so that each electrode 113a, 115 is exposed.

Hereinafter, with reference to the accompanying drawings, first, Figure 7 is a flow chart showing a manufacturing process sequence of a metal chip scale semiconductor package according to the present invention, Figures 8a to 8f, respectively, according to the VI-VI line of Figure 5a Process sectional drawing which shows the cross section cut along this.

First, a frame 112 on a plate as shown in FIG. 8A is provided. (St1)

The frame 112 may be a substrate made of any one metal selected from Cu, Fe, Cu alloy, and Fe alloy. In particular, the thickness k is preferably in the range of 1 to 25 micrometers. Of course, it is not limited to this and may be thicker.

This is a very small value compared to the case where a substrate having a thickness of 250 micrometers or more is used as in the prior art. Since the half etching is not used in the method of manufacturing a metal chip scale semiconductor package according to the present invention, a frame having a thinner thickness is used. It can be easily understood by those skilled in the art through the following description that can be implemented a reliable device even using.

Subsequently, a photoresist pattern is formed on the frame 112 through a photolithography process (st2), which is a photoresist coating process st2a for applying photoresist to one surface of the frame 112 and a region selected using a mask. And exposing and concealing the photoresist of the photoresist and then removing the photoresist.

In this case, as shown in FIG. 8B, a photoresist pattern 114a including a plurality of first holes 116a exposing the frame 112 and at least one second hole 116b is formed on one surface of the frame 112. The plurality of first holes 116a and the at least one second hole 116b are for forming the external connection electrode and the ground electrode according to the present invention, respectively.

Subsequently, a plurality of external connection electrodes 113a and at least one ground electrode 115 are formed by filling a metal material into each of the holes 116a and 116b, which can be implemented by a plating method. 8c)

In this case, it is particularly preferable that each of the electrodes 113a and 115 form a structure in which various kinds of metals are stacked. Referring to FIG. 9, which is an enlarged view of the circle of FIG. 8C, in particular, each electrode has one surface of the frame 112. The first Au metal film 120a of the lowermost layer and the second Au metal film 120b of the uppermost layer are included so as to contact each other.

More preferably, metal films such as Cu and / or Ni may be interposed between the first Au metal film 120a and the second Au metal film 120b, respectively. The first Ni metal film 120c stacked on the 1 Au metal film 120a, the Cu metal film 120e stacked on the upper portion thereof, and the lower surface of the first Au metal film 120b stacked on the first Au metal film 120a and in contact with the bottom surface of the second Au metal film 120b. The second Ni metal film 120d may be included.

Therefore, the first and second Ni metal films 120c and 120d, and the first and second Au metal films 120a and 120b, respectively, may be sequentially stacked around the center Cu metal film 120e. In particular, the center Cu metal film 120e has the largest thickness among the metal films to be stacked and is preferably formed within the range of 5 to 150 micrometers, but is not limited thereto.

Returning to FIG. 8D, the cleaning process of peeling the residual photoresist and removing impurities is performed on the frame 112 on which the external connection electrode 113a and the ground electrode 115 of the above-described laminated structure are formed. The semiconductor chip 111 is fixed to the one surface of the frame 112 through an adhesive 111a, and then (st5), the semiconductor chip 111, the external connection electrode 113a and the ground electrode 115 are electrically connected to each other. Connect with

As the connection method, bonding through the Au wire 119 is possible similarly to the general case. (St6)

Therefore, in this case, as shown, the frame 112, the plurality of external connection electrode 113a and at least one ground electrode 115 formed in an island shape on one surface of the frame 112 and the same plane The semiconductor chip 111 is fixed on the electrode, and each of the electrodes 113a and 115 and the semiconductor chip 111 are bonded to each other through the wire 119.

Thereafter, the semiconductor chip 111, the external connection electrode 113a and the ground electrode 115, and the molding 117 covering the wire 119 are formed. (St7: Fig. 8e) This is an epoxy resin as in the general case. Method such as mold molding or potting using can be used.

Finally, the frame 112 is removed. Preferably, the external connection electrode 113a and the ground electrode 115 are molded 117 by removing by the dipping etching method of dipping and etching in a predetermined etchant. ) The metal chip scale semiconductor package exposed to the bottom is completed (st8).

Compared with the metal chip scale semiconductor package according to the present invention completed through the above process and the general, in particular, in the case of the present invention, a plurality of external connection electrode 113a is exposed only to the bottom surface of the molding 117, it does not particularly protrude Although there is a difference in that, even though the plurality of external connection electrodes 113a are simply exposed to the bottom of the molding 117, there is no problem in mounting them on a circuit board and connecting them with other electrical elements.

In this case, for reference, the reason why the multilayer structure of FIG. 9 is used as the plurality of external ground electrodes 113a and at least one ground electrode 115 may be based on a portion of the portion connected to the wire 119 and an external electrical element. In order to improve the soldering characteristics, the first Au metal film 120a and the second Au metal film 120b are positioned at the outermost surfaces, respectively.

However, for easier connection, a solder dipping or solder ball attach to immerse the metal chip scale semiconductor package according to the present invention in the state of FIG. 8F in the electrolyte and grow the solder to extend the external connection electrode 113a. If one of the plating processes selected from the solder ball attach is added, the device having the same shape as that of FIG. 6 and the general metal chip scale semiconductor package can be easily implemented. (st9)

In FIG. 6, reference numeral 113b indicates a grown solder terminal, and the solder terminal 113b and the external connection electrode 113a together form an external connection terminal 113.

Meanwhile, in the above description, in order to increase process efficiency, a plurality of metal chip scale semiconductor packages may be manufactured at the same time for a large area frame, and in this case, a cutting process of cutting and separating them may be followed. (St10)

In summary, when the manufacturing method of the metal chip scale semiconductor package according to the present invention is compared with the general case, in particular, the present invention may implement a device having the same configuration without using half etching. In addition, only one photolithography process is performed by implementing a plurality of external connection electrodes and at least one ground electrode in the same process sequence.

Therefore, even a simpler process can implement a metal chip scale semiconductor package of the same configuration.

According to the present invention, it is possible to simultaneously perform pattern formation and functional plating by one plating process, and to realize external connection electrodes and ground electrodes through one photolithography process, thereby greatly simplifying the overall process to greatly increase productivity. There is an advantage that can be improved.

In addition, since the present invention does not use half etching, there is no need to worry about side effects due to the decrease in uniformity characteristics expected in the conventional half etching technique, so that a large number of metal chip scale semiconductor packages can be simultaneously manufactured in a large area frame. Even precise fine patterns can be implemented.

In addition, the present invention, unlike the prior art, the contact area between the molding material and the terminal is relatively large, and has excellent characteristics of reliability in semiconductor assembly.

In addition, the present invention can manufacture a device having excellent characteristics without half etching, so that the amount of etchant used is greatly reduced, thereby improving the environmental pollution and process yield.

Claims (9)

As a method of manufacturing a metal chip scale semiconductor package, Providing a frame; Forming at least one ground electrode and a plurality of external connection electrodes including a first Au metal film in contact with the surface and a second Au metal film stacked on the first Au metal film; Fixing a semiconductor chip on one surface of the frame; Electrically connecting the at least one ground electrode and the plurality of external connection electrodes to a semiconductor chip through wire bonding; Molding the semiconductor chip, at least one ground electrode, and a plurality of external connection electrodes on one surface of the frame; Etching and removing the frame such that the at least one ground electrode and the plurality of external connection electrodes are exposed. Method of manufacturing a metal chip scale semiconductor package comprising a The method according to claim 1, After removing the frame, Any one plating step selected from solder dipping or solder ball attach to grow and expose the exposed external connection electrode. Method of manufacturing a metal chip scale semiconductor package further comprising The method according to claim 1, Forming at least one ground electrode and a plurality of external connection electrodes on one surface of the frame, Applying a photoresist to one surface of the frame; Forming a photoresist pattern including a plurality of holes exposing the frame through exposure and development using a mask; Laminating and plating metal at least twice so as to fill the respective patterns to form at least one ground electrode and a plurality of external connection electrodes; Removing the photoresist pattern Method of manufacturing a metal chip scale semiconductor carrier comprising a. The method according to claim 1, Electrically connecting the at least one ground electrode and the plurality of external connection electrodes to the semiconductor chip through wire bonding, respectively; The wire bonding method of manufacturing a metal chip scale semiconductor package, characterized in that using the Au wire The method according to claim 1, Removing the frame, Method of manufacturing a metal chip scale semiconductor package implemented by etching the frame using an etchant The method according to claim 1, The material of the frame is a method of manufacturing a metal chip scale semiconductor package consisting of any one selected from Cu, Fe or Cu alloy, Fe alloy The method according to claim 1, Interposed between the first Au metal film and the second Au metal film, A first Ni metal film in contact with the first Au metal film; A second Ni metal film in contact with the second Au metal film; Cu metal film interposed between the first Ni metal film and the second Ni metal film Method of manufacturing a metal chip scale semiconductor package further comprising Metal chip scale semiconductor package manufactured by any one of claims 1 to 7. delete

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