KR100259079B1 - Semiconductor package and method for fabricating the same - Google Patents
Semiconductor package and method for fabricating the same Download PDFInfo
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- KR100259079B1 KR100259079B1 KR1019980000451A KR19980000451A KR100259079B1 KR 100259079 B1 KR100259079 B1 KR 100259079B1 KR 1019980000451 A KR1019980000451 A KR 1019980000451A KR 19980000451 A KR19980000451 A KR 19980000451A KR 100259079 B1 KR100259079 B1 KR 100259079B1
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- lead frame
- semiconductor chip
- wire
- bonding pad
- lead
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
본 발명은 반도체 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 경박단소화 한 새로운 타입의 반도체 패키지를 제공하기 위한 것이다.The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to provide a new type of semiconductor package that is light and thin.
도 1은 표면 실장형 반도체 패키지인 SOP(Small Outline Package)를 나타낸 것으로서, 일반적인 반도체 조립공정의 개요에 대해 SOP타입의 반도체 소자를 예로들어 설명하면 다음과 같다.FIG. 1 illustrates a small outline package (SOP), which is a surface mount semiconductor package, which is described below with reference to an SOP type semiconductor device for an outline of a general semiconductor assembly process.
먼저, 전기적 회로가 형성된 웨이퍼를 각각의 단일 칩으로 분리하는데, 이때 Si(실리콘)는 모스경도 7로서 딱딱하고 깨지기 쉬운 성질을 갖고 있으므로 웨이퍼의 제조시 미리 분리할 라인에 절단하기 위한 물질을 넣어두고 이 분리라인을 따라 브레이크 응력을 가해 파괴, 분리시키는 방법을 취하는 경우가 많다.First, the wafer on which the electrical circuit is formed is separated into each single chip, and Si (silicon) has a Mohs hardness of 7 and is hard and brittle, so that a material for cutting is placed in a line to be separated in advance in manufacturing the wafer. In many cases, a break stress is applied along this separation line to break and separate.
또한, 분리된 각각의 반도체 칩은(1) 리드프레임의 칩부착부인 다이패드(11)에 본딩되고, 이때의 접합방법은 Au-Si 공정(共晶)법, 납땜법, 수지접착법 등이 있으며 용도에 따라 알맞은 방법이 선택되어 사용된다.In addition, each of the separated semiconductor chips (1) is bonded to the die pad 11, which is a chip attaching part of the lead frame, and the bonding method is Au-Si, soldering, resin bonding, or the like. The proper method is selected according to the application.
한편, 전술한 바와같이 반도체 칩(1)을 리드프레임의 다이패드(11)에 접착하는 목적은 조립이 완료된 후 기판(8)에 실장시키기 위해서 뿐만 아니라 전기적 입출력단자나 어스를 겸하는일도 있으며 소자의 동작시 발생하는 열의 방열통로로서도 필요로하는 경우가 있기 때문이다.On the other hand, as described above, the purpose of adhering the semiconductor chip 1 to the die pad 11 of the lead frame is not only to be mounted on the substrate 8 after assembly is completed, but also to serve as an electrical input / output terminal or earth. This is because the heat dissipation path of heat generated during operation may also be required.
상기와 같이 반도체 칩(1)을 본딩한 후에는 칩과 리드프레임의 인너리드(9)를 와이어(5)로 본딩하므로써 연결하게 되며, 와이어 본딩의 방법으로 플라스틱 봉함 팩키지에서는 일반적으로 금선을 사용한 열압착법 또는 열압착법과 초음파법을 혼용한 방법이 주로 이용되고 있다.After bonding the semiconductor chip 1 as described above, the inner lead 9 of the chip and the lead frame is bonded by the wire 5, and in the plastic encapsulation package as a method of wire bonding, heat is generally used using a gold wire. The compression method or the method which mixed the thermocompression method and the ultrasonic method is mainly used.
또한, 와이어 본딩에 의해 칩(1)과 인너리드(9)가 전기적으로 연결된 후에는 칩을 고순도의 에폭시 수지를 사용하여 성형 봉합하는 몰딩공정이 수행되는데, 이때 사용되는 에폭시 수지는 집적회로의 신뢰성을 좌우하는 중요한 요소이며, 수지의 고순도화와 몰딩시 집적회로에 주어지는 응력을 저감시키기 위한 저응력화 등의 개선이 추진되고 있다.In addition, after the chip 1 and the inner lead 9 are electrically connected by wire bonding, a molding process of forming and sealing the chip using a high-purity epoxy resin is performed. In addition, the improvement of the high purity of the resin and the reduction of the stress for reducing the stress applied to the integrated circuit during molding are being promoted.
그리고, 상기한 공정이 완료된 후에는 IC 패키지를 소켓이나 기판(8)에 실장하기 위해 아웃리드(out lead)를 소정의 형상으로 절단(Trimming)하고 성형(Forming)하는 공정이 행해지며, 아웃터리드(10)에는 실장접합성(납땜성)을 향상시키기 위해 도금이나 납딥(dip)이 처리된다.After the above process is completed, a process of trimming and forming an out lead into a predetermined shape is performed to mount the IC package on the socket or the substrate 8. Plating or lead dip is applied to (10) in order to improve mounting bondability (solderability).
한편, 이와 같이 제조되는 반도체 패키지는 끊임없이 경박단소화를 추구하고 있으며, 이를 위한 노력이 지속되고 있으나, 종래의 반도체 패키지는 와이어 본딩이 반도체 칩(1)과 리드프레임(3)의 칩 외부영역 사이에 이루어지므로 인해, 반도체 패키지를 경박단소화하는 데 한계가 있었다.On the other hand, the semiconductor package manufactured as described above is constantly pursuing light and small size, and efforts for this continue, but in the conventional semiconductor package, wire bonding is performed between the semiconductor chip 1 and the chip outer region of the lead frame 3. Due to this, there was a limit to light and small sized semiconductor package.
본 발명은 상기한 제반 문제점을 해결하기 위한 것으로서, 반도체 칩의 면적 내에서 와이어 본딩 및 봉지공정이 이루어지도록하여 반도체 패키지를 경박단소화 한 새로운 타입의 반도체 패키지를 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a new type of semiconductor package in which the semiconductor package is made thin and short by allowing wire bonding and encapsulation processes to be performed within the area of the semiconductor chip.
도 1은 종래 반도체 패키지중의 일예를 나타낸 사시도1 is a perspective view showing an example of a conventional semiconductor package
도 2는 본 발명의 반도체 패키지가 기판에 실장되는 상태를 나타낸 종단면도2 is a longitudinal sectional view showing a state in which a semiconductor package of the present invention is mounted on a substrate;
도 3 내지 및 도 4는 은 본 발명의 반도체 패키지의 패키징 과정을 설명하는 단면도로서,3 to 4 are cross-sectional views illustrating a packaging process of the semiconductor package of the present invention.
도 3은 칩을 리드프레임에 부착하는 공정이 완료된 후의 상태를 나타낸 종단면도Figure 3 is a longitudinal cross-sectional view showing a state after the process of attaching the chip to the lead frame is completed
도 4는 와이어 본딩 공정이 완료된 후의 상태를 나타낸 종단면도Figure 4 is a longitudinal cross-sectional view showing a state after the wire bonding process is completed.
도 5는 봉지공정이 완료된 후의 상태를 나타낸 종단면도Figure 5 is a longitudinal cross-sectional view showing a state after the sealing process is completed.
도 6은 도 4의 A방향에서 바라본 저면도6 is a bottom view as viewed from the direction A of FIG.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
1:반도체 칩 2:본딩패드1: Semiconductor chip 2: Bonding pad
3:리드프레임 4:바텀리드3: Lead frame 4: Bottom lead
5:와이어 6:몰드바디5: Wire 6: Molded body
7:통공7: through
상기한 목적을 달성하기 위해, 본 발명은 내부에 전기적 회로가 형성되며 일면에 전기적접속단자인 본딩패드가 형성되는 반도체 칩과, 상기 반도체 칩의 본딩패드가 형성된 면에 부착되며 상기 본딩패드를 제외한 영역에 부착되는 리드프레임과, 상기 리드프레임의 타측에 부착되는 외부접속단자인 바텀리드와, 상기 본딩패드와 리드프레임을 전기적으로 연결하는 와이어와, 상기 바텀리드의 선단부를 제외하고 반도체 칩과 리드 프레임 및 와이어를 봉지하는 몰드바디를 구비한 것을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the above object, the present invention is an electrical circuit is formed therein and the semiconductor chip is formed on the surface is a bonding pad, which is an electrical connection terminal, and is attached to the surface on which the bonding pad of the semiconductor chip is formed, except for the bonding pad A semiconductor chip and lead except for a lead frame attached to an area, a bottom lead which is an external connection terminal attached to the other side of the lead frame, a wire electrically connecting the bonding pad and the lead frame, and a tip of the bottom lead. There is provided a semiconductor package comprising a mold body for sealing a frame and a wire.
상기한 목적을 달성하기 위한 본 발명의 다른 형태에 따르면, 본 발명은 반도체 칩의 본딩패드가 노출되도록 상기 반도체 칩을 상기 반도체 칩의 본딩패드에 대응하는 영역이 뚫린 리드프레임에 부착하는 단계와, 상기 리드프레임 일측에 외부접속단자인 바텀리드를 부착하는 단계와, 상기 본딩패드와 리드프레임이 전기적으로 연결되도록 상기 본딩패드와 리드프레임을 와이어로 본딩하는 단계와, 상기 바텀리드의 선단부를 제외한 전부분이 봉지되도록 반도체 칩과 리드프레임 및 와이어를 에폭시 몰드 콤파운드로 감싸 봉지하는 단계를 순차적으로 수행하여서 됨을 특징으로 하는 반도체 패키지 제조방법이 제공된다.According to another aspect of the present invention for achieving the above object, the present invention comprises the steps of attaching the semiconductor chip to the lead frame perforated to the bonding pad of the semiconductor chip to expose the bonding pad of the semiconductor chip, Attaching a bottom lead, which is an external connection terminal to one side of the lead frame, bonding the bonding pad and the lead frame to a wire so that the bonding pad and the lead frame are electrically connected, and all but the front end of the bottom lead. A method of manufacturing a semiconductor package is provided by encapsulating a semiconductor chip, a lead frame, and a wire with an epoxy mold compound so as to encapsulate powder.
이하, 본 발명의 일실시예를 첨부도면 도 2 내지 도 6을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 6.
도 2는 본 발명의 반도체 패키지가 기판에 실장되는 상태를 나타낸 종단면도이고, 도 3 내지 및 도 4는 은 본 발명의 반도체 패키지의 패키징 과정을 설명하는 단면도이며, 도 5는 봉지공정이 완료된 후의 상태를 나타낸 종단면도이고, 도 6은 도 4의 A방향에서 바라본 저면도이다.Figure 2 is a longitudinal cross-sectional view showing a state in which the semiconductor package of the present invention is mounted on a substrate, Figures 3 to 4 are cross-sectional views illustrating a packaging process of the semiconductor package of the present invention, Figure 5 is after the sealing process is completed It is a longitudinal cross-sectional view which shows the state, and FIG. 6 is a bottom view seen from the A direction of FIG.
본 발명은 내부에 전기적 회로가 형성되며 일면에 전기적접속단자인 본딩패드(2)가 형성되는 반도체 칩(1)과, 상기 반도체 칩(1)의 본딩패드(2)가 형성된 면에 부착되며 상기 본딩패드(2)를 제외한 영역에 부착되는 리드프레임(3)과, 상기 리드프레임(3)의 타측에 부착되는 외부접속단자인 바텀리드(4)와, 상기 본딩패드(2)와 리드프레임(3)을 전기적으로 연결하는 와이어(5)와, 상기 바텀리드(4)의 선단부를 제외하고 반도체 칩(1)과 리드 프레임 및 와이어(5)를 봉지하는 몰드바디(6)가 구비되어 구성된다.According to the present invention, an electrical circuit is formed therein and a semiconductor chip 1 having a bonding pad 2, which is an electrical connection terminal, is attached to a surface on which a bonding pad 2 of the semiconductor chip 1 is formed. A lead frame 3 attached to an area excluding the bonding pad 2, a bottom lead 4 which is an external connection terminal attached to the other side of the lead frame 3, and the bonding pad 2 and a lead frame ( And a mold body 6 for encapsulating the semiconductor chip 1, the lead frame and the wire 5 except for the tip end of the bottom lid 4. .
한편, 본 발명의 반도체 패키지에 대한 패키징 과정을 설명하면 다음과 같다.Meanwhile, a packaging process for the semiconductor package of the present invention will be described below.
먼저, FAB공정을 마침에 따라 제조 완료된 반도체 칩(1)과, 상기 반도체 칩(1)의 본딩패드(2)와 대응하는 영역이 뚫린 리드프레임(3)을 각각 별도로 준비한 상태에서, 반도체 칩(1)의 본딩패드(2)가 형성된 면상에 리드프레임(3)을 상기 반도체 칩(1)의 전기적 접속단자인 본딩패드(2)가 노출되도록 부착시키게 된다.First, the semiconductor chip 1 manufactured by the completion of the FAB process and the lead frame 3 in which the regions corresponding to the bonding pads 2 of the semiconductor chip 1 are drilled are separately prepared. The lead frame 3 is attached on the surface on which the bonding pad 2 of 1) is formed such that the bonding pad 2, which is an electrical connection terminal of the semiconductor chip 1, is exposed.
이에 따라, 상기 반도체 칩(1)의 본딩패드(2)는 도 3 및 도 6에 각각 나타낸 바와 같이 리드프레임(3)의 통공(7)을 통해 노출된다.Accordingly, the bonding pads 2 of the semiconductor chip 1 are exposed through the through holes 7 of the lead frame 3 as shown in FIGS. 3 and 6, respectively.
한편, 반도체 칩(1)을 리드프레임(3)에 부착한 후에는 상기 리드프레임(3) 일측에 외부접속단자인 바텀리드(4)를 부착시키게 된다.Meanwhile, after the semiconductor chip 1 is attached to the lead frame 3, the bottom lead 4, which is an external connection terminal, is attached to one side of the lead frame 3.
또한, 그 후에는 도 4에 나타낸 바와 같이 상기 본딩패드(2)와 리드프레임(3)이 전기적으로 연결되도록 상기 본딩패드(2)와 리드프레임(3)을 골드 와이어(5)(gold wire)로 연결하는 와이어 본딩을 실시하게 된다.After that, as shown in FIG. 4, the bonding pad 2 and the lead frame 3 are connected to the gold wire 5 so that the bonding pad 2 and the lead frame 3 are electrically connected to each other. Wire bonding is performed.
그리고, 와이어 본딩이 완료된 후에는, 도 5에 나타낸 바와 같이, 상기 바텀리드(4)의 선단부를 제외한 전부분이 봉지되도록 반도체 칩(1)과 리드프레임(3) 및 와이어(5)를 에폭시 몰드 콤파운드(EMC)로 감싸는 봉지 공정을 수행하게 되며, 이로써 반도체 소자의 패키징 과정이 완료된다.After the wire bonding is completed, as shown in FIG. 5, the semiconductor chip 1, the lead frame 3, and the wire 5 are epoxy-molded so that the entire portion of the bottom lead 4 except for the tip portion is sealed. An encapsulation process is performed by wrapping the semiconductor device (EMC), thereby completing the packaging process of the semiconductor device.
이 때, 상기 몰드바디(6)는 반도체 칩(1)의 면적 크기를 벗어나지 않는 크기를 갖게 된다.At this time, the mold body 6 has a size that does not deviate from the area size of the semiconductor chip (1).
또한, 상기한 패키징 공정의 원할한 진행을 위해서는 도 3 내지 도 6에 나타낸 바와 같이 반도체 칩(1)이 가장 하부에 위치한 상태에서 칩 본딩과 와이어 본딩 및 봉지공정이 이루어지는 것이 가장 바람직하다.In addition, it is most preferable that the chip bonding, the wire bonding, and the encapsulation process are performed in the state where the semiconductor chip 1 is located at the bottom as shown in FIGS.
한편, 상기에서 바텀리드(4)는 리드프레임(3) 제작시 리드프레임과 일체로 형성되어도 무방하다.On the other hand, the bottom lead 4 may be formed integrally with the lead frame when manufacturing the lead frame (3).
이와 같이 제조된 반도체 패키지는 도 2에 나타낸 바와 같이 바텀리드(4)가 실장용 기판(8) 상면에 접속되도록 실장하게 된다.The semiconductor package manufactured as described above is mounted such that the bottom lead 4 is connected to the upper surface of the mounting substrate 8 as shown in FIG.
이상에서와 같이, 본 발명의 반도체 패키지는 반도체 칩(1)의 면적을 벗어나지 않는 크기로 와이어 본딩 및 봉지공정이 이루어짐에 따라 반도체 패키지를 경박단소화하여 실장밀도를 향상시킬 수 있게 된다.As described above, the semiconductor package of the present invention can improve the mounting density by making the semiconductor package thin and short as the wire bonding and encapsulation process is performed in a size that does not deviate from the area of the semiconductor chip 1.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980000451A KR100259079B1 (en) | 1998-01-10 | 1998-01-10 | Semiconductor package and method for fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980000451A KR100259079B1 (en) | 1998-01-10 | 1998-01-10 | Semiconductor package and method for fabricating the same |
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| Publication Number | Publication Date |
|---|---|
| KR19990065237A KR19990065237A (en) | 1999-08-05 |
| KR100259079B1 true KR100259079B1 (en) | 2000-06-15 |
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|---|---|---|---|
| KR1019980000451A KR100259079B1 (en) | 1998-01-10 | 1998-01-10 | Semiconductor package and method for fabricating the same |
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| Country | Link |
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| KR (1) | KR100259079B1 (en) |
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| KR19990065237A (en) | 1999-08-05 |
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