JPH04192421A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04192421A
JPH04192421A JP32422090A JP32422090A JPH04192421A JP H04192421 A JPH04192421 A JP H04192421A JP 32422090 A JP32422090 A JP 32422090A JP 32422090 A JP32422090 A JP 32422090A JP H04192421 A JPH04192421 A JP H04192421A
Authority
JP
Japan
Prior art keywords
pattern
face
semiconductor element
semiconductor device
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32422090A
Other languages
Japanese (ja)
Inventor
Yoshihiro Tomita
至洋 冨田
Naohisa Ueda
上田 直久
Hitoshi Fujimoto
藤本 仁士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP32422090A priority Critical patent/JPH04192421A/en
Publication of JPH04192421A publication Critical patent/JPH04192421A/en
Pending legal-status Critical Current

Links

Landscapes

  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To protect the end face of a semiconductor element and to improve reliability by covering the element with resin for protecting a pattern of the element to the end face of the element. CONSTITUTION:A pattern 2 is formed on the main surface of a wafer 1 by extending at an interval corresponding to a groove 5. Then, the groove 5 is formed by etching or cutting, and covered with protective resin covering the pattern 2 and also filling the groove 5. Thereafter, the wafer 1 is cut in a dicing step at a broken part, and separated into individual semiconductor elements 4. Thus, the end face of the element can be protected to improve reliability.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

〔従来の技術〕[Conventional technology]

第2図は、従来の半導体装置の断面図を示すものであり
、(al〜(d)はその製造の課程を示すものである。
FIG. 2 shows a cross-sectional view of a conventional semiconductor device, and (al to (d)) show the manufacturing process thereof.

図において、(1)はウェハ、(2)はウェハ主面上に
形成されたパターン、(3)は前記パターン(2)の中
央部に被覆された保護樹脂、(4)は個々に分離され、
次工程に送られ、封止されて半導体装置に組立てられる
へき半導体素子(4)である。
In the figure, (1) is the wafer, (2) is the pattern formed on the main surface of the wafer, (3) is the protective resin coated on the center of the pattern (2), and (4) is the individual separated pattern. ,
The semiconductor element (4) is sent to the next process, sealed, and assembled into a semiconductor device.

次に製造の課程について説明する。Next, the manufacturing process will be explained.

第2図(a)に示すウェハ(1)の主面上に、第2図(
blに示すようにパターン(2)を形成する。次いて第
2図(C)においてパターン(2)の中央部に保護樹脂
(3)を被覆する。この後ウェハ(1)は、ダイシング
工程において第2図FC+に示す破線部を切断され、第
2図(d)に示すように個々の半導体素子(4)に分離
される。
On the main surface of the wafer (1) shown in FIG. 2(a),
A pattern (2) is formed as shown in bl. Next, in FIG. 2(C), the central part of the pattern (2) is coated with a protective resin (3). Thereafter, the wafer (1) is cut along the broken line shown in FIG. 2(d) in a dicing step, and separated into individual semiconductor elements (4) as shown in FIG. 2(d).

半導体素子(4)は、例えば、半導体素子(4)を基板
上に固着するダイホント、半導体素子(4)と外部端子
を電気的に結線するワイヤポンド等を経て、封止され半
導体装置として組立てられる。
The semiconductor element (4) is sealed and assembled as a semiconductor device through, for example, a die bonnet for fixing the semiconductor element (4) on a substrate, a wire bond for electrically connecting the semiconductor element (4) and external terminals, etc. .

〔発明か解決しようとする課題〕[Invention or problem to be solved]

従来の半導体装置は以上のように構成されているので、
半導体素子の端面か保護されておらず、従って例えば、
ダイシングてはパターンを形成している材料(例えばA
7)のはく離、ダイホントては、半導体素子の端面への
ダメージによる、チッピングやクラック、ワイヤホント
ては電極と外部端子を結線する材料(例えばAu線)か
半導体素子の端面に接触することによって起こるノヨー
ト等の問題点かあった。
Conventional semiconductor devices are configured as described above, so
The edges of the semiconductor device are unprotected and therefore e.g.
In dicing, the material forming the pattern (for example, A
7) Peeling and die-cutting are caused by chipping and cracking due to damage to the end face of the semiconductor element, and wires are caused by the material (such as Au wire) connecting the electrode and external terminal coming into contact with the end face of the semiconductor element. There was a problem with Noyoto etc.

この発明は上記のような問題点を解消するためになされ
たもので、半導体素子の端面を保護できるとともに、信
頼性の高い半導体装置を得ることを目的とする。
This invention was made to solve the above-mentioned problems, and aims to provide a highly reliable semiconductor device that can protect the end face of a semiconductor element.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置は、半導体素子のパターンを
保護する樹脂を、半導体素子の端面まて被覆するように
したものである。
In the semiconductor device according to the present invention, the end face of the semiconductor element is coated with a resin that protects the pattern of the semiconductor element.

〔作用〕[Effect]

この発明における半導体装置は、樹脂により半導体素子
の端面か保護されるので、半導体装置の信頼性か向上す
る。
In the semiconductor device according to the present invention, the end face of the semiconductor element is protected by the resin, so the reliability of the semiconductor device is improved.

〔実施例〕〔Example〕

以下、この発明の一実施例と図について説明する。 Hereinafter, one embodiment of the present invention and the drawings will be described.

第1図において、(al〜(d)はその製造の課程を示
すものであり、(1)〜(4)は従来技術て説明したも
のと同等であるので、詳細な説明は省略する。(5)は
、ウェハ(1)の主面上に形成された溝である。
In FIG. 1, (al to (d) indicate the manufacturing process, and since (1) to (4) are the same as those described in the prior art, detailed explanations will be omitted. ( 5) is a groove formed on the main surface of the wafer (1).

次に製造の課程について説明する。Next, the manufacturing process will be explained.

第1図(alに示す前記ウェハ(1)の主面上に、あら
かしめ前記溝(5)の分たけ間隔を拡げて、第1図(b
lに示すようにパターン(2)を形成する。次いて第1
図(C1に示すように、エツチングあるいは切削により
溝(5)を形成し、第1図(d)に示すようにパターン
(2゛・上を被覆するたけてなく、溝(5)まで充てん
するように保護樹脂(3)を塗布する。この後ウェハ(
1)は、ダイシング工程において第1図(d)に示す破
線部と切断され、第1図(e)に示すように個々の半導
体素子(4)に分離される。半導体素子(4)は、従来
技術で説明したように、ダイポンド、ワイヤポンド等を
経て封止され、半導体装置として組立てられる。
On the main surface of the wafer (1) shown in FIG. 1(al), the intervals of the grooves (5) are widened, as shown in FIG. 1(b).
A pattern (2) is formed as shown in FIG. Then the first
As shown in Figure (C1), a groove (5) is formed by etching or cutting, and as shown in Figure 1 (d), the pattern (2゛) is filled up to the groove (5) without covering the top. Apply the protective resin (3) as shown below.After this, apply the protective resin (3) to the wafer (
1) is cut along the broken line shown in FIG. 1(d) in the dicing process, and separated into individual semiconductor elements (4) as shown in FIG. 1(e). The semiconductor element (4) is sealed via a die bond, a wire bond, etc., as described in the prior art section, and assembled as a semiconductor device.

なお、本実施例においては、溝(5)をU字型として図
示したか、溝(5)の形状はこれによらない。
In this embodiment, although the groove (5) is shown as U-shaped, the shape of the groove (5) is not limited to this.

また、上記実施例においては、保護樹脂の材料について
は特に言及していないか、絶縁性の樹脂を使用すれば、
ワイヤポンドにおいて結線材と半導体素子端面との接触
によるショートか防止できる。
In addition, in the above examples, there is no particular mention of the material of the protective resin, or if an insulating resin is used,
It is possible to prevent short circuits caused by contact between the wiring material and the end face of the semiconductor element in the wire pond.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、半導体素子の表面を
保護する樹脂を、半導体素子の端面をも保護するように
したので、組立て工程における種々の問題、例えばダイ
シングにおけるパターン材料のはく離、ダイホントにお
ける半導体素子端面へのダメージ軽減、ワイヤポンドに
おける結線材と半導体素子端面とのショート等か解消で
き、信頼性の高い半導体装置か得られる効果力\ある。
As described above, according to the present invention, the resin that protects the surface of the semiconductor element also protects the end face of the semiconductor element, which can solve various problems in the assembly process, such as peeling of pattern material during dicing, die bonding, etc. It has the effect of reducing damage to the semiconductor element end face in the process, eliminating short-circuits between the connecting material and the semiconductor element end face in the wire pond, and producing a highly reliable semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体装置を示す断
面図、第2図は従来の半導体装置を示す断面図である。 図において、(11はウェハ、(2)はパターン、(3
)は保護樹脂、(4)は半導体素子、(5)は溝である
。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, (11 is the wafer, (2) is the pattern, and (3) is the wafer.
) is a protective resin, (4) is a semiconductor element, and (5) is a groove. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims]  半導体素子表面を保護する樹脂を備えた半導体装置に
おいて、前記半導体素子の端面を前記樹脂により保護す
ることを特徴とした半導体装置。
1. A semiconductor device comprising a resin for protecting a surface of a semiconductor element, wherein an end face of the semiconductor element is protected by the resin.
JP32422090A 1990-11-26 1990-11-26 Semiconductor device Pending JPH04192421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32422090A JPH04192421A (en) 1990-11-26 1990-11-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32422090A JPH04192421A (en) 1990-11-26 1990-11-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04192421A true JPH04192421A (en) 1992-07-10

Family

ID=18163384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32422090A Pending JPH04192421A (en) 1990-11-26 1990-11-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04192421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216215A (en) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 Semiconductor devices and manufacturing method
US11201097B2 (en) 2017-06-30 2021-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216215A (en) * 2017-06-30 2019-01-15 台湾积体电路制造股份有限公司 Semiconductor devices and manufacturing method
US11121050B2 (en) 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device
US11201097B2 (en) 2017-06-30 2021-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device

Similar Documents

Publication Publication Date Title
US6841414B1 (en) Saw and etch singulation method for a chip package
WO2007106487A2 (en) Methods of making qfn package with power and ground rings
JPH06338583A (en) Resin-sealed semiconductor device and manufacture thereof
JPH04192421A (en) Semiconductor device
US3395447A (en) Method for mass producing semiconductor devices
JPS63232342A (en) Semiconductor device
JPS61147555A (en) Semiconductor device
JPS62154769A (en) Semiconductor device
JPH01257361A (en) Resin-sealed semiconductor device
JPS5930538Y2 (en) semiconductor equipment
JPH0621305A (en) Semiconductor device
JPH01135052A (en) Semiconductor device and manufacture thereof
JPH10214933A (en) Semiconductor device and its manufacturing
JPS62296541A (en) Plastic molded semiconductor device
JPH04277637A (en) Semiconductor chip and manufacture thereof
KR100214532B1 (en) Making method of column lead package
KR0184061B1 (en) Semiconductor package
KR100201389B1 (en) Semiconductor package
JPS6236299Y2 (en)
JP2533751B2 (en) Resin-sealed semiconductor device
JPS617638A (en) Semiconductor device
KR200331874Y1 (en) Multi-pin Package of Semiconductor
JPH11150144A (en) Semiconductor device and its manufacture
JP2533750B2 (en) Resin-sealed semiconductor device
JPH0724275B2 (en) Semiconductor device