JPS63232342A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63232342A JPS63232342A JP62063926A JP6392687A JPS63232342A JP S63232342 A JPS63232342 A JP S63232342A JP 62063926 A JP62063926 A JP 62063926A JP 6392687 A JP6392687 A JP 6392687A JP S63232342 A JPS63232342 A JP S63232342A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- package
- recess
- side surfaces
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 8
- 229920005989 resin Polymers 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- 239000000919 ceramic Substances 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 241000283070 Equus zebra Species 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10157—Shape being other than a cuboid at the active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置におけるパッケージと電極接続技術
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package and electrode connection technology in a semiconductor device.
ＩＣ等の半導体装置における基本パッケージング技術と
しては、例えば丸善株式会社１９６８年１１月発行「集
積回路ハンドブックＪｐ８１０に記載されているように
、（１）金属を用いたＴＯ−５形、（２）樹脂封止によ
るフラットパッケージ形、＋３１セラミツク容器を用い
るデエアｙインライン形等がある。いずれの場合におい
ても、パッケージ基体にＩＣ本体である半導体チップを
取付けた後、チップの各電極とパッケージ側の内端子〔
樹脂封止の場合はリード）との閣をワイヤボンディング
手段により接続することが必須要件となっている。Basic packaging technologies for semiconductor devices such as ICs include (1) TO-5 type using metal, (2) There is a flat package type using resin sealing, and a de-air inline type using a +31 ceramic container.In either case, after attaching the semiconductor chip, which is the IC body, to the package base, each electrode of the chip and the inside of the package are connected. Terminal [
In the case of resin sealing, it is essential to connect the cap to the lead (lead) by wire bonding.
〔発明が解決しよ５とする問題点〕
上述したパッケージング技術では、ワイヤボンディング
のために半導体チップの周辺にそってボンディングバッ
ドと称する端子電極を配置しなければならない。このパ
ッドの寸法及び間隔はポンディング位置誤差な一考慮し
て充分に広くとる必要があり、このためにチップ周辺部
は少なからぬ面積がパッドに占められることになる。又
、電極の数に対応する数のワイヤを使うことでボンディ
ングに時間がかかり、ワイヤが長いときにワイヤとチッ
プ角部が接触する「ワイヤ流れ」による短絡事故を生ず
る等の問題があった。[Problems to be Solved by the Invention] In the above-mentioned packaging technology, terminal electrodes called bonding pads must be arranged along the periphery of the semiconductor chip for wire bonding. The size and spacing of these pads must be sufficiently wide to take into account the bonding position error, and for this reason, a considerable area of the chip periphery is occupied by the pads. Furthermore, since the number of wires corresponding to the number of electrodes is used, bonding takes time, and when the wires are long, there are problems such as short circuit accidents due to "wire flow" where the wires come into contact with the corners of the chip.
本発明は上記した問題を克服するためになされたもので
あり、その目的とするところは、半導体チップ側の電極
とパッケージ側の端子とがワイヤを介することなく接続
を保つことができ、組立も簡単にできる新規なパッケー
ジング技術を提供することにある。The present invention has been made to overcome the above-mentioned problems, and its purpose is to maintain a connection between the electrodes on the semiconductor chip and the terminals on the package without using wires, and to make assembly easier. Our goal is to provide a new packaging technology that is easy to implement.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、半導体内部に回路素子が形成され、一主面上
に配線が形成されるとともに側面には上記配線の端子が
設けられた半導体チップと、このチップを収納すること
のできる凹部を有し、周辺に外部リードが設けられると
ともに上記凹部側面に上記リードの内端子が設けられた
パッケージとを具備し、上記半導体チップの側面とパッ
ケージ凹部側面とを突合せることにより上記チップの電
極と外部リードとを接続するようにしたものである。That is, it has a semiconductor chip in which a circuit element is formed inside the semiconductor, wiring is formed on one main surface, and terminals for the wiring are provided on the side surface, and a recess in which this chip can be housed; A package is provided with external leads on the periphery and inner terminals of the leads are provided on the side surfaces of the recess, and by abutting the side surfaces of the semiconductor chip and the side surfaces of the package recess, the electrodes of the chip and the external leads are connected. It is designed to connect.
上記した手段によれば半導体チップ側面の電極とパッケ
ージの凹部側面の内端子とが直接に接触することでワイ
ヤ乃至ワイヤボンディング工程が不要であり、チップに
おいてはボンディングのためのパッドが不要であるため
にチップの面積を縮小できる等の効果がある。According to the above-mentioned means, the electrodes on the side surface of the semiconductor chip and the inner terminals on the side surface of the recessed part of the package come into direct contact, so there is no need for a wire or wire bonding process, and no pads for bonding are required on the chip. This has the advantage of reducing the chip area.
〔実施例１〕
第１図乃至第１図は本発明の一実施例を示すものである
。[Embodiment 1] FIGS. 1 and 1 show an embodiment of the present invention.
第１図はＩＣチップの斜面図であって、１はＳｉ基板で
あり、その−主表面よりの不純物拡散によって基板内部
にトランジスタ等の回路素子が形成される。FIG. 1 is a perspective view of an IC chip. Reference numeral 1 denotes a Si substrate, and circuit elements such as transistors are formed inside the substrate by diffusion of impurities from its main surface.
２はＡ１配線であって、回路素子の各拡散領域に接続さ
れ、そのチップ周辺から側面に延在し側面導電層３がそ
れぞれ外端子となっている。A1 wiring 2 is connected to each diffusion region of the circuit element, extends from the periphery of the chip to the side surface, and the side surface conductive layer 3 serves as an external terminal.
上記のような側面導電層３を形成するにあたっては、た
とえば第２図に示すような側面に窓孔５を有する箱状の
マスク４を使用し、ウェハ状態でＡ！配線２を形成し、
ダイシングによって個々のチップ１に分割した後、上記
マスク４でテップ１を覆った状態でＡＡ等の金属を蒸着
することにより窓孔５を通してチップ側面に導電層（３
１を形成することができる。In forming the side conductive layer 3 as described above, for example, a box-shaped mask 4 having a window hole 5 on the side surface as shown in FIG. 2 is used, and A! Form wiring 2,
After dividing into individual chips 1 by dicing, a conductive layer (3
1 can be formed.
第３図は上記チップを接続するためのパッケージの斜面
図であって、本体６はセラミック又は樹脂等の絶縁物か
らなり、上部に凹部７があけである。この凹部７は前記
ＩＣチップ１を挿入してその側面との間に隙間が生じな
いようにチップに合わせて寸法が規定される。FIG. 3 is a perspective view of the package for connecting the above-mentioned chips, and the main body 6 is made of an insulating material such as ceramic or resin, and has a recess 7 in the upper part. The dimensions of this recess 7 are determined according to the IC chip 1 so that there is no gap between the IC chip 1 and its side surface.
凹部７の上面及び側面には導電層８，９が前記チップの
各導電層に対応する位置に形成しである。Conductive layers 8 and 9 are formed on the top and side surfaces of the recess 7 at positions corresponding to the respective conductive layers of the chip.
側面の導電層９は、チップの場合と同様に特定のマスク
を使用することにより形成することができる。上面の各
導電層８の上にはリード１０を接続しである。The conductive layer 9 on the side surface can be formed by using a specific mask as in the case of the chip. Leads 10 are connected to each conductive layer 8 on the upper surface.
これらリード１０は予めリードフレーム（点線で示す）
の状態でパッケージ上面に半田等で固着した後、周辺の
フレーム１１を切り離すことにより個々に分離したり−
ド１０として形成することができる。These leads 10 are attached to a lead frame (indicated by dotted lines) in advance.
After fixing it to the top surface of the package with solder etc. in this state, it can be separated individually by cutting off the surrounding frame 11.
It can be formed as a board 10.
第１図は前記したＩＣテップ１をノくツケージ６の凹部
７内に挿入することにより、テップの各配線端子とパッ
ケージのリードとをチップ側面で接続させた状態を示す
断面図である。チップ１とノくッケージ６の間には隙間
を存在させないようにすれば、チップ側面の導電層３と
凹部側面の導電層９とが互いに密着し、電気的な接続を
得ることができる。FIG. 1 is a cross-sectional view showing a state in which the IC chip 1 described above is inserted into the recess 7 of the socket cage 6, and each wiring terminal of the chip and the lead of the package are connected at the side surface of the chip. If there is no gap between the chip 1 and the socket 6, the conductive layer 3 on the side surface of the chip and the conductive layer 9 on the side surface of the recess will come into close contact with each other, and electrical connection can be achieved.
１２はチップを覆うように設けた樹脂等の絶縁物よりな
る蓋部である。この蓋部１２は樹脂モールド又は樹脂ボ
ンディングによって形成することができる。Reference numeral 12 denotes a lid portion made of an insulating material such as resin and provided to cover the chip. This lid portion 12 can be formed by resin molding or resin bonding.
パッケージ６がセラミック材の場合は、蓋部に金属又は
セラミックの板を用いガラス材等を介して封止する。When the package 6 is made of a ceramic material, a metal or ceramic plate is used as the lid and sealed with a glass material or the like interposed therebetween.
上記した実施例から得られる作用効果は下記のとおりで
ある。The effects obtained from the above embodiments are as follows.
（１）ワイヤボンディング工程がいらないから、ＳＴが
低減でき、ワイヤが不要でＶＡ効効果ある。又、ワイヤ
流れのおそれもない。(1) Since no wire bonding process is required, ST can be reduced, and no wires are required, resulting in VA effect. Also, there is no risk of wire drifting.
（２１チップ上面において、ポンディングパッドがな（
なることにより、チップ面積を有効に使用できる。(There are no bonding pads on the top surface of the 21 chip.
By doing so, the chip area can be used effectively.
（３＋ＩＣ上面を伏せて置いて封止するパッシベーショ
ン効果が太きい。(3+The passivation effect of sealing by placing the IC top face down is strong.
〔実施例２〕
第５図乃至第７図は本発明の他の一実施例を示すもので
ある。[Embodiment 2] FIGS. 5 to 7 show another embodiment of the present invention.
第５図はＩＣチップの断面図であって、チップ１の側面
は一部にテーパー１３を設けである。このようなテーパ
ー１３はフェノ・−の状態でアルカリエッチなどの特種
のエツチングにより斜面の溝の一部として形成し、その
後チップに分割することにより得られる。このようなテ
ーパーの溝な形成してｉ６（ことにより、ウェハの状態
で人！配線蒸着と同時に側面導電層１４を設けることが
容易となる。FIG. 5 is a cross-sectional view of the IC chip, and the side surface of the chip 1 is partially tapered 13. Such a taper 13 can be obtained by forming a part of a groove on an inclined surface by special etching such as alkali etching in a phenol state, and then dividing it into chips. By forming such a tapered groove, it becomes easy to provide the side conductive layer 14 simultaneously with the wiring vapor deposition in the wafer state.
第６図は上記ＩＣチップをパッケージに接続する場合の
態様を示す断面図である。FIG. 6 is a cross-sectional view showing the manner in which the above-mentioned IC chip is connected to a package.
この場合に使用されパッケージ６の凹部７はチップの場
合と同様にテーパー１５を設けである。The recess 7 of the package 6 used in this case is provided with a taper 15 as in the case of the chip.
テーパー上にはチップの導体層１６と対応して上面から
連続する導体層１６を設けである。On the taper, a conductor layer 16 is provided that corresponds to the conductor layer 16 of the chip and continues from the top surface.
１７は弾性棒状コネクタ（商品名ゼブラ・コネクタ）で
あって、第７図に示すようにゴム状の絶縁棒体の側面を
取囲む縞状電極１８を有する。この棒体の断面は同図１
１１ 、 （ｂｌに示すよ５に四角形であってもよく、
円形であってもよい。Reference numeral 17 denotes an elastic rod-like connector (trade name: Zebra Connector), which has a striped electrode 18 surrounding the side surface of a rubber-like insulating rod, as shown in FIG. The cross section of this rod is shown in Figure 1.
11, (as shown in bl, 5 may be rectangular,
It may be circular.
これら縞状電極１８と前記チップ１及′びパッケージ６
斜面の導電層１４．１６と同じ間隔で電極が設けてあり
、この縞状電極コネクタをチップとパッケージの間にで
きるＶ状溝に挿入されることでゴム状のコネクタが両方
の導電層間に密着して両者の間が電気的に導通される。These striped electrodes 18, the chip 1' and the package 6
Electrodes are provided at the same intervals as the conductive layers 14 and 16 on the slope, and by inserting this striped electrode connector into the V-shaped groove formed between the chip and the package, the rubber-like connector is tightly attached between both conductive layers. Thus, electrical continuity is established between the two.
゛
なお、コネクタ挿入後は、第１図を参照し上側を絶縁性
板または樹脂等を被覆して固定する。After inserting the connector, refer to FIG. 1 and cover the upper side with an insulating plate or resin to fix it.
このような縞状電極を有するコネクタを使用する場合は
、チップ及びパッケージにおいて斜面に導電層を設けれ
ばよく、側面に設ける場合に比して作業工程が短縮でき
る。又、チップとパッケージ凹部の法によって多少の隙
間を許容することができ、工作上も有利である。When using a connector having such striped electrodes, it is sufficient to provide the conductive layer on the slope of the chip and package, and the work process can be shortened compared to the case where the conductive layer is provided on the side surface. Further, it is possible to allow a certain amount of gap depending on the method between the chip and the package recess, which is advantageous in terms of manufacturing.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能である。Although the invention made by the present inventor has been specifically described above based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof.
たとえばパッケージの凹部を入口は広く底部は狭いテー
パーとすればチップを挿入しやすく、挿入後に側面での
密着性が良（なる。For example, if the concave part of the package is tapered with a wide entrance and a narrow bottom, it will be easier to insert the chip, and it will have good adhesion on the sides after insertion.
本発明は半導体製品全般に応用することができる。The present invention can be applied to semiconductor products in general.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば下記のとおりである
。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、チップとパッケージの間でのワイヤボ／ディ
／グが不要となり、パッケージングの簡略化、自動化を
実現できる。In other words, there is no need for wire bonding/digging between the chip and the package, making it possible to simplify and automate packaging.
第１図は本発明の一実施例を示すチップの斜面図である
。
第２図はｇ１図のチップの側面に導電層を設ける形態を
示す斜面図である。
第３図は本発明の一実施例を示すパッケージの斜面図で
ある。
第１図は本発明の一実施例を示す半導体装置の組立断面
図である。
第５図は本発明の他の一実施例を示すチップの断面図で
ある。
第６図は本発明の他の一実施例を示す半導体装置の組立
断面図である。
第７図１ａｌ 、 （ｂｌは弾性棒状コネクタの斜面図
である。
１・・・Ｓｉ基板、２・・・Ａ２配線、３・・・側面導
電層。
４・・・マスク、５・・・窓孔、６・・・パッケージ本
体、７・・・凹部、８，９・・・導電層、１０・・・リ
ード、１１・・・フレーム、１２・・・蓋部（樹脂）、
１３・・・テーパー、１４・・・導電層、１５・・・テ
ーパー、１６・・・導電層、１７・・・コネクタ、１８
・・・縞状電極。
代理人 弁理士 小 川 勝 男
第 １ 図
第 ２ 図
第 ３ 図
第 ４ 図
第 ６ 図
第 ７ 図FIG. 1 is a perspective view of a chip showing an embodiment of the present invention. FIG. 2 is a perspective view showing a configuration in which a conductive layer is provided on the side surface of the chip in FIG. g1. FIG. 3 is a perspective view of a package showing an embodiment of the present invention. FIG. 1 is an assembled sectional view of a semiconductor device showing an embodiment of the present invention. FIG. 5 is a sectional view of a chip showing another embodiment of the present invention. FIG. 6 is an assembled sectional view of a semiconductor device showing another embodiment of the present invention. FIG. 7 1al, (bl is an oblique view of the elastic rod-shaped connector. 1...Si substrate, 2...A2 wiring, 3...side conductive layer. 4...mask, 5...window Hole, 6... Package body, 7... Recess, 8, 9... Conductive layer, 10... Lead, 11... Frame, 12... Lid (resin),
13... Taper, 14... Conductive layer, 15... Taper, 16... Conductive layer, 17... Connector, 18
...Striped electrode. Agent Patent Attorney Katsoo Ogawa Figure 1 Figure 2 Figure 3 Figure 4 Figure 6 Figure 7
Claims (1)
が設けられるとともに側面に上記配線の外端子が設けら
れた半導体チップと、上記チップが収納できる凹部を有
し、周辺に外部リードが設けられるとともに上記凹部側
面に上記リードの内端子が設けられたパッケージとを具
備し、上記半導体チップの側面でその外端子と上記パッ
ケージの凹部側面のリードの内端子とが突合せ接続され
ていることを特徴とする半導体装置。 ２、上記半導体チップの側面の外端子とパッケージ凹部
側面のリード内端子とは縞状の電極を有する弾性棒状コ
ネクタを介して接続されている特許請求の範囲第１項に
記載の半導体装置。[Scope of Claims] 1. A semiconductor chip having a circuit element formed inside the semiconductor, wiring provided on one principal surface, and external terminals for the wiring provided on a side surface, and a recessed portion in which the chip can be accommodated. and a package in which an external lead is provided on the periphery and an inner terminal of the lead is provided on the side surface of the recess, and the outer terminal and the inner terminal of the lead on the side surface of the recess of the package are connected to each other on the side surface of the semiconductor chip. A semiconductor device characterized in that these are butt-connected. 2. The semiconductor device according to claim 1, wherein the outer terminal on the side surface of the semiconductor chip and the inner lead terminal on the side surface of the package recess are connected via an elastic rod-shaped connector having a striped electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62063926A JPS63232342A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62063926A JPS63232342A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63232342A true JPS63232342A (en) | 1988-09-28 |
Family
ID=13243434
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62063926A Pending JPS63232342A (en) | 1987-03-20 | 1987-03-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63232342A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606198A (en) * | 1993-10-13 | 1997-02-25 | Yamaha Corporation | Semiconductor chip with electrodes on side surface |
| US5825084A (en) * | 1996-08-22 | 1998-10-20 | Express Packaging Systems, Inc. | Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices |
| US7115984B2 (en) * | 2002-06-18 | 2006-10-03 | Micron Technology, Inc. | Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices |
| JP2006319002A (en) * | 2005-05-10 | 2006-11-24 | Nippon Steel Corp | Semiconductor mounted body, semiconductor mounted body semi-finished product and their manufacturing method |
| US7208335B2 (en) | 2003-09-30 | 2007-04-24 | Micron Technology, Inc. | Castellated chip-scale packages and methods for fabricating the same |
| US7226809B2 (en) | 2002-06-18 | 2007-06-05 | Micron Technology, Inc. | Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated methods |
| SG157221A1 (en) * | 2002-06-18 | 2009-12-29 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices |
| JP2011254110A (en) * | 2011-09-15 | 2011-12-15 | Aoi Electronics Co Ltd | Semiconductor device and manufacturing method therefor |
-
1987
- 1987-03-20 JP JP62063926A patent/JPS63232342A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5606198A (en) * | 1993-10-13 | 1997-02-25 | Yamaha Corporation | Semiconductor chip with electrodes on side surface |
| US5825084A (en) * | 1996-08-22 | 1998-10-20 | Express Packaging Systems, Inc. | Single-core two-side substrate with u-strip and co-planar signal traces, and power and ground planes through split-wrap-around (SWA) or split-via-connections (SVC) for packaging IC devices |
| US7115984B2 (en) * | 2002-06-18 | 2006-10-03 | Micron Technology, Inc. | Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices |
| US7226809B2 (en) | 2002-06-18 | 2007-06-05 | Micron Technology, Inc. | Semiconductor devices and semiconductor device components with peripherally located, castellated contacts, assemblies and packages including such semiconductor devices or packages and associated methods |
| US7285850B2 (en) | 2002-06-18 | 2007-10-23 | Micron Technology, Inc. | Support elements for semiconductor devices with peripherally located bond pads |
| SG157221A1 (en) * | 2002-06-18 | 2009-12-29 | Micron Technology Inc | Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices |
| US7208335B2 (en) | 2003-09-30 | 2007-04-24 | Micron Technology, Inc. | Castellated chip-scale packages and methods for fabricating the same |
| US7633159B2 (en) | 2003-09-30 | 2009-12-15 | Micron Technology, Inc. | Semiconductor device assemblies and packages with edge contacts and sacrificial substrates and other intermediate structures used or formed in fabricating the assemblies or packages |
| JP2006319002A (en) * | 2005-05-10 | 2006-11-24 | Nippon Steel Corp | Semiconductor mounted body, semiconductor mounted body semi-finished product and their manufacturing method |
| JP2011254110A (en) * | 2011-09-15 | 2011-12-15 | Aoi Electronics Co Ltd | Semiconductor device and manufacturing method therefor |
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