JPH0547988A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0547988A JPH0547988A JP3233845A JP23384591A JPH0547988A JP H0547988 A JPH0547988 A JP H0547988A JP 3233845 A JP3233845 A JP 3233845A JP 23384591 A JP23384591 A JP 23384591A JP H0547988 A JPH0547988 A JP H0547988A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- die pad
- semiconductor device
- resin
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ダイパッド上に搭載し
たチップを樹脂にて一体封止する半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a chip mounted on a die pad is integrally sealed with resin.
【０００２】[0002]
【従来の技術】従来、製造工程が簡易で低コストなパッ
ケージとして、例えばトランスファーモールド法による
樹脂封止型の半導体装置がある。これは、図５に示すよ
うに、リードフレーム１のダイパッド２上に搭載したチ
ップ３と、このチップ３とリードフレーム１とを接続し
たワイヤー４と、これら全体を一体封止した樹脂５とか
ら成る半導体装置である。このチップ３の下面全体とダ
イパッド２の上面は吸水性の高い銀ペースト７により接
着されている。2. Description of the Related Art Conventionally, as a package which has a simple manufacturing process and a low cost, there is, for example, a resin-sealed semiconductor device by a transfer molding method. As shown in FIG. 5, this is composed of a chip 3 mounted on the die pad 2 of the lead frame 1, a wire 4 connecting the chip 3 and the lead frame 1, and a resin 5 integrally encapsulating them. It is a semiconductor device. The entire lower surface of the chip 3 and the upper surface of the die pad 2 are adhered by a silver paste 7 having high water absorption.
【０００３】[0003]
【発明が解決しようとする課題】このように前記説明し
た半導体装置では、以下に示す問題がある。すなわち、
樹脂による一体封止が完了した半導体装置において、チ
ップとダイパッドとを接着している銀ペースト内は水分
を含んだままの状態である。この半導体装置を基板に実
装し、ハンダ付けを行うため２４０℃前後に加熱する
と、前述の銀ペースト内に含まれていた水分が気化して
膨張する。このとき発生する応力により、チップとダイ
パッドが剥離する。さらにこの剥離が進むと、図６に示
すようにパッケージにクラック（亀裂）が発生する。こ
のチップとダイパッドとが剥離することでチップが破損
したり、クラックによりワイヤーの断線が生じて半導体
装置の信頼性が低下する。よって、本発明はハンダ付け
工程での加熱によりパッケージにクラックが発生しない
信頼性の高い半導体装置を提供することを目的とする。The semiconductor device described above has the following problems. That is,
In a semiconductor device that has been integrally sealed with a resin, the inside of the silver paste that bonds the chip to the die pad remains moist. When this semiconductor device is mounted on a substrate and heated to about 240 ° C. for soldering, the water contained in the silver paste is vaporized and expanded. Due to the stress generated at this time, the chip and the die pad are separated. When this peeling further progresses, cracks occur in the package as shown in FIG. When the chip and the die pad are peeled off, the chip is damaged, or the wire breaks due to cracks, which lowers the reliability of the semiconductor device. Therefore, an object of the present invention is to provide a highly reliable semiconductor device in which cracks do not occur in the package due to heating in the soldering process.
【０００４】[0004]
【課題を解決するための手段】本発明は、これらの課題
を解決するために成された半導体装置である。すなわ
ち、リードフレームのダイパッド上にチップを搭載し、
このチップとリードフレームとをワイヤーにて接続し、
これら全体を樹脂で一体封止して成る半導体装置におい
て、ダイパッドの上面に複数の突起を設ける。この突起
上にチップを搭載することで、チップとダイパッドとの
間に間隙を設け、一体封止する樹脂をこの間隙にも充填
させるものである。The present invention is a semiconductor device made to solve these problems. That is, the chip is mounted on the die pad of the lead frame,
Connect this chip and the lead frame with a wire,
In a semiconductor device formed by integrally sealing all of these with resin, a plurality of protrusions are provided on the upper surface of the die pad. By mounting a chip on this protrusion, a gap is provided between the chip and the die pad, and the resin for integrally sealing is also filled in this gap.
【０００５】[0005]
【作用】チップは、ダイパッド上に設けられた突起の上
面に銀ペーストで接着されている。これにより、吸水性
の高い銀ペーストをチップの下面全体に塗布することな
く、突起の上面に塗布するだけですむ。したがって、ハ
ンダ付け工程により半導体装置を加熱した場合、銀ペー
スト内で水分が気化して発生する膨張応力が小さい。さ
らに、ダイパッドの上面に形成された突起上にチップを
搭載しているので、チップとダイパッドとの間に間隙が
形成される。この間隙に一体封止した樹脂が入り込むた
め、チップとダイパッドとの密着性が向上する。The chip is adhered to the upper surface of the protrusion provided on the die pad with silver paste. As a result, it is only necessary to apply the highly water-absorbing silver paste to the upper surface of the projection without applying it to the entire lower surface of the chip. Therefore, when the semiconductor device is heated by the soldering process, the expansion stress generated by vaporization of water in the silver paste is small. Furthermore, since the chip is mounted on the protrusion formed on the upper surface of the die pad, a gap is formed between the chip and the die pad. Since the resin integrally sealed enters the gap, the adhesion between the chip and the die pad is improved.
【０００６】[0006]
【実施例】以下に本発明の実施例を図面に基づいて説明
する。図１は本発明の半導体装置を説明する概略断面
図、図２は本発明のダイパッドを説明する斜視図であ
る。図１に示すように、リードフレーム１のほぼ中央に
位置するダイパッド２上にチップ３が搭載されている。
このチップ３とリードフレーム１はワイヤー４にて電気
的に接続されており、このリードフレーム１とダイパッ
ド２上のチップ３とワイヤー４との全体を例えばトラン
スファーモールド法により樹脂５にて一体封止してい
る。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view illustrating a semiconductor device of the present invention, and FIG. 2 is a perspective view illustrating a die pad of the present invention. As shown in FIG. 1, a chip 3 is mounted on a die pad 2 located approximately in the center of a lead frame 1.
The chip 3 and the lead frame 1 are electrically connected by a wire 4, and the entire chip 3 and the wire 4 on the lead frame 1, the die pad 2 are integrally sealed with a resin 5 by, for example, a transfer molding method. is doing.
【０００７】このダイパッド２の上面には図２の斜視図
に示すように、突起６が例えばその四隅に形成されてい
る。この突起６一つの大きさは、直径約１ｍｍ、高さが
約２０μｍである。また、この突起６はダイパッド２を
リードフレーム１の高さより低くする、いわゆるディプ
レスの工程と同時に形成できる。このダイパッド２の上
面に設けられた突起６上には少量の銀ペースト７が塗布
されており、これを接着材としてチップ３が搭載されて
いる。As shown in the perspective view of FIG. 2, protrusions 6 are formed on the upper surface of the die pad 2, for example, at its four corners. The size of each protrusion 6 is about 1 mm in diameter and about 20 μm in height. The protrusion 6 can be formed at the same time as the so-called depressing step of lowering the die pad 2 from the height of the lead frame 1. A small amount of silver paste 7 is applied on the protrusions 6 provided on the upper surface of the die pad 2, and the chip 3 is mounted using this as a bonding material.
【０００８】なお、突起６の大きさは前記の数値に限定
されず、一体封止する時、軟化した樹脂５の充填圧力
で、チップ３がはずれない接着強度が得られる表面積が
あればよく、その高さは半導体装置の高さが大幅に増加
しない程度であればよい。また、突起６の個数および形
状はチップ３を安定よく保持できるものであればよい。The size of the protrusions 6 is not limited to the above-mentioned numerical values, and it is sufficient that the protrusions 6 have a surface area which can provide an adhesive strength to prevent the chips 3 from coming off by the filling pressure of the softened resin 5 when integrally sealed. The height may be such that the height of the semiconductor device does not increase significantly. The number and shape of the protrusions 6 may be any as long as they can hold the chip 3 in a stable manner.
【０００９】このように突起６上にチップ３を搭載する
ことで、チップ３とダイパッド２との間に間隙が形成さ
れる。そして、全体を樹脂５で一体封止すると同時にこ
の間隙の側面側から樹脂５が入り込み、チップ３の下面
にも充填される。このチップ３の下面に充填された樹脂
５は接着性がよいため、チップ３とダイパッド２とが強
固に接着する。By mounting the chip 3 on the protrusion 6 in this manner, a gap is formed between the chip 3 and the die pad 2. Then, the whole body is integrally sealed with the resin 5, and at the same time, the resin 5 enters from the side surface side of this gap and is also filled in the lower surface of the chip 3. Since the resin 5 with which the lower surface of the chip 3 is filled has good adhesiveness, the chip 3 and the die pad 2 are firmly bonded.
【００１０】次に、本発明の他の実施例を図３、図４に
基づいて説明する。図３は本発明の他の実施例を説明す
る概略断面図、図４は本発明の他の実施例のダイパッド
を説明する斜視図である。この半導体装置の構成は、前
記説明した実施例と同様、リードフレーム１のダイパッ
ド２上にチップ３が搭載されており、このチップ３がワ
イヤー４にてリードフレーム１と配線されている。そし
て、これら全体を樹脂５にて一体封止したものである。Next, another embodiment of the present invention will be described with reference to FIGS. FIG. 3 is a schematic sectional view for explaining another embodiment of the present invention, and FIG. 4 is a perspective view for explaining a die pad of another embodiment of the present invention. In this semiconductor device, the chip 3 is mounted on the die pad 2 of the lead frame 1, and the chip 3 is wired to the lead frame 1 by the wire 4, as in the above-described embodiment. Then, the whole of them is integrally sealed with the resin 5.
【００１１】このダイパッド２の上面には、図４の斜視
図に示すように複数の突起６と貫通孔８が設けられてい
る。この突起６上にチップ３を搭載すれば、ダイパッド
２とチップ３との間に間隙ができる。この状態で樹脂５
にて一体封止すると、軟化した樹脂５がこの間隙の側面
側から入り込む。さらに、ダイパッド２の下面側からも
この貫通孔８を通過して樹脂５が入り込むことができ
る。したがって、半導体装置の小型化を図るため突起６
の高さを低くして、チップ３とダイパッド２との間隙が
狭くなっても容易に樹脂５が充填されることになる。A plurality of projections 6 and through holes 8 are provided on the upper surface of the die pad 2 as shown in the perspective view of FIG. If the chip 3 is mounted on the protrusion 6, a gap is created between the die pad 2 and the chip 3. Resin 5 in this state
Then, the softened resin 5 enters from the side surface side of this gap. Further, the resin 5 can also enter from the lower surface side of the die pad 2 through the through holes 8. Therefore, in order to reduce the size of the semiconductor device, the protrusion 6
The resin 5 can be easily filled even if the height of is reduced to narrow the gap between the chip 3 and the die pad 2.
【００１２】この貫通孔８は、ダイパッド２のプレス成
形と同時に設ければよい。また、図４に示す貫通孔８は
ダイパッド２のほぼ中央部分の４箇所に設けられている
が、本発明はこれに限定されず、軟化した樹脂５が通過
しやすい形状であればよい。The through hole 8 may be provided at the same time as the die pad 2 is press-molded. Further, the through holes 8 shown in FIG. 4 are provided at four locations in the substantially central portion of the die pad 2, but the present invention is not limited to this, and may have a shape that allows the softened resin 5 to easily pass through.
【００１３】前記いずれの実施例においても、突起６と
チップ３とが、この４つの突起６の上面のみで接触する
ことになる。したがって、この接触部分に少量の銀ペー
スト７が塗布されているだけなので、銀ペースト７内の
水分が気化して発生する膨張応力が小さい。さらに、ダ
イパッド２とチップ３との間隙に樹脂５が充填されるの
で、ダイパッド２とチップ３との密着性が向上する。よ
って、半導体装置を基板に実装し、ハンダ付けで加熱さ
れても、ダイパッド２とチップ３が剥離することがな
く、パッケージのクラックが発生しない。In any of the above-mentioned embodiments, the projection 6 and the chip 3 are in contact with each other only on the upper surfaces of the four projections 6. Therefore, since only a small amount of silver paste 7 is applied to this contact portion, the expansion stress generated by vaporization of water in silver paste 7 is small. Furthermore, since the resin 5 is filled in the gap between the die pad 2 and the chip 3, the adhesion between the die pad 2 and the chip 3 is improved. Therefore, even if the semiconductor device is mounted on a substrate and heated by soldering, the die pad 2 and the chip 3 do not separate, and the package does not crack.
【００１４】[0014]
【発明の効果】以上説明したように、本発明の半導体装
置によれば、ハンダ付け工程で２４０℃前後に加熱され
てもチップとダイパッドが剥離しないので、パッケージ
にクラックが発生しない。したがって、ワイヤーの断線
やチップの破損がなく、半導体装置の信頼性が向上す
る。As described above, according to the semiconductor device of the present invention, the chip and the die pad are not separated even when heated to about 240 ° C. in the soldering process, so that the package is not cracked. Therefore, there is no wire breakage or chip damage, and the reliability of the semiconductor device is improved.
【図１】本発明の半導体装置を説明する概略断面図であ
る。FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device of the present invention.
【図２】本発明のダイパッドを説明する斜視図である。FIG. 2 is a perspective view illustrating a die pad of the present invention.
【図３】本発明の他の実施例を説明する概略断面図であ
る。FIG. 3 is a schematic sectional view illustrating another embodiment of the present invention.
【図４】他の実施例のダイパッドを説明する斜視図であ
る。FIG. 4 is a perspective view illustrating a die pad of another embodiment.
【図５】従来の半導体装置を説明する概略断面図であ
る。FIG. 5 is a schematic cross-sectional view illustrating a conventional semiconductor device.
【図６】加熱処理によるクラックが発生した状態を説明
する概略断面図である。FIG. 6 is a schematic cross-sectional view illustrating a state in which a crack is generated by heat treatment.
１ リードフレーム ２ ダイパッド ３ チップ ４ ワイヤー ５ 樹脂 ６ 突起 ７ 銀ペースト ８ 貫通孔 1 lead frame 2 die pad 3 chip 4 wire 5 resin 6 protrusion 7 silver paste 8 through hole
Claims (1)
たチップと、前記チップと前記リードフレームとを接続
したワイヤーと、これら全体を一体封止した樹脂とから
成る半導体装置において、 前記ダイパッドの上面に複数の突起を設け、前記突起上
に前記チップを搭載することで、前記チップと前記ダイ
パッドとの間に間隙を形成し、前記間隙にも前記樹脂を
充填させたことを特徴とする半導体装置。1. A semiconductor device comprising a chip mounted on a die pad of a lead frame, a wire connecting the chip and the lead frame, and a resin encapsulating all of them, wherein a plurality of chips are provided on an upper surface of the die pad. And a chip is mounted on the protrusion to form a gap between the chip and the die pad, and the gap is filled with the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3233845A JPH0547988A (en) | 1991-08-21 | 1991-08-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3233845A JPH0547988A (en) | 1991-08-21 | 1991-08-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547988A true JPH0547988A (en) | 1993-02-26 |
Family
ID=16961472
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3233845A Pending JPH0547988A (en) | 1991-08-21 | 1991-08-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547988A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0722550U (en) * | 1993-09-22 | 1995-04-21 | サンケン電気株式会社 | Semiconductor device |
| EP1134806A3 (en) * | 2000-03-16 | 2003-11-12 | Microchip Technology Inc. | Stress reducing lead-frame for plastic encapsulation |
| US9613888B2 (en) | 2013-04-02 | 2017-04-04 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor module |
| IT202000008119A1 (en) * | 2020-04-16 | 2021-10-16 | St Microelectronics Srl | Production of integrated devices from lead-frames with spacers |
| US11916353B2 (en) | 2020-04-16 | 2024-02-27 | Stmicroelectronics (Grenoble 2) Sas | Electronic chip support device and corresponding manufacturing method |
-
1991
- 1991-08-21 JP JP3233845A patent/JPH0547988A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0722550U (en) * | 1993-09-22 | 1995-04-21 | サンケン電気株式会社 | Semiconductor device |
| EP1134806A3 (en) * | 2000-03-16 | 2003-11-12 | Microchip Technology Inc. | Stress reducing lead-frame for plastic encapsulation |
| US9613888B2 (en) | 2013-04-02 | 2017-04-04 | Mitsubishi Electric Corporation | Semiconductor device and semiconductor module |
| IT202000008119A1 (en) * | 2020-04-16 | 2021-10-16 | St Microelectronics Srl | Production of integrated devices from lead-frames with spacers |
| US11916353B2 (en) | 2020-04-16 | 2024-02-27 | Stmicroelectronics (Grenoble 2) Sas | Electronic chip support device and corresponding manufacturing method |
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