JPS60113932A - Assembling process of resin sealed semiconductor device - Google Patents

Assembling process of resin sealed semiconductor device

Info

Publication number
JPS60113932A
JPS60113932A JP58222679A JP22267983A JPS60113932A JP S60113932 A JPS60113932 A JP S60113932A JP 58222679 A JP58222679 A JP 58222679A JP 22267983 A JP22267983 A JP 22267983A JP S60113932 A JPS60113932 A JP S60113932A
Authority
JP
Japan
Prior art keywords
semiconductor chip
die pads
leads
chip
plastic film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58222679A
Other languages
Japanese (ja)
Inventor
Masaharu Takeuchi
竹内　正晴
Tomoharu Yamauchi
山内　智晴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP58222679A priority Critical patent/JPS60113932A/en
Publication of JPS60113932A publication Critical patent/JPS60113932A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49558—Insulating layers on lead frames, e.g. bridging members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve productivity by means of lowering the chip position by a method wherein, in a leadframe composed of die pads fixing to a semiconductor chip and internal leads opposing to the die pads, the die pads are omitted to stick a plastic film on the lower surface of each inner leads while a chip is fixed on the position corresponding to the die pads to be wire-bonded with the leads opposing to the chip. CONSTITUTION:The die pads for loading a semiconductor chip 2 normally provided on a leadframe 11 is omitted and the die pads eliminating the leads 11b comprising the leadframe 11 are held and opposingly arranged. Next a plastic film 12 sticked on the lower surface of the leads 11b is omitted and a semiconductor chip 2 is fixed on the film 12 corresponding to the die pads to connect an electrode wiring provided on the semiconductor chip 2 to the leads 11b using metallic wirings 3. Through these procedures, the position of the chip 2 is lowered by means of omitting the normally used die pads to resin-seal the whole body while exposing the ends of the leads 11b.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、半導体チップをリードフレームにワイヤボ
ンドし装着する、樹脂封止半導体装置の組立方法に関す
る０ 〔従来技術〕 従来のこの種の半導体装置の組立方法による、樹脂封止
前の半導体装置を、第１図及び第２図に平面図及び断面
図で示す。（１）はリードフレームで、ダイパッド部（
ｌａ）、多数のリード部（１ｂ）及び連結枠部（ＩＣ）
とからなっている。（２）はダイパッド部（１ａ）に接
着されだ工Ｃチップなどの半導体チップ、（３）は半導
体チップ（２）とリード部（１１））とにワイヤボンデ
ィングされた金属細線、（４）はリード部（ｌｂ）群上
に接着されたプラスチックフィルムである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for assembling a resin-sealed semiconductor device in which a semiconductor chip is wire-bonded and mounted on a lead frame. [Prior Art] A conventional semiconductor device of this type FIGS. 1 and 2 show a plan view and a cross-sectional view of a semiconductor device before resin encapsulation according to the assembly method. (1) is the lead frame, and the die pad part (
la), a large number of lead parts (1b) and a connecting frame part (IC)
It consists of (2) is a semiconductor chip such as a die pad (1a) bonded to the die pad part (1a), (3) is a thin metal wire wire-bonded to the semiconductor chip (2) and the lead part (11), and (4) is It is a plastic film glued onto the lead part (lb) group.

上記半導体装置の従来の組立方法は、次のようにしてい
た。まず、リードフレーム（４）をプレス機にかけ、第
２図に示すように、ダイパッド部（１ａ）をリード部（
１ｂ）の厚さだけリードフレーム（４）面７５虻ら沈め
る。これは、後工程でワイヤボンディングされた金属細
線（３）が半導体チップ（２）の周辺部やダイパッド部
（１ａ）に接触し短絡するのを防ぐためである。つづい
て、半導体チップ（２）をダイパッド部（１ａ）上に接
着し、金属細線（３）でワイヤボンディングする。次に
、１対のプラスチックフィルム（４）をリード部（１ｂ
）群上に接着し、各リード部（１ｂ）を固定する。これ
により、組立途中や組立後の運搬によりリード部（１ｂ
）が揺れ、金属細線（３）が変形したり断線するのを防
ぐ。この後、成形金型により半導体チップ（２）部を樹
脂封止成形する。ついで、プレス機により連結枠部（１
Ｃ）を切取り各リード部（１ｂ）を分離する。The conventional method for assembling the semiconductor device is as follows. First, the lead frame (4) is put on a press machine, and the die pad part (1a) is inserted into the lead part (1a) as shown in FIG.
The lead frame (4) surface 75 is sunk by the thickness of 1b). This is to prevent the thin metal wire (3) wire-bonded in a later process from coming into contact with the peripheral part of the semiconductor chip (2) or the die pad part (1a) and causing a short circuit. Subsequently, the semiconductor chip (2) is adhered onto the die pad portion (1a) and wire bonded with a thin metal wire (3). Next, attach a pair of plastic films (4) to the lead part (1b
) to fix each lead part (1b). This makes it easier to transport the lead part (1b) during or after assembly.
) to prevent the thin metal wire (3) from deforming or breaking due to shaking. Thereafter, the semiconductor chip (2) portion is resin-sealed and molded using a molding die. Next, the connecting frame part (1
C) and separate each lead part (1b).

上記従来の方法では、金属細線（３）の短絡を防ぐだめ
のリードフレーム（１）のダイパッド部（１ａ）を沈め
加工する工程と、金属細線（３）の変形、断線を防ぐた
めのリード部（１ｂ）群へプラスチックフィルム（４）
を接着する工程との、２工程を要していた。The conventional method described above involves a step of sinking the die pad portion (1a) of the lead frame (1) to prevent short-circuiting of the thin metal wire (3), and a step of sinking the die pad portion (1a) of the lead frame (1) to prevent the thin metal wire (3) from deforming or breaking. Plastic film (4) to group (1b)
It required two steps: one to glue the two.

〔発明の概要〕[Summary of the invention]

この発明は、上記従来方法の欠点をなくするためになさ
れたもので、リードフレーム（１１にダイパッド部をな
くし、各リード部に下方からプラスチックフィルムを接
着し、このプラスチックフィルム上に半導体チップを接
着するようにし、ｌ工程により半導体チップを下げるこ
とと、各リード部の固定とができ、生産性を向上した樹
脂封止半導体装置の組立方法を提供することを目的とし
ている０ 〔発明の実施例〕 以下、この発明の一実施例による半導体装置の組立方法
を、第３凹及び第４図に樹脂封止前の半導体装置の平面
図及び断面図で示す。０υはリードフレームで、多数の
リード部（ｘｌｂ）及び連結枠部（ｌｌｃ）が設けられ
ており、従来のようなダイパッド部はなくされている。This invention was made in order to eliminate the drawbacks of the conventional method described above.The die pad part is eliminated from the lead frame (11), a plastic film is bonded to each lead part from below, and a semiconductor chip is bonded onto this plastic film. It is an object of the present invention to provide a method for assembling a resin-sealed semiconductor device, which can lower the semiconductor chip and fix each lead part by a step I, and improves productivity.0 [Embodiments of the Invention] ] Below, a method for assembling a semiconductor device according to an embodiment of the present invention is shown in a plan view and a cross-sectional view of the semiconductor device before resin sealing in Fig. 3 and Fig. 4. (xlb) and a connecting frame part (llc), and the conventional die pad part is eliminated.

各リード部（］ｌｌｂの内方側下面にプラスチックフィ
ルムα力を接着し固定する。このプラスチックフィルム
θη上の中央に半導体チップ（２）を接着し、金属細線
（３）を半導体チップ（２）と各リード部（１１ｂ）に
ワイヤボンディングする。A plastic film α force is adhered and fixed to the inner lower surface of each lead part (]llb. A semiconductor chip (2) is adhered to the center of this plastic film θη, and a thin metal wire (3) is attached to the semiconductor chip (2). and wire bonding to each lead part (11b).

この後、リードフレームを成形金型に入れ、半導体チッ
プ（２）部を樹脂封止成形する。ついで、プレス機によ
り連結枠部（ｌｌｃ）を切取り各リード部（１１ｂ）を
分離する。Thereafter, the lead frame is placed in a mold, and the semiconductor chip (2) portion is sealed and molded with resin. Next, the connecting frame portion (llc) is cut out using a press machine to separate each lead portion (11b).

このように、リードフレームθυの各リード部（１１１
））の下部にプラスチックフィルム（ゆを接着し、この
プラスチックフィルム＠上に半導体チップ（２）を接着
することにより、半導体チップ（２）はリードフレーム
０Ｄ上面からその板厚分だけ沈んだことになる。こうし
て、従来のようなリードフレーム（１）のダイパッド部
（ｌａ）の沈め加工の工程が省かれ、リード部（ｘｌｂ
）の揺れを防ぎ金属細線（３）の保護と半導体チップ（
２）を沈めるための工程が１工程でできる。In this way, each lead part (111
By gluing a plastic film (Y) to the bottom of the lead frame 0D and gluing the semiconductor chip (2) onto this plastic film, the semiconductor chip (2) is sunk from the top surface of the lead frame 0D by the thickness of the plastic film. In this way, the conventional step of sinking the die pad part (la) of the lead frame (1) is omitted, and the lead part (xlb
) to prevent shaking of the thin metal wire (3) and protect the semiconductor chip (
2) can be done in one step.

なお、上記実施例では、半導体チップ（２）としてＩＣ
チップの場合を示したが、樹脂封止形の半導体チップで
あれば他の種の半導体チップ、例えばトランジスタアレ
イの場合にも適用できるものである。Note that in the above embodiment, the semiconductor chip (2) is an IC.
Although the case of a chip is shown, the invention can also be applied to other types of semiconductor chips, such as transistor arrays, as long as they are resin-sealed semiconductor chips.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明の方法によれば、リードフレー
ムにはダイパッド部を省き、各リード部の内方側の下面
にプラスチックフィルムを接着し、このプラスチックフ
ィルム上の中央部に半導体チップを接着するようにした
ので、半導体チップを下げることと、各リード部の内方
側の固定が１工程ででき、生産性が向上される。As described above, according to the method of the present invention, the die pad part is omitted from the lead frame, a plastic film is adhered to the inner lower surface of each lead part, and a semiconductor chip is adhered to the center part on this plastic film. As a result, lowering the semiconductor chip and fixing the inner side of each lead portion can be done in one step, improving productivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図及び第２図は従来の樹脂封止半導体装置の組立方
法を示す樹脂封止前の半導体装置の平面図及び正面断面
図、第３図及び第４図はこの発明の一実施例による樹脂
封止半導体装置の組立方法を示す樹脂封止前の半導体装
置の平面図及び正面断面図である。 ２・・・半導体チップ、３・・・金属細線、１１・・・
リードフレーム、ｌｌｂ・・・リード部、１２・・・プ
ラスチックフィルム なお、図中同一符号は同−又は相当部分を示す○代理人
　大岩増雄1 and 2 are a plan view and a front cross-sectional view of a semiconductor device before resin encapsulation, showing a conventional method of assembling a resin-sealed semiconductor device, and FIGS. 3 and 4 are according to an embodiment of the present invention. FIG. 2 is a plan view and a front cross-sectional view of a semiconductor device before being resin-sealed, illustrating a method for assembling a resin-sealed semiconductor device. 2... Semiconductor chip, 3... Metal thin wire, 11...
Lead frame, llb...Lead part, 12...Plastic film Note that the same reference numerals in the drawings indicate the same or equivalent parts○Representative: Masuo Oiwa

Claims (1)

【特許請求の範囲】[Claims] リードフレームに装着された半導体チップ部を樹脂封止
する半導体装置の組立方法において、上記リードフレー
ムにはダイパッド部を省いており、リードフレームの各
リード部の内方側の下面にプラスチックフィルムを接着
し、このプラスチックフィルム上の中央部に上記半導体
チップを接着し、この半導体チップと上記各リード部を
それぞれ金属細線によりワイヤボンドすることを特徴と
する樹脂封止半導体装置の組立方法。In a semiconductor device assembly method in which a semiconductor chip mounted on a lead frame is sealed with resin, the die pad part is omitted from the lead frame, and a plastic film is bonded to the lower surface of the inner side of each lead part of the lead frame. A method for assembling a resin-sealed semiconductor device, characterized in that the semiconductor chip is adhered to the center of the plastic film, and the semiconductor chip and each lead are wire-bonded using thin metal wires.
JP58222679A 1983-11-26 1983-11-26 Assembling process of resin sealed semiconductor device Pending JPS60113932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58222679A JPS60113932A (en) 1983-11-26 1983-11-26 Assembling process of resin sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58222679A JPS60113932A (en) 1983-11-26 1983-11-26 Assembling process of resin sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS60113932A true JPS60113932A (en) 1985-06-20

Family

ID=16786220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58222679A Pending JPS60113932A (en) 1983-11-26 1983-11-26 Assembling process of resin sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS60113932A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63170945U (en) * 1987-04-27 1988-11-07
JPS63272043A (en) * 1987-04-30 1988-11-09 Mitsui Haitetsuku:Kk Semiconductor device and manufacture thereof
US5057456A (en) * 1988-08-23 1991-10-15 Bull, S.A. Method of manufacturing a tab semiconductor package by securing a thin insulating frame to inner leads of the package
US5508232A (en) * 1994-02-07 1996-04-16 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834934A (en) * 1981-08-26 1983-03-01 Toshiba Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5834934A (en) * 1981-08-26 1983-03-01 Toshiba Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63170945U (en) * 1987-04-27 1988-11-07
JPS63272043A (en) * 1987-04-30 1988-11-09 Mitsui Haitetsuku:Kk Semiconductor device and manufacture thereof
JPH0583178B2 (en) * 1987-04-30 1993-11-25 Mitsui High Tec
US5057456A (en) * 1988-08-23 1991-10-15 Bull, S.A. Method of manufacturing a tab semiconductor package by securing a thin insulating frame to inner leads of the package
US5508232A (en) * 1994-02-07 1996-04-16 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device

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