JPH06209071A - Resin sealed type semiconductor device and its manufacture - Google Patents

Resin sealed type semiconductor device and its manufacture

Info

Publication number
JPH06209071A
JPH06209071A JP5003393A JP339393A JPH06209071A JP H06209071 A JPH06209071 A JP H06209071A JP 5003393 A JP5003393 A JP 5003393A JP 339393 A JP339393 A JP 339393A JP H06209071 A JPH06209071 A JP H06209071A
Authority
JP
Japan
Prior art keywords
resin
chip
chips
semiconductor chip
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5003393A
Other languages
Japanese (ja)
Inventor
Takaaki Hayashi
孝明 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP5003393A priority Critical patent/JPH06209071A/en
Publication of JPH06209071A publication Critical patent/JPH06209071A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent the occurrence of delamination between an inter-chip resin and package resin which may result in package cracks. CONSTITUTION:A first semiconductor chip 3 and second semiconductor chip 4 having a larger size than the chip 3 are counterposed to each other and their electrodes pads 3a and 4a are connected to each other through solder bumps 7. Then the space between the chips 3 and 4 is filled up with a reinforcing inter-chip resin 2 by injecting the resin 2 into the space and the peripheral side face of the resin 2 is flushed with that of the chip 3 by removing the fillet section (fin-like section) squeezed out from the chip 3. After the second chip 4 is die-bonded to the chip mounting section 6b of a lead frame 6 and outside connecting terminals 4b on the chip 4 are connected to leads 6a through bonding wires 5, the whole body is molded with a package resin 1 except parts of the leads 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数の半導体チップを
対面させ電気的に結合させた後に、全体を樹脂でパッケ
ージしたマルチチップモジュールの半導体装置およびそ
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a multi-chip module in which a plurality of semiconductor chips are faced to each other and electrically coupled to each other, and then the whole is packaged with a resin, and a manufacturing method thereof.

【0002】[0002]

【従来の技術】図4に従来のこの種のプラスチックパッ
ケージのマルチチップモジュールの半導体装置の断面構
造を示す。
2. Description of the Related Art FIG. 4 shows a sectional structure of a conventional semiconductor device of a multi-chip module of this type of plastic package.

【0003】第1の半導体チップ3とそれよりも大きい
第2の半導体チップ4とを、それぞれの電極パッド3
a,4a間に半田バンプ7を介在させる状態で対面配置
し、半田バンプ7をリフローすることにより両半導体チ
ップ3,4を電気的に接続し、次いで、第1の半導体チ
ップ3の周囲からディスペンサーなどを用いてチップ間
樹脂2を両半導体チップ3,4間の隙間に注入充填す
る。チップ間樹脂2を硬化させた後に、第2の半導体チ
ップ4の背面をリードフレーム6におけるチップマウン
ト部6bにダイボンドする。そして、第2の半導体チッ
プ4の周辺部に引き出された外部接続端子4bとリード
フレーム6におけるリード6aとをボンディングワイヤ
5を介して電気的に接続する。さらに、リード6aの一
部を除いて全体をパッケージ樹脂1のトランスファモー
ルドによって封止し、パッケージ樹脂1の外部に露出し
ているリード6aの部分を切断し折り曲げることによ
り、マルチチップモジュールの半導体装置を完成させて
いる。
The first semiconductor chip 3 and the second semiconductor chip 4 larger than the first semiconductor chip 3 are connected to the respective electrode pads 3
a and 4a are arranged face-to-face with the solder bumps 7 interposed therebetween, the solder bumps 7 are reflowed to electrically connect the two semiconductor chips 3 and 4, and then the dispenser is placed around the first semiconductor chip 3. The inter-chip resin 2 is injected and filled into the gap between the semiconductor chips 3 and 4 by using, for example, After the resin 2 between chips is cured, the back surface of the second semiconductor chip 4 is die-bonded to the chip mount portion 6b of the lead frame 6. Then, the external connection terminals 4b drawn out to the peripheral portion of the second semiconductor chip 4 and the leads 6a in the lead frame 6 are electrically connected via the bonding wires 5. Further, the entire lead 6a except for a part thereof is sealed by transfer molding of the package resin 1, and the portion of the lead 6a exposed to the outside of the package resin 1 is cut and bent, whereby a semiconductor device of a multi-chip module is formed. Has been completed.

【0004】両半導体チップ3,4間の隙間に予めチッ
プ間樹脂2を注入充填し硬化させておくのは、パッケー
ジ樹脂1のモールド時に加えられる圧力によって半田バ
ンプ7が押し潰されたり各半導体チップ3,4が破損さ
れたりすることがないように補強するためである。
It is necessary to inject and fill the inter-chip resin 2 in the gap between the two semiconductor chips 3 and 4 in advance and to cure the resin so that the solder bumps 7 are crushed by the pressure applied at the time of molding the package resin 1 or each semiconductor chip is crushed. This is to reinforce so that 3 and 4 will not be damaged.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上記構
成のマルチチップモジュールの半導体装置の場合、製造
後の信頼性試験において、図5に示すように、チップ間
樹脂2とパッケージ樹脂1との界面において剥離が発生
し、やがてパッケージクラック8等の不良を引き起こす
原因となることが判明した。
However, in the case of the semiconductor device of the multi-chip module having the above structure, in the reliability test after manufacturing, as shown in FIG. 5, at the interface between the inter-chip resin 2 and the package resin 1. It was found that peeling occurred and eventually caused defects such as package cracks 8 and the like.

【0006】このことは、パッケージ樹脂1と半導体チ
ップ3,4やリードフレーム6との密着性に比べて、パ
ッケージ樹脂1とチップ間樹脂2との密着性が劣ってい
ることを示している。
This indicates that the adhesiveness between the package resin 1 and the inter-chip resin 2 is inferior to the adhesiveness between the package resin 1 and the semiconductor chips 3, 4 and the lead frame 6.

【0007】両半導体チップ3,4間の隙間に対するチ
ップ間樹脂2の充填が第1の半導体チップ3の周囲から
染み込ませるようにして行われるため、両半導体チップ
3,4の界面だけでなく第1の半導体チップ3の外側に
もチップ間樹脂2が薄く広がり、フィレット部(ひれ状
部)2aを形成する結果、チップ間樹脂2とパッケージ
樹脂1との接触面積が大きくなる。チップ間樹脂2とパ
ッケージ樹脂1との界面は上記のように密着性が弱いも
のであり、フィレット部2aの存在により両者の接触面
積が大きくなっていると、それだけ界面剥離が生じやす
いのである。
Since the inter-chip resin 2 is filled in the gap between the two semiconductor chips 3 and 4 so that the resin is soaked from the periphery of the first semiconductor chip 3, not only the interface between the two semiconductor chips 3 and 4 but also the The inter-chip resin 2 spreads thinly on the outer side of the semiconductor chip 3 of No. 1 to form the fillet portion (fin-shaped portion) 2a. As a result, the contact area between the inter-chip resin 2 and the package resin 1 becomes large. The interface between the inter-chip resin 2 and the package resin 1 has weak adhesion as described above, and if the contact area between the two is large due to the presence of the fillet portion 2a, the interface peeling is more likely to occur.

【0008】チップ間樹脂2としてパッケージ樹脂1と
の密着性の良好なものを採用できれば上記の問題は解消
されるのであるが、チップ間樹脂2はトランスファモー
ルド時の温度,圧力に耐えて半田バンプ7にかかる応力
を緩和することができるものである必要があり、このよ
うな2つの条件を同時に満たす適当な代替樹脂を得るこ
とはきわめてむずかしいことである。逆に、パッケージ
樹脂1の方を変えることも考えられるが、これまで長い
間すぐれた実績のある樹脂の種類を変えることは、成形
性等の点で不安があり、これも非常にむずかしいことで
ある。
The above problem can be solved if a resin having good adhesiveness to the package resin 1 can be adopted as the resin 2 between chips, but the resin 2 between chips can withstand the temperature and pressure at the time of transfer molding and the solder bumps. It is necessary to be able to relieve the stress applied to No. 7, and it is extremely difficult to obtain a suitable alternative resin that simultaneously satisfies these two conditions. On the contrary, it is possible to change the package resin 1, but it is very difficult to change the type of resin that has been used for a long time in terms of moldability, which is also very difficult. is there.

【0009】本発明は、このような事情に鑑みて創案さ
れたものであって、パッケージクラックの原因となるチ
ップ間樹脂とパッケージ樹脂との層間剥離を防止するこ
とを目的とする。
The present invention was devised in view of such circumstances, and an object thereof is to prevent delamination between the resin between chips and the package resin, which causes a package crack.

【0010】[0010]

【課題を解決するための手段】本発明に係る樹脂封止半
導体装置は、第1の半導体チップとそれより大きい第2
の半導体チップとが対面配置された状態で両者間に介在
された半田バンプを介して電気的に接続されているとと
もに前記第1および第2の両半導体チップ間の隙間に補
強用のチップ間樹脂が充填硬化されており、全体がパッ
ケージ樹脂でモールドされた樹脂封止半導体装置であっ
て、前記両半導体チップ間の隙間に充填硬化された前記
チップ間樹脂の周側面が前記第1の半導体チップの周側
面とほぼ面一に形成されていることを特徴とするもので
ある。
A resin-sealed semiconductor device according to the present invention comprises a first semiconductor chip and a second semiconductor chip larger than the first semiconductor chip.
Is electrically connected via a solder bump interposed between the two semiconductor chips in a state of being face-to-face, and a resin between the chips for reinforcement in the gap between the first and second semiconductor chips. Is a resin-encapsulated semiconductor device that is entirely filled and cured with a package resin, and a peripheral side surface of the inter-chip resin that is filled and cured in the gap between the two semiconductor chips is the first semiconductor chip. It is characterized in that it is formed substantially flush with the peripheral side surface of the.

【0011】また、本発明に係る樹脂封止半導体装置の
製造方法は、第1の半導体チップとそれより大きい第2
の半導体チップとを対面配置した状態で両者間に介在し
た半田バンプをもって電気的に接続する工程と、前記第
1および第2の両半導体チップ間の隙間に補強用のチッ
プ間樹脂を注入充填する工程と、その充填したチップ間
樹脂を硬化させる工程と、前記第2の半導体チップ上で
前記第1の半導体チップよりも外側にはみ出したチップ
間樹脂のフィレット部を除去してチップ間樹脂の周側面
を第1の半導体チップの周側面と面一にする工程と、全
体をパッケージ樹脂でモールドする工程とを含むことを
特徴とするものである。
The method of manufacturing a resin-encapsulated semiconductor device according to the present invention includes a first semiconductor chip and a second semiconductor chip larger than the first semiconductor chip.
And electrically connecting the semiconductor chip with the semiconductor chip with a solder bump interposed therebetween, and injecting and filling a resin between chips for reinforcement into the gap between the first and second semiconductor chips. And a step of curing the filled inter-chip resin, and removing the fillet portion of the inter-chip resin protruding outside the first semiconductor chip on the second semiconductor chip to remove the periphery of the inter-chip resin. The method is characterized by including the step of making the side surface flush with the peripheral side surface of the first semiconductor chip, and the step of molding the whole with a package resin.

【0012】[0012]

【作用】本発明の樹脂封止半導体装置によれば、両半導
体チップ間に充填硬化された補強用のチップ間樹脂の周
側面と第1の半導体チップの周側面とが面一となってお
り、あとからモールドされたパッケージ樹脂とチップ間
樹脂との接触面積が最小限となっているから、パッケー
ジ樹脂とチップ間樹脂とが密着性の良くないものであっ
ても、界面剥離が生じにくくなる。
According to the resin-sealed semiconductor device of the present invention, the peripheral side surface of the inter-chip resin for reinforcement filled and cured between both semiconductor chips and the peripheral side surface of the first semiconductor chip are flush with each other. Since the contact area between the package resin and the resin between chips that is molded afterwards is minimized, interfacial peeling is less likely to occur even if the package resin and the resin between chips are poor in adhesion. .

【0013】また、本発明の樹脂封止半導体装置の製造
方法によれば、補強用のチップ間樹脂が第1の半導体チ
ップより外側にはみ出してフィレット部(ひれ状部)が
生じても、そのフィレット部を除去してチップ間樹脂の
周側面を第1の半導体チップの周側面と面一にするか
ら、チップ間樹脂の流動性を高めて両半導体チップ間へ
のチップ間樹脂の充填を容易にしながらも、あとからモ
ールドするパッケージ樹脂とチップ間樹脂との界面剥離
を生じにくくする。
Further, according to the method of manufacturing a resin-sealed semiconductor device of the present invention, even if the inter-chip resin for reinforcement protrudes outside the first semiconductor chip to form a fillet portion (fin-like portion), Since the fillet portion is removed so that the peripheral side surface of the inter-chip resin is flush with the peripheral side surface of the first semiconductor chip, the fluidity of the inter-chip resin is enhanced and the inter-chip resin can be easily filled between both semiconductor chips. However, the interface peeling between the package resin to be molded later and the inter-chip resin is less likely to occur.

【0014】[0014]

【実施例】以下、本発明に係る樹脂封止半導体装置およ
びその製造方法の一実施例を図面に基づいて詳細に説明
する。図1はマルチチップモジュールの半導体装置の完
成状態での構造を示す断面図、図2および図3は製造過
程の途中段階での構造を示す断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a resin-sealed semiconductor device and a method of manufacturing the same according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing a structure of a semiconductor device of a multi-chip module in a completed state, and FIGS. 2 and 3 are sectional views showing a structure at an intermediate stage of a manufacturing process.

【0015】図2に示すように、まず、第1の半導体チ
ップ3とそれよりも大きい第2の半導体チップ4とを半
田バンプ7を介して電気的に接続する。すなわち、第2
の半導体チップ4の電極パッド4a上に半田層を形成
し、その半田層に第1の半導体チップ3の電極パッド3
aが接触するようにして第1の半導体チップ3と第2の
半導体チップ4とを対面配置させる。そして、熱を加え
ることにより半田層をリフローさせて電極パッド3aと
電極パッド4aとを半田バンプ7を介して電気的に接続
する。
As shown in FIG. 2, first, the first semiconductor chip 3 and the larger second semiconductor chip 4 are electrically connected via the solder bumps 7. That is, the second
A solder layer is formed on the electrode pad 4a of the semiconductor chip 4, and the electrode pad 3 of the first semiconductor chip 3 is formed on the solder layer.
The first semiconductor chip 3 and the second semiconductor chip 4 are arranged face-to-face so that a contacts. Then, the solder layer is reflowed by applying heat to electrically connect the electrode pad 3 a and the electrode pad 4 a via the solder bump 7.

【0016】次いで、第1の半導体チップ3の周囲から
ディスペンサーなどを用いて両半導体チップ3,4間の
隙間に補強用のチップ間樹脂2を染み込ませるようにし
て注入充填する。両半導体チップ3,4間の隙間に予め
チップ間樹脂2を注入充填し硬化させておくのは、後述
するところのパッケージ樹脂1のモールド時に加えられ
る圧力によって半田バンプ7が押し潰されたり各半導体
チップ3,4が破損されたりすることがないように補強
するためである。
Then, the inter-chip resin 2 for reinforcement is injected and filled from around the first semiconductor chip 3 into the gap between the two semiconductor chips 3 and 4 using a dispenser or the like. It is necessary to inject and fill the inter-chip resin 2 into the gap between the two semiconductor chips 3 and 4 in advance and to cure the resin 2 so that the solder bumps 7 are crushed by the pressure applied at the time of molding the package resin 1, which will be described later, or each semiconductor This is to reinforce the chips 3 and 4 so as not to be damaged.

【0017】チップ間樹脂2の注入充填に際しては、両
半導体チップ3,4を加熱することでチップ間樹脂2の
流動性を高めることにより、両半導体チップ3,4間の
隙間に対する充填を容易化している。
When the resin 2 between chips is injected and filled, the fluidity of the resin 2 between chips is increased by heating both semiconductor chips 3 and 4, thereby facilitating the filling of the gap between the semiconductor chips 3 and 4. ing.

【0018】しかし、このようにチップ間樹脂2の流動
性を高めることが原因で、チップ間樹脂2は両半導体チ
ップ3,4間の隙間だけでなく、第2の半導体チップ4
上において第1の半導体チップ3よりも広い範囲に薄く
拡がることになる。その後、チップ間樹脂2は硬化する
が、硬化したときの形状は図示のように第1の半導体チ
ップ3の周辺の外側に拡がるフィレット部(ひれ状部)
2aが形成された状態となっている。
However, due to the increase in the fluidity of the inter-chip resin 2 as described above, the inter-chip resin 2 is not only formed in the gap between the semiconductor chips 3 and 4, but also in the second semiconductor chip 4.
In the above, it spreads thinly over a wider area than the first semiconductor chip 3. After that, the inter-chip resin 2 is cured, but the shape when cured is a fillet portion (fin-shaped portion) that spreads outside the periphery of the first semiconductor chip 3 as shown in the figure.
2a has been formed.

【0019】このフィレット部2aをそのまま残してお
くと、後述するパッケージ樹脂1のモールドに際して、
チップ間樹脂2とパッケージ樹脂1との接触面積が大き
くなり、その接触界面での密着性が比較的弱いものであ
ることから、経年変化により界面剥離が生じやすく、パ
ッケージクラック等の不良を引き起こす原因となりやす
い。
If this fillet portion 2a is left as it is, when the package resin 1 described later is molded,
Since the contact area between the resin 2 between chips and the package resin 1 becomes large and the adhesion at the contact interface is relatively weak, the interface peeling easily occurs due to aging, which causes defects such as package cracks. It is easy to become.

【0020】そこで、第1の半導体チップ3の外側に拡
がったフィレット部2aを、図3に示すように、切削,
研磨などの機械的な方法や物理化学的なエッチング方法
によって除去し、チップ間樹脂2の周側面が第1の半導
体チップ3の周側面と面一になるように加工する。な
お、半田バンプ7はチップ間樹脂2に埋め込まれた状態
を保っている。
Therefore, as shown in FIG. 3, the fillet portion 2a expanded to the outside of the first semiconductor chip 3 is cut,
It is removed by a mechanical method such as polishing or a physicochemical etching method, and processed so that the peripheral side surface of the interchip resin 2 is flush with the peripheral side surface of the first semiconductor chip 3. The solder bumps 7 are kept embedded in the resin 2 between chips.

【0021】次いで、図1に示すように、第2の半導体
チップ4の背面をリードフレーム6におけるチップマウ
ント部6bにダイボンドする。そして、第2の半導体チ
ップ4の周辺部に引き出された外部接続端子4bとリー
ドフレーム6におけるリード6aの接続部とをボンディ
ングワイヤ5を介して電気的に接続する。さらに、リー
ド6aの一部を除いて全体をパッケージ樹脂1のトラン
スファモールドによって封止する。
Next, as shown in FIG. 1, the back surface of the second semiconductor chip 4 is die-bonded to the chip mount portion 6b of the lead frame 6. Then, the external connection terminal 4 b drawn out to the peripheral portion of the second semiconductor chip 4 and the connection portion of the lead 6 a in the lead frame 6 are electrically connected via the bonding wire 5. Further, the entire lead 6a except for a part is sealed by transfer molding of the package resin 1.

【0022】なお、パッケージ樹脂1としては、これま
で実績のあるものとして用いられてきたものを使用する
ものとし、特にチップ間樹脂2との密着性を考慮しなく
てもよい。また、チップ間樹脂2としてもパッケージ樹
脂1との密着性を考慮する必要は特にはなく、パッケー
ジ樹脂1のトランスファモールド時の温度,圧力に耐え
て半田バンプ7にかかる応力を緩和することができるも
のであればよい。このことは、フィレット部2aを除去
することに要する費用を補ってなお余りあるコストダウ
ンを図ることとなる。
As the package resin 1, what has been used as a proven product has been used, and it is not necessary to particularly consider the adhesion with the resin 2 between chips. Further, it is not necessary to consider the adhesiveness with the package resin 1 as the inter-chip resin 2, and the stress applied to the solder bumps 7 can be alleviated by withstanding the temperature and pressure of the package resin 1 during transfer molding. Anything will do. This compensates for the cost required for removing the fillet portion 2a, and further reduces the cost.

【0023】そして、最後に、パッケージ樹脂1の硬化
後において、パッケージ樹脂1の外部に露出しているリ
ード6aの部分を切断し折り曲げることにより、マルチ
チップモジュールの半導体装置を完成させる。
Finally, after the package resin 1 is hardened, the portions of the leads 6a exposed to the outside of the package resin 1 are cut and bent to complete the semiconductor device of the multichip module.

【0024】以上のようにして製造された樹脂封止半導
体装置は、フィレット部2aが除去されており、チップ
間樹脂2の周側面が第1の半導体チップ3の周側面と面
一となっていてパッケージ樹脂1との接触面積が大幅に
減少しているから、たとえチップ間樹脂2とパッケージ
樹脂1との密着性がそれほど良いものではなくても、チ
ップ間樹脂2とパッケージ樹脂1との界面における剥離
の発生を抑制することができ、パッケージクラック等の
不良を防止して半導体装置の信頼性を高めることができ
る。
In the resin-sealed semiconductor device manufactured as described above, the fillet portion 2a is removed, and the peripheral side surface of the inter-chip resin 2 is flush with the peripheral side surface of the first semiconductor chip 3. Since the contact area with the package resin 1 is significantly reduced, even if the adhesion between the chip resin 2 and the package resin 1 is not so good, the interface between the chip resin 2 and the package resin 1 is reduced. It is possible to suppress the occurrence of peeling in the semiconductor device, prevent defects such as package cracks, and improve the reliability of the semiconductor device.

【0025】なお、上記実施例においては説明を簡単に
するため第1の半導体チップ3が1つの場合で説明した
が、本発明はこれに限定されるものではなく、第2の半
導体チップ4に対して接続される第1の半導体チップ3
が2以上であってもよい。また、必ずしも両半導体チッ
プ3,4とも能動素子を有している必要はなく、いずれ
か一方が単にアルミニウム配線を形成したシリコン基板
であってもよい。
In the above embodiment, the case where the first semiconductor chip 3 is one has been described for simplification of description, but the present invention is not limited to this, and the second semiconductor chip 4 is used. First semiconductor chip 3 connected to
May be 2 or more. Further, both semiconductor chips 3 and 4 do not necessarily have to have active elements, and either one may be a silicon substrate on which aluminum wiring is simply formed.

【0026】[0026]

【発明の効果】本発明に係る樹脂封止半導体装置によれ
ば、チップ間樹脂とパッケージ樹脂との接触面積を最小
限としたので両者間の界面剥離が生じにくくなり、チッ
プ間樹脂およびパッケージ樹脂として特別に密着性の良
いものを採用しなくても、換言すれば、コストアップを
抑えながら、パッケージクラック等の不良の発生を防止
して半導体装置の信頼性を向上させることができる。
According to the resin-encapsulated semiconductor device of the present invention, since the contact area between the resin between chips and the package resin is minimized, the interfacial peeling between them is less likely to occur, and the resin between chips and the package resin are less likely to occur. In other words, even if a material having particularly good adhesion is not used, in other words, it is possible to prevent the occurrence of defects such as package cracks and improve the reliability of the semiconductor device while suppressing the cost increase.

【0027】また、本発明に係る樹脂封止半導体装置の
製造方法によれば、チップ間樹脂の流動性を高めて両半
導体チップ間へのチップ間樹脂の充填を容易にしながら
も、あとからモールドするパッケージ樹脂とチップ間樹
脂との界面剥離を生じにくくでき、パッケージクラック
等の不良の発生の少ない信頼性の高い樹脂封止半導体装
置を製造することができる。
Further, according to the method of manufacturing a resin-sealed semiconductor device according to the present invention, the fluidity of the resin between chips is increased to facilitate the filling of the resin between chips between the two semiconductor chips, but at the same time, the molding is performed later. It is possible to prevent the occurrence of interface peeling between the package resin and the resin between the chips, and it is possible to manufacture a highly reliable resin-encapsulated semiconductor device with few defects such as package cracks.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る樹脂封止半導体装置の
完成状態の構造を示す断面図である。
FIG. 1 is a sectional view showing a structure of a resin-sealed semiconductor device according to an embodiment of the present invention in a completed state.

【図2】実施例においてチップ間樹脂を注入充填した状
態を示す断面図である。
FIG. 2 is a cross-sectional view showing a state in which a resin between chips is injected and filled in an example.

【図3】実施例においてチップ間樹脂のフィレット部を
除去した状態を示す断面図である。
FIG. 3 is a cross-sectional view showing a state in which a fillet portion of resin between chips is removed in the example.

【図4】従来例に係るプラスチックパッケージのマルチ
チップモジュールの半導体装置を示す断面図である。
FIG. 4 is a sectional view showing a semiconductor device of a multi-chip module of a plastic package according to a conventional example.

【図5】従来例の半導体装置においてパッケージクラッ
クが生じた状態を示す断面図である。
FIG. 5 is a cross-sectional view showing a state in which a package crack has occurred in a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1……パッケージ樹脂 2……チップ間樹脂 2a……フィレット部(ひれ状部) 3……第1の半導体チップ 3a……電極パッド 4……第2の半導体チップ 4a……電極パッド 4b……外部接続端子 5……ボンディングワイヤ 6……リードフレーム 6a……リード 6b……チップマウント部 7……半田バンプ 8……パッケージクラック 1 ... Package resin 2 ... Chip-to-chip resin 2a ... Fillet part (fin part) 3 ... First semiconductor chip 3a ... Electrode pad 4 ... Second semiconductor chip 4a ... Electrode pad 4b. External connection terminal 5 ... Bonding wire 6 ... Lead frame 6a ... Lead 6b ... Chip mount part 7 ... Solder bump 8 ... Package crack

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 第1の半導体チップとそれより大きい第
2の半導体チップとが対面配置された状態で両者間に介
在された半田バンプを介して電気的に接続されていると
ともに前記第1および第2の両半導体チップ間の隙間に
補強用のチップ間樹脂が充填硬化されており、全体がパ
ッケージ樹脂でモールドされた樹脂封止半導体装置であ
って、前記両半導体チップ間の隙間に充填硬化された前
記チップ間樹脂の周側面が前記第1の半導体チップの周
側面とほぼ面一に形成されていることを特徴とする樹脂
封止半導体装置。
1. A first semiconductor chip and a second semiconductor chip, which is larger than the first semiconductor chip, are electrically connected to each other via solder bumps interposed therebetween in a state of being arranged facing each other. A resin-encapsulated semiconductor device in which the inter-chip resin for reinforcement is filled and cured in the gap between the second semiconductor chips, and the whole is molded with a package resin, and the gap between the semiconductor chips is filled and cured. A resin-encapsulated semiconductor device, wherein a peripheral side surface of the resin between chips thus formed is formed to be substantially flush with a peripheral side surface of the first semiconductor chip.
【請求項2】 第1の半導体チップとそれより大きい第
2の半導体チップとを対面配置した状態で両者間に介在
した半田バンプをもって電気的に接続する工程と、前記
第1および第2の両半導体チップ間の隙間に補強用のチ
ップ間樹脂を注入充填する工程と、その充填したチップ
間樹脂を硬化させる工程と、前記第2の半導体チップ上
で前記第1の半導体チップよりも外側にはみ出したチッ
プ間樹脂のフィレット部を除去してチップ間樹脂の周側
面を第1の半導体チップの周側面と面一にする工程と、
全体をパッケージ樹脂でモールドする工程とを含むこと
を特徴とする樹脂封止半導体装置の製造方法。
2. A step of electrically connecting a first semiconductor chip and a second semiconductor chip, which is larger than the first semiconductor chip, to each other with solder bumps interposed therebetween, and both the first and second semiconductor chips. A step of injecting and filling a resin between chips for reinforcement into a gap between the semiconductor chips, a step of curing the filled resin between chips, and a step of protruding to the outside of the first semiconductor chip on the second semiconductor chip. And removing the fillet portion of the resin between chips to make the peripheral side surface of the resin between chips flush with the peripheral side surface of the first semiconductor chip,
And a step of molding the entire body with a package resin.
JP5003393A 1993-01-12 1993-01-12 Resin sealed type semiconductor device and its manufacture Pending JPH06209071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5003393A JPH06209071A (en) 1993-01-12 1993-01-12 Resin sealed type semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5003393A JPH06209071A (en) 1993-01-12 1993-01-12 Resin sealed type semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH06209071A true JPH06209071A (en) 1994-07-26

Family

ID=11556120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5003393A Pending JPH06209071A (en) 1993-01-12 1993-01-12 Resin sealed type semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH06209071A (en)

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US6476502B2 (en) 1999-07-28 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
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KR100535932B1 (en) * 1997-03-10 2006-03-27 세이코 엡슨 가부시키가이샤 Electronic component and semiconductor device
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US7932612B2 (en) 1997-03-10 2011-04-26 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US7598619B2 (en) 1997-03-10 2009-10-06 Seiko Epson Corporation Electronic component and semiconductor device, method of fabricating the same, circuit board mounted with the same, and electronic appliance comprising the circuit board
US6476502B2 (en) 1999-07-28 2002-11-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and manufacturing method thereof
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