JPS6066836A - Sealed semiconductor device - Google Patents

Sealed semiconductor device

Info

Publication number
JPS6066836A
JPS6066836A JP58175999A JP17599983A JPS6066836A JP S6066836 A JPS6066836 A JP S6066836A JP 58175999 A JP58175999 A JP 58175999A JP 17599983 A JP17599983 A JP 17599983A JP S6066836 A JPS6066836 A JP S6066836A
Authority
JP
Japan
Prior art keywords
recess
resin
copper foil
semiconductor element
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58175999A
Other languages
Japanese (ja)
Inventor
Taro Fukui
太郎 福井
Shinobu Ikeno
池野　忍
Tsuyoshi Imazu
今津　強
Hideo Kawamura
英雄 河村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP58175999A priority Critical patent/JPS6066836A/en
Publication of JPS6066836A publication Critical patent/JPS6066836A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Abstract

PURPOSE:To prevent a semiconductor element from penetration of water even when resin is expanded or shrinked, by providing a recess on the surface of a circuit substrate, forming patterns of copper coil respectively on the central portion of the bottom of the recess and on the periphery surrounding the same, effecting a predetermined connection for the semiconductor element fixed on the central portion, covering the element and the ends of the connection with a metallic cap, and filling the gap defined between the cap and the side face of the recess with sealing resin. CONSTITUTION:A circuit substrate 1 is provided with a deep recess. A copper foil 2 is formed in a die bond section 3 at the center of the bottom face of the recess. The peripheral bonding section 2a surrounding the die bond section is also applied with a copper foil extending to the surface around the recess. Then a semiconductor element 4 is fixed on the copper foil 2 of the die bond section and is bonded to the peripheral copper foil through wires 5. The element 4 and the ends of the copper foil 2 are covered with a metallic cap 6. Then, a gap defined between the inner wall of the recess and the outer wall of the cap 6 is filled with resin to seal the same. Thus, the element 4 is not exposed to the effect by expansion or shrinking of the resin.

Description

【発明の詳細な説明】 〔技術分野〕 この発明は、能動電子部品（半導体、ＩＣ，ＬＳＩ）の
樹脂」−・１止構造を改善した封止半導体装置に関する
。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a sealed semiconductor device with an improved resin sealing structure for active electronic components (semiconductors, ICs, LSIs).

〔背景技術〕[Background technology]

］・ランジスタ、ＩＣ，ＬＳＩなどの半導体素子に対し
ては、温度・湿度などの外「１；環境から保護し、機械
的な振動・衝撃などによる破１１やデバイス特性の変化
を防止するため、金属・セラミックを用いる気密封止か
、エポキシ４Ｍ脂やシリコン樹脂を用いる樹脂封止が行
なわれている。封止の信頼性では、水を全く通さない気
密封止が優れているが、量産性に冨み、かつ安価である
という点から、現在では約８０％程度の素子が樹脂ノ、
１止されている。] - Semiconductor devices such as transistors, ICs, and LSIs should be protected from the environment, including temperature and humidity, and to prevent damage and changes in device characteristics due to mechanical vibrations and shocks. Hermetic sealing using metal/ceramic or resin sealing using epoxy 4M resin or silicone resin is used.In terms of sealing reliability, airtight sealing, which does not allow water to pass through at all, is superior, but mass production is difficult. Approximately 80% of the elements are currently made of resin, as it is rich in resin and inexpensive.
1 has been stopped.

樹脂を用いる封止法としては、■わ）体樹脂を熔解し、
圧力によフて金型に注入し封止する低圧トランスファー
成形法、■ボッティング、キャスティングと呼ばれる注
型法、および■冷開成形されたＢステージ状樹脂タブレ
ットを加熱溶融する方法が知られているが、量産性に優
れていることから、殆どの半導体素子は■の低圧１−ラ
ンスファー成形方式で封止されている。As a sealing method using resin,
The following methods are known: low-pressure transfer molding, in which molds are injected and sealed using pressure, ■ casting methods called botting and casting, and ■ methods in which cold-open molded B-stage resin tablets are heated and melted. However, most semiconductor devices are encapsulated using the low-pressure 1-transfer molding method (2) because of its superior mass productivity.

この低圧Ｉ・ランスファー成形力式で封止された半導体
素子では、半導体素子と４６ノ脂とか密着した構造であ
るため、■樹脂の硬化収縮応力や温瓜刃イクルによる膨
張収縮応力などの外力が半導体素子やボンディング部に
かかるため、素子やパッシベーション膜にクラックが入
る、■湿気が樹脂バルクおよびリード線と樹脂の界面を
通って拡散し、Ａ１配線を腐食する、などの問題がある
ほか、■金型の値段が高い、■金型と完成品との離型が
悪い、■ランナ一部分において樹脂のロスが発生ずる、
などの改善すべき課題をもっている。The semiconductor element sealed using this low-pressure I/transfer molding force method has a structure in which the semiconductor element and 46 resin are in close contact with each other. In addition to problems such as moisture being applied to semiconductor elements and bonding parts, cracks occur in the elements and passivation films, and moisture spreading through the resin bulk and the interface between the lead wire and resin, corroding the A1 wiring. ■The price of the mold is high.■The mold release between the mold and the finished product is poor.■Resin loss occurs in a part of the runner.
There are issues that need improvement, such as:

一方、注型法や樹脂タブレットを加熱溶融する方法は■
〜■の問題はなく、ハイブリッドＩＣやチップオンボー
トの素子封止に用いられているが、樹脂封止に伴う前記
■、■の問題を有している状況は変わらない。On the other hand, the casting method and the method of heating and melting resin tablets are ■
Although there is no problem of ~■ and it is used for encapsulating elements of hybrid ICs and chip-on-boards, the situation in which it has the above-mentioned problems of 1 and 2 associated with resin encapsulation remains unchanged.

〔発明の１」的〕 この発明は、従来の樹脂封止の欠点であった樹脂の膨張
・収縮による応力や湿気の侵入を防ぐことができ、安価
で信頼性に優れた封止半導体装置を提供することを目的
とする。[Objective of Invention 1] This invention can prevent the intrusion of stress and moisture caused by expansion and contraction of the resin, which were the drawbacks of conventional resin encapsulation, and provides an inexpensive and highly reliable encapsulated semiconductor device. The purpose is to provide.

〔発明の開示〕[Disclosure of the invention]

」二記目的を達成するために、この発明は、次のように
構成さている。すなわち、表面に回路パターンを有する
回路基板に凹みが形成されてぃζ、グイボンド部と回路
のボンディング部がこの凹み内に配設され、前記グイボ
ンド８１；に［Ｍ定された゛１′導体素子およびこの素
子と前記ボンディング部を結合するボンディングワイヤ
ーに全屈キ４・ツブが被せられていて、この金属キャッ
プと回路基板の凹みとの間に形成されている隙間に封止
樹脂が充填されているのである。以下にごれを、その実
施例をあられす図面に基いて詳しく述べる。In order to achieve the second object, the present invention is constructed as follows. That is, a recess is formed in a circuit board having a circuit pattern on its surface, a bonding part and a bonding part of the circuit are disposed in this recess, and a conductive element 1' with a The bonding wire that connects this element and the bonding portion is covered with a fully bent lug, and the gap formed between this metal cap and the recess of the circuit board is filled with sealing resin. It is. Examples of the present invention will be described in detail below with reference to the drawings.

第１図は、この発明にがかる封止半導体装置の一実施例
を示す断面図である。■は半導体素子−４の入る凹み１
ａを有する回路）、（板で、表面に銅箔２が回路パター
ン状に形成されている。凹み１ａにはダイポン１部３が
配設され、銅７１′ｊ回ｌｌ′８２のボンディング部２
ａもこの凹ｈ］　ａに臨んでいる。FIG. 1 is a sectional view showing an embodiment of a sealed semiconductor device according to the present invention. ■ is the recess 1 where the semiconductor element-4 is inserted.
a), (a board, on which a copper foil 2 is formed in the form of a circuit pattern. A dipon 1 part 3 is disposed in the recess 1a, and a bonding part 2 of copper 71'j times ll'82 is formed.
a also faces this concave h] a.

グイボンド部部３には半導体素子４が接着固定され、こ
の半導体素子とボンディング部２ａとはワイヤー５で結
合されている。半導体素子４およびワイヤー５には金属
キャップ６が被セられでいる。A semiconductor element 4 is adhesively fixed to the bonding part 3, and the semiconductor element and the bonding part 2a are connected with a wire 5. The semiconductor element 4 and the wire 5 are covered with a metal cap 6.

そして、この金属キャップ６と回路基板の凹み１ａとの
間に形成されている隙間には封止樹脂７が充填されてい
る。A sealing resin 7 is filled in the gap formed between the metal cap 6 and the recess 1a of the circuit board.

第２図は、別の実施例を示すものであって、回路基板の
厚みが一定の封止チップ構造の断面図である。すなわち
、図にみるように、この場合、回路基板１′は、金属層
１ｂの上に絶縁層ＩＣが重ね合わせられた板状のもので
あって、凹み１ａを作るよう屈曲加工されてなる。その
他の部分は、第１図の場合と同じであるので、図中、第
１図と同一の符合部分は同一部分をあられず。FIG. 2 shows another embodiment, and is a cross-sectional view of a sealed chip structure in which the thickness of the circuit board is constant. That is, as shown in the figure, in this case, the circuit board 1' is in the form of a plate in which an insulating layer IC is superimposed on a metal layer 1b, and is bent to form a recess 1a. The other parts are the same as in FIG. 1, so the same reference numerals in the figure as in FIG. 1 do not refer to the same parts.

〔発明のリノ果〕[The fruit of invention]

上にみたように、この発明の封止半導体装置では、半導
体素子は、その上に金属キャップが被ゼられ、この金属
キャップの周囲に樹脂を充填することによって気密封止
されているので、樹脂の硬化収縮応力や温度サイクルに
よる樹脂の膨張収縮応力などの外力を受けないという利
点がある。半導体およびワイヤーは透湿性のない全屈キ
４・ツブでおおわれており、かつ金属キャップと回路基
板の間は厚く樹脂封止されているので、外部からの湿気
の侵入も殆どなくすることができる。また、従来、フラ
ットな基板」二に搭載した半導体を液状樹脂で封止する
場合には、加熱硬化が完了するまでの間樹脂が流動し拡
がらないよ・うにするため、枠体が必要であったが、こ
の発明の％Ｊ止半導体装置では、回路基板に凹みが形成
されていて、この凹みと金属キ４・ツブの間に樹脂をＡ
１止するＪ、う乙こしているので、このような枠体が不
要となる。As seen above, in the sealed semiconductor device of the present invention, the semiconductor element is covered with a metal cap and hermetically sealed by filling the resin around the metal cap. It has the advantage that it is not subject to external forces such as the curing and shrinkage stress of the resin and the expansion and contraction stress of the resin due to temperature cycles. The semiconductor and wires are covered with a non-moisture-permeable fully flexible tube, and the space between the metal cap and the circuit board is sealed with a thick resin, which almost eliminates the intrusion of moisture from the outside. . In addition, conventionally, when sealing a semiconductor mounted on a flat substrate with liquid resin, a frame is required to prevent the resin from flowing and spreading until heating and curing is completed. However, in the %J stop semiconductor device of the present invention, a recess is formed in the circuit board, and a resin is inserted between the recess and the metal key 4.
1 Stop J, since it is lying, there is no need for such a frame.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図はこの発明の二つの実施例をあられ
ず断面図である。 １．１′・・・回路基板　１ａ・・・凹の　２・・・銅
７ｔｉ２ａ・・・ボンディング部　３・・・グイボンド
部　４・・半導体素子　５・・・ボンディングワイヤー
−６・・・金属キャップ　７・・・封止樹脂　１］〕・
・・金属層　ＩＣ・・・絶縁層 代理人　弁理士　松　本　武　彦1 and 2 are cross-sectional views of two embodiments of the invention. 1.1'... Circuit board 1a... Concave 2... Copper 7ti2a... Bonding part 3... Gui bond part 4... Semiconductor element 5... Bonding wire -6... Metal cap 7... Sealing resin 1]]
...Metal layer IC...Insulating layer Agent Patent attorney Takehiko Matsumoto

Claims (1)

【特許請求の範囲】[Claims] （１）表面に回路パターンを有する回路基板に凹みが形
成されていて、ダイボンド部と回路のボンディング部が
この凹み内に配設され、前記グイボンドａ［≦にＩＭＩ
定された半導体素子およびこの素子とｉｉＩ記ボンディ
ング部を結合するボンディングワイヤーに金属キャップ
が被せられていて、この金属キャップと回路基板の凹み
との間に形成されている隙Ｌｊ、ｒｌに封止樹脂が売場
されていることを特徴とする１・ｊ正半導体装置。(1) A recess is formed in a circuit board having a circuit pattern on the surface, and a die bonding part and a circuit bonding part are arranged in this recess, and the IMI
A metal cap is placed over the defined semiconductor element and the bonding wire that connects this element to the bonding portion described in iii, and the gaps Lj and rl formed between the metal cap and the recess of the circuit board are sealed. A 1.j positive semiconductor device characterized by having a resin sales area.
JP58175999A 1983-09-22 1983-09-22 Sealed semiconductor device Pending JPS6066836A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58175999A JPS6066836A (en) 1983-09-22 1983-09-22 Sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58175999A JPS6066836A (en) 1983-09-22 1983-09-22 Sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS6066836A true JPS6066836A (en) 1985-04-17

Family

ID=16005934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58175999A Pending JPS6066836A (en) 1983-09-22 1983-09-22 Sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS6066836A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995020244A1 (en) * 1994-01-21 1995-07-27 Nippon Carbide Kogyo Kabushiki Kaisha Package for electronic element
WO2012064708A1 (en) * 2010-11-12 2012-05-18 Apple Inc. Unitary housing for electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995020244A1 (en) * 1994-01-21 1995-07-27 Nippon Carbide Kogyo Kabushiki Kaisha Package for electronic element
US5635672A (en) * 1994-01-21 1997-06-03 Nippon Carbide Kogyo Kabushiki Kaisha Package for electronic element
WO2012064708A1 (en) * 2010-11-12 2012-05-18 Apple Inc. Unitary housing for electronic device
US8730656B2 (en) 2010-11-12 2014-05-20 Apple Inc. Unitary housing for electronic device
US10118560B2 (en) 2010-11-12 2018-11-06 Apple Inc. Unitary housing for electronic device
US10696235B2 (en) 2010-11-12 2020-06-30 Apple Inc. Unitary housing for electronic device
US11505131B2 (en) 2010-11-12 2022-11-22 Apple Inc. Unitary housing for electronic device

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