JPH08288428A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH08288428A JPH08288428A JP7095256A JP9525695A JPH08288428A JP H08288428 A JPH08288428 A JP H08288428A JP 7095256 A JP7095256 A JP 7095256A JP 9525695 A JP9525695 A JP 9525695A JP H08288428 A JPH08288428 A JP H08288428A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor device
- semiconductor element
- lead frame
- die pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 229920005989 resin Polymers 0.000 claims abstract description 33
- 239000011347 resin Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 238000007789 sealing Methods 0.000 abstract description 6
- 229920001187 thermosetting polymer Polymers 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 239000002390 adhesive tape Substances 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910002026 crystalline silica Inorganic materials 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止型半導体装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来の樹脂封止型半導体装置はまず、図
４ａに示す様に、リードフレーム１のダイパッド４に半
導体素子３をマウントし金等でできたワイヤ５により半
導体素子３とリードフレーム１のリードとを結線する。
次に、図４（ｂ）に示す様に、封入工程において封止金
型７の内部に半導体素子３をマウントしたリードフレー
ム１を保持し、封止樹脂６を注入して図４（ｃ）に示す
様に、樹脂封止型半導体装置を製造している。2. Description of the Related Art In a conventional resin-sealed semiconductor device, as shown in FIG. 4A, a semiconductor element 3 is mounted on a die pad 4 of a lead frame 1 and a wire 5 made of gold or the like is used to mount the semiconductor element 3 and the lead frame. Connect with the lead of 1.
Next, as shown in FIG. 4B, in the encapsulation step, the lead frame 1 on which the semiconductor element 3 is mounted is held inside the encapsulation mold 7, and the encapsulation resin 6 is injected to form the encapsulation resin 6, as shown in FIG. As shown in, a resin-sealed semiconductor device is manufactured.
【０００３】しかし、近年の樹脂封止型半導体装置は、
半導体素子３の高集積化により多ピン化するとともに実
装密度向上の為に薄型化する傾向にあり樹脂封止が難し
くなっている。更に、半導体素子３の高集積化により半
導体素子３の発熱量が大きくなり半導体素子３がそれ自
体の発熱により使用中に電気的に不良となる。この対策
として、図５に示す様なダイパッド４を大きくし、リー
ドフレーム１のリードと貼り付けることにより樹脂封止
型半導体装置の低熱抵抗化を行っている。However, recent resin-encapsulated semiconductor devices are
Due to the high integration of the semiconductor element 3, the number of pins is increased and the semiconductor element 3 tends to be thinned to improve the mounting density, which makes resin sealing difficult. Further, as the degree of integration of the semiconductor element 3 increases, the amount of heat generated by the semiconductor element 3 increases and the semiconductor element 3 becomes electrically defective during use due to its own heat generation. As a countermeasure against this, the die pad 4 as shown in FIG. 5 is enlarged and attached to the leads of the lead frame 1 to reduce the thermal resistance of the resin-sealed semiconductor device.
【０００４】[0004]
【発明が解決しようとする課題】この従来の樹脂封止型
半導体装置の製造方法においては、ダイパッドがパッケ
ージの上方又は下方へ動き、半導体素子の露出やダイパ
ッドの露出を引き起こし、最悪の場合、ワイヤの断線を
引き起こし、電気的に不良となっている。これは、近年
の樹脂封止型半導体の薄型化により、その発生が著しく
なっているという問題点がある。In this conventional method of manufacturing a resin-sealed semiconductor device, the die pad moves upward or downward of the package to cause the exposure of the semiconductor element or the die pad, and in the worst case, the wire. Causing a wire breakage and is electrically defective. This is a problem in that the occurrence has become remarkable due to the recent thinning of resin-sealed semiconductors.
【０００５】また、半導体素子の高集積化により、半導
体素子の発熱量が大きくなる傾向にあり昇温による半導
体素子の故障の原因となっている。そのため、ダイパッ
ドの拡大等により半導体装置の低熱抵抗化を行っている
が、まだ不充分であり、更に低熱抵抗化する必要性があ
るという問題点がある。Further, as the degree of integration of semiconductor elements increases, the amount of heat generated by the semiconductor elements tends to increase, which causes failure of the semiconductor elements due to temperature rise. Therefore, the thermal resistance of the semiconductor device has been reduced by expanding the die pad and the like, but it is still insufficient and there is a problem that it is necessary to further reduce the thermal resistance.
【０００６】本発明の目的は、薄型で、ワイヤの断線が
なく低熱抵抗化が実現できる樹脂封止型半導体装置を提
供することにある。An object of the present invention is to provide a resin-sealed semiconductor device which is thin and which can realize a low thermal resistance without wire breakage.
【０００７】[0007]
【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、キャビティが成形された高熱伝導性樹脂と、
前記キャビティ内に固着されたリードフレームのダイパ
ッド沈めによって形成されたアイランドまたは前記高熱
伝導性樹脂の前記キャビティの位置に両面が露出するよ
うに埋設された金属ブロックと、この金属ブロックまた
は前記アイランド上に接着された半導体素子と、前記キ
ャビティが成形された高熱伝導性樹脂の上部に貼付けさ
れたリードフレームと、このリードフレームと前記半導
体素子を接続するボンディングワイヤと、前記キャビテ
ィが成形された高熱伝導性樹脂の上部で前記半導体素子
と前記ボンディングワイヤと前記リードフレームを封止
する熱硬化性樹脂とを有することを特徴とする。A resin-encapsulated semiconductor device of the present invention comprises a high thermal conductive resin having a cavity formed therein,
An island formed by submerging the die pad of the lead frame fixed in the cavity, or a metal block embedded so that both surfaces are exposed at the position of the cavity of the high thermal conductive resin, and a metal block on the metal block or the island. The bonded semiconductor element, the lead frame attached to the upper portion of the high thermal conductive resin in which the cavity is molded, the bonding wire connecting the lead frame and the semiconductor element, and the high thermal conductivity in which the cavity is molded. A thermosetting resin that seals the semiconductor element, the bonding wire, and the lead frame is provided on top of the resin.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will now be described with reference to the drawings.
【０００９】図１（ａ）〜（ｃ）は、本発明の第１の実
施例の製造方法を説明する工程順に示した断面図であ
る。本発明の第１の実施例の樹脂封止型半導体装置の製
造に当っては、まず、図１（ａ）に示す様に、パッケー
ジのリードフレーム１のダイパッド沈めによって形成さ
れたダイパッド４を固着するキャビティを有する下の部
分をあらかじめ高熱伝導性樹脂２により成形する。この
高熱伝導性樹脂２としては、汎用のエポキシ樹脂に結晶
性シリカを高充填化した樹脂等を用いることができる。
次に、図１（ｂ）に示す様に、あらかじめ成形した高熱
伝導性樹脂２にリードフレーム１を貼りつけリードフレ
ーム１のダイパッド４に半導体素子３を接着し、金等の
ワイヤ５により半導体素子３とリードフレーム１のリー
ドとを結線する。高熱伝導性樹脂２の成形体とリードフ
レーム１の貼り付けには、ポリイミド等の接着テープを
用いることができる。また、あらかじめ高熱伝導性樹脂
２を成形する際にリードフレーム１を埋め込んでおいて
もよい。次に、図１（ｃ）に示す様に、熱硬化性樹脂６
によりパッケージの上部を封止する。このとき、ダイパ
ッド４は高熱伝導性樹脂２に固定されているため、ダイ
パッド４の移動を防止するとともにパッケージ下部の高
熱伝導性樹脂２により樹脂封止型半導体装置の低熱抵抗
化を実現することができる。1 (a) to 1 (c) are sectional views showing the manufacturing method of the first embodiment of the present invention in order of process steps. In manufacturing the resin-encapsulated semiconductor device of the first embodiment of the present invention, first, as shown in FIG. 1A, a die pad 4 formed by submerging the die pad of the lead frame 1 of the package is fixed. The lower part having the cavity to be molded is previously molded with the high thermal conductive resin 2. As the high thermal conductive resin 2, a resin in which a general-purpose epoxy resin is highly filled with crystalline silica can be used.
Next, as shown in FIG. 1B, the lead frame 1 is attached to the high-thermal-conductivity resin 2 that has been molded in advance, the semiconductor element 3 is adhered to the die pad 4 of the lead frame 1, and the semiconductor element is bonded by the wire 5 such as gold. 3 and the lead of the lead frame 1 are connected. An adhesive tape such as polyimide can be used to attach the lead frame 1 and the molded body of the high thermal conductive resin 2. Alternatively, the lead frame 1 may be embedded in advance when the high thermal conductive resin 2 is molded. Next, as shown in FIG. 1C, the thermosetting resin 6
To seal the upper part of the package. At this time, since the die pad 4 is fixed to the high thermal conductive resin 2, it is possible to prevent the die pad 4 from moving and realize the low thermal resistance of the resin-sealed semiconductor device by the high thermal conductive resin 2 under the package. it can.
【００１０】図２は本発明の第２の実施例の断面図、図
３（ａ），（ｂ）は図２の第２の実施例に用いるパッケ
ージ下部の断面図及び平面図である。本発明の第２の実
施例の樹脂封止型半導体装置は、まず、図４（ａ），
（ｂ）に示すような半導体素子３を搭載する部分に金属
ブロック８をパッケージの下部にあらかじめ埋め込んだ
成形体の高熱伝導性樹脂２を成形しておく。この金属ブ
ロック８は銅等の熱伝導率の高い金属を用いるとよい。
次に、この金属ブロック８に半導体素子３を接着しワイ
ヤ５により半導体素子５とリードフレーム１のリードと
を結線する。次に、このパッケージの成形体の上部を通
常の熱硬化性樹脂６で封止する。この樹脂封止型半導体
装置は、金属ブロック８がパッケージの外部に露出して
いるため樹脂封止型半導体装置の熱抵抗を大幅に低下す
ることができる。FIG. 2 is a sectional view of a second embodiment of the present invention, and FIGS. 3 (a) and 3 (b) are a sectional view and a plan view of the lower portion of the package used in the second embodiment of FIG. The resin-encapsulated semiconductor device according to the second embodiment of the present invention is first described with reference to FIG.
The high heat conductive resin 2 of a molded body in which the metal block 8 is embedded in the lower part of the package in advance in the portion where the semiconductor element 3 is mounted as shown in (b) is molded. The metal block 8 is preferably made of a metal having a high thermal conductivity such as copper.
Next, the semiconductor element 3 is adhered to the metal block 8 and the wire 5 connects the semiconductor element 5 and the lead of the lead frame 1. Next, the upper part of the molded body of this package is sealed with a usual thermosetting resin 6. In this resin-sealed semiconductor device, the metal block 8 is exposed to the outside of the package, so that the thermal resistance of the resin-sealed semiconductor device can be significantly reduced.
【００１１】表１に本発明の実施例の効果を樹脂封止型
半導体装置の熱抵抗値と封入後の半導体素子のシフト量
を従来例と比較して示す。表１に示す様に、従来例と比
較して第１の実施例，第２の実施例が熱抵抗値，シフト
量ともに優れているとが認められる。Table 1 shows the effects of the embodiment of the present invention by comparing the thermal resistance value of the resin-sealed semiconductor device and the shift amount of the semiconductor element after encapsulation with the conventional example. As shown in Table 1, it is recognized that the first example and the second example are superior in the thermal resistance value and the shift amount as compared with the conventional example.
【００１２】[0012]
【表１】 [Table 1]
【００１３】[0013]
【発明の効果】以上説明したように本発明は、樹脂封止
型半導体装置のパッケージのリードフレームより下の部
分をあからじめ高熱伝導性樹脂により成形しこの高熱伝
導性樹脂に固定された高熱伝導性の金属に半導体素子を
搭載し、搭載後半導体素子の上部を熱硬化性樹脂により
封止することにより、半導体素子の封入後のシフトによ
るワイヤの断線不良を防止し、更に、樹脂封止型半導体
装置の熱抵抗を低下させ昇温による故障を防止できると
いう効果を有している。As described above, according to the present invention, the portion of the package of the resin-encapsulated semiconductor device below the lead frame is molded with a high heat conductive resin and fixed to the high heat conductive resin. By mounting the semiconductor element on a metal with high thermal conductivity and sealing the upper part of the semiconductor element with a thermosetting resin after mounting, wire disconnection failure due to shift after encapsulation of the semiconductor element is prevented. This has the effect of reducing the thermal resistance of the static semiconductor device and preventing failure due to temperature rise.
【図１】（ａ）〜（ｃ）は本発明の第１の実施例の製造
方法を説明する工程順に示した断面図である。FIG. 1A to FIG. 1C are cross-sectional views showing a manufacturing process of a first embodiment of the present invention in order of process steps.
【図２】本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.
【図３】（ａ），（ｂ）は図２の第２の実施例に用いる
パッケージ下部の断面図及び平面である。3A and 3B are a sectional view and a plan view of a lower portion of a package used in the second embodiment of FIG.
【図４】（ａ）〜（ｃ）は従来の樹脂封止型半導体装置
の一例の製造方法を説明する工程順に示した断面図であ
る。FIG. 4A to FIG. 4C are cross-sectional views showing, in order of steps, a method of manufacturing an example of a conventional resin-encapsulated semiconductor device.
【図５】従来の樹脂封止型半導体装置の他の例の断面図
である。FIG. 5 is a cross-sectional view of another example of a conventional resin-sealed semiconductor device.
１ リードフレーム ２ 高熱伝導性樹脂 ３ 半導体素子 ４ ダイパッド ５ ワイヤ ６ 熱硬化性樹脂 ７ 封止金型 ８ 金属ブロック ９ 接着テープ 1 Lead Frame 2 High Thermal Conductive Resin 3 Semiconductor Element 4 Die Pad 5 Wire 6 Thermosetting Resin 7 Sealing Mold 8 Metal Block 9 Adhesive Tape
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/31 // Ｂ２９Ｌ 31:34 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 23/31 // B29L 31:34
Claims (3)
と、前記キャビティ内に固着されたダイパッドと、この
ダイパッド上に接着された半導体素子と、前記キャビテ
ィが成形された高熱伝導性樹脂の上部に貼付されたリー
ドフレームと、このリードフレームと前記半導体素子を
接続するボンディングワイヤと、前記キャビティが成形
された高熱伝導性樹脂の上部で前記半導体素子と前記ボ
ンディングワイヤと前記リードフレームを封止する熱硬
化樹脂とを有することを特徴とする樹脂封止型半導体装
置。1. A high thermal conductive resin in which a cavity is molded, a die pad fixed in the cavity, a semiconductor element bonded on the die pad, and an upper portion of the high thermal conductive resin in which the cavity is molded. The attached lead frame, the bonding wire that connects the lead frame and the semiconductor element, and the heat that seals the semiconductor element, the bonding wire, and the lead frame above the high thermal conductive resin in which the cavity is molded. A resin-encapsulated semiconductor device comprising a cured resin.
パッド沈めによって形成されたアイランドであることを
特徴とする請求項１記載の樹脂封止型半導体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein the die pad is an island formed by sinking the die pad of a lead frame.
ビティの位置に両面が露出するように埋設された金属ブ
ロックであることを特徴とする請求項１記載の樹脂封止
型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein the die pad is a metal block that is buried in the cavity of the high thermal conductive resin so that both surfaces are exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7095256A JP2762954B2 (en) | 1995-04-20 | 1995-04-20 | Method for manufacturing resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7095256A JP2762954B2 (en) | 1995-04-20 | 1995-04-20 | Method for manufacturing resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08288428A true JPH08288428A (en) | 1996-11-01 |
| JP2762954B2 JP2762954B2 (en) | 1998-06-11 |
Family
ID=14132689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7095256A Expired - Lifetime JP2762954B2 (en) | 1995-04-20 | 1995-04-20 | Method for manufacturing resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2762954B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000183279A (en) * | 1998-10-05 | 2000-06-30 | Fuji Electric Co Ltd | Package for semiconductor element and manufacture thereof |
| KR100356787B1 (en) * | 1998-06-03 | 2003-01-24 | 주식회사 하이닉스반도체 | Semiconductor Package Manufacturing Method |
| JP2009194275A (en) * | 2008-02-18 | 2009-08-27 | Sumitomo Electric Ind Ltd | Assembling structure for packaging, and resin sealed semiconductor device |
| JP2020047696A (en) * | 2018-09-18 | 2020-03-26 | 日立化成株式会社 | Semiconductor device |
| US11699647B2 (en) | 2021-04-15 | 2023-07-11 | Infineon Technologies Ag | Pre-molded lead frames for semiconductor packages |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5455172A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Semiconductor device |
| JPS6420643A (en) * | 1987-07-15 | 1989-01-24 | Sumitomo Electric Industries | High heat sink semiconductor device |
| JPH04348550A (en) * | 1991-05-25 | 1992-12-03 | Sony Corp | Resin-sealed semiconductor device |
| JPH06268114A (en) * | 1993-03-12 | 1994-09-22 | Nippon Steel Corp | Semiconductor device |
| JPH06326236A (en) * | 1993-05-11 | 1994-11-25 | Toshiba Corp | Resin sealed semiconductor device |
| JPH06334068A (en) * | 1993-05-24 | 1994-12-02 | Toyota Autom Loom Works Ltd | Semiconductor package incorporating head spreader |
| JPH06342860A (en) * | 1993-06-02 | 1994-12-13 | Hitachi Cable Ltd | Semiconductor device and manufacture thereof |
-
1995
- 1995-04-20 JP JP7095256A patent/JP2762954B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5455172A (en) * | 1977-10-12 | 1979-05-02 | Toshiba Corp | Semiconductor device |
| JPS6420643A (en) * | 1987-07-15 | 1989-01-24 | Sumitomo Electric Industries | High heat sink semiconductor device |
| JPH04348550A (en) * | 1991-05-25 | 1992-12-03 | Sony Corp | Resin-sealed semiconductor device |
| JPH06268114A (en) * | 1993-03-12 | 1994-09-22 | Nippon Steel Corp | Semiconductor device |
| JPH06326236A (en) * | 1993-05-11 | 1994-11-25 | Toshiba Corp | Resin sealed semiconductor device |
| JPH06334068A (en) * | 1993-05-24 | 1994-12-02 | Toyota Autom Loom Works Ltd | Semiconductor package incorporating head spreader |
| JPH06342860A (en) * | 1993-06-02 | 1994-12-13 | Hitachi Cable Ltd | Semiconductor device and manufacture thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100356787B1 (en) * | 1998-06-03 | 2003-01-24 | 주식회사 하이닉스반도체 | Semiconductor Package Manufacturing Method |
| JP2000183279A (en) * | 1998-10-05 | 2000-06-30 | Fuji Electric Co Ltd | Package for semiconductor element and manufacture thereof |
| JP2009194275A (en) * | 2008-02-18 | 2009-08-27 | Sumitomo Electric Ind Ltd | Assembling structure for packaging, and resin sealed semiconductor device |
| JP2020047696A (en) * | 2018-09-18 | 2020-03-26 | 日立化成株式会社 | Semiconductor device |
| US11699647B2 (en) | 2021-04-15 | 2023-07-11 | Infineon Technologies Ag | Pre-molded lead frames for semiconductor packages |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2762954B2 (en) | 1998-06-11 |
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